View AT32AP7000-150CGU_3859203.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? high performance, low power avr ? 32 32-bit microcontroller ? 133 mhz clock frequency ? 16 kb instruction cache and 16 kb data caches ? memory management unit enab ling use of operating systems ? single-cycle risc instruction set including simd and dsp instructions ? java hardware acceleration ? multimedia co-processor ? vector multiplication unit for video acceleration thro ugh color-space conversion (yuv<->rgb), image scalin g and filtering, quarter pixel motion compensation ? multi-hierarchy bus system ? high-performance data transfers on separate buses for increased performance ? data memories ? 32kbytes sram ? external memory interface ? sdram, dataflash ? , sram, multi media card (mmc), secure digital (sd), compact flash, smart media, nand flash, ? direct memory access controller ? external memory access without cpu intervention ? interrupt controller ? individually maskable interrupts ? each interrupt request has a programm able priority and autovector address ? system functions ? power and clock manager ? crystal oscillator wit h phase-lock-loop (pll) ? watchdog timer ? real-time clock ? 6 multifunction timer/counters ? three external clock inputs, i/o pins, pwm, capture and various counting capabilities ? 4 universal synchronous/asynchrono us receiver/transmitters (usart) ? 115.2 kbps irda modulation and demodulation ? hardware and software handshaking ? 3 synchronous serial protocol controllers ? supports ac97, i2s, s/pdif, spi and generic frame-based protocols ? two-wire interface ? sequential read/write operations, philips? i2c? compatible ? liquid crystal disp lay (lcd) interface ? supports tft displays ? configurable pixel resolution supporting qcif/qvga/vga/svga configurations. ? image sensor interface ? 12-bit data interface for cmos cameras ? universal serial bus (usb) 2.0 high speed (480 mbps) device ? on-chip transceivers with physical interface ? 2 ethernet mac 10/100 mbps interfaces ? 802.3 ethernet me dia access controller ? supports media independent interf ace (mii) and reduced mii (rmii) ? 16-bit stereo audio dac ? sample rates up to 50 khz ? on-chip debug system ? nexus class 3 ? full speed, non-intrusive data and program trace ? runtime control and jtag interface ? package/pins ? 256-ball cabga 1.0mm pitch/160 gpio pins ? power supplies ? 1.65v to1.95v vddcore ? 3.0v to 3.6v vddio 32003e?avr32?05/06 avr ? 32 32-bit microcontroller at32ap7000 preliminary
2 32003e?avr32?05/06 at32ap7000 1. part description the at32ap7000 is a complete system-on-chip application processor with an avr32 risc processor running at frequencies up to 133 mhz. avr32 is a high-performance 32-bit risc microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density and high application performance. at32ap7000 implements a memory management unit (mmu) and a flexible interrupt controller supporting modern operating systems and real-time operating systems. the processor also includes a rich set of dsp and simd instructio ns, specially designed fo r multimedia and telecom applications. at32ap7000 incorporates sram memories on-chip for fast and secure access. for applica- tions requiring additional memory, external 16-bit sram is accessible. additionally, an sdram controller provides off-chip volat ile memory access as well as cont rollers for all industry standard off-chip non-volatile memories, like compact flash, multi media card (mmc), secure digital (sd)-card, smartcard, nand flash and atmel dataflash?. the direct memory access controller for all the serial peripherals enables data transfer between memories without processor intervention. this reduces the processor overhead when transfer- ring continuous and large data streams between modules in the mcu. the timer/counters includes three identical 16-bit timer/counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measure- ment, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. at32ap7000 also features an onboard lcd controller, supporting single and double scan monochrome and color passive stn lcd modul es and single scan acti ve tft lcd modules. on monochrome stn displays, up to 16 gray shades are supported using a time-based dither- ing algorithm and frame rate control (frc) method. this method is also used in color stn displays to generate up to 4096 colors. the lcd controller is programmable for supporting resolutions up to 2048 x 2048 with a pixel depth from 1 to 24 bits per pixel. a pixel co-processor provides color space conv ersions for images and video, in addition to a wide variety of hardware filter support the media-independent interface (mii) and reduced mii (rmii) 10/100 ethernet mac modules provides on-chip solutions for network-connected devices. synchronous serial controllers provide easy ac cess to serial communication protocols, audio standards like ac'97, i2s, i2c? and various spi modes. the modules support frame-based pro- tocols, like voip sip protocols. the java hardware acceleration implementation in avr32 allows for a very high java byte-code execution. avr32 implements java instructions in hardware, reusing the existing risc data path, which allows for a near-zero hardware overhead and cost with a very high performance. the image sensor interface supports cameras with up to 12-bit data buses and connects directly to the lcd interface through a separate bus. ps2 connectivity is provided for standa rd input devices like mice and keyboards.
3 32003e?avr32?05/06 at32ap7000 at32ap7000 integrates a class 3 nexus 2.0 on -chip debug (ocd) system, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. the c-compiler is closely linked to the architecture and is able to utilize code optimization fea- tures, both for size and speed.
4 32003e?avr32?05/06 at32ap7000 2. blockdiagram figure 2-1. blockdiagram system manager intc pwm tc0 tc1 ps2 twi ahb bus matrix dma controller 16kb sram 16kb sram ahb-apb bridge ahb-apb bridge configuration registers phy macb0 macb1 isi usb hmatrix smc sdram ecc avr32 ap cpu 16kb icache 16kb dcache mmu nexus class 3 ocd pixel coprocessor ssc0 ssc1 ssc2 pdc spi0 spi1 pdc usart0 usart1 usart2 usart3 pdc lcd controller dma ethernet mac1 dma ethernet mac0 dma image sensor interface dma usb hs device dma dac dma ac97c dma mci dma pio pio apb bus a apb bus b apb bus a peripheral dma controller sdram controller static memory controller ecc ebi input/output pins input/output pins
5 32003e?avr32?05/06 at32ap7000 2.1 processor and architecture 2.1.1 avr32ap cpu ? 32-bit load/store avr32b risc architecture. ? up to 15 general-purpose 32-bit registers. ? 32-bit stack pointer, program counter and link register reside in register file. ? fully orthogonal instruction set. ? privileged and unprivileged modes enabling efficient and secure operating systems. ? innovative instruction set together with variable instruction length ensu ring industry leading code density. ? dsp extention with saturating arithmetic, and a wide variet y of multiply instructions. ? simd extention for media applications. ? 7 stage pipeline allows one instruction per clock cycle for most instructions. ? java hardware acceleration. ? byte, half-word, word and double word memory access. ? unaligned memory access. ? shadowed interrupt context for int3 an d multiple interrupt priority levels. ? dynamic branch prediction and return address stac k for fast change-of-flow. ? coprocessor interface. ? full mmu allows for operating systems with memory protection. ? 16kbyte instruction and 16kbyte data caches. ? virtually indexed, physically tagged. ? 4-way associative. ? write-through or write-back. ? nexus class 3 on-chip debug system. ? low-cost nanotrace supported. 2.1.2 pixel coprocessor (pico) ? coprocessor coupled to the avr3 2 cpu core through the tcb bus. ? three parallel vector multiplicati on units (vmu) where each unit can: ? multiply three pixel componen ts with three coefficients. ? add the products from the multiplications together. ? accumulate the result or add an o ffset to the sum of the products. ? can be used for accelerating: ? image color space conversion. ?configurable conver sion coefficients. ? supports packed and planar input and output formats. ? supports subsampled input color spaces (i.e 4:2:2, 4:2:0). ? image filtering/scaling. ? configurable filter coefficients. ? throughput of one sample per cycle for a 9-tap fir filter. ? can use the built-in accumulator to extend the fir filter to more than 9-taps. ? can be used for bilinear/bicubic interpolations. ? mpeg-4/h.264 quarter pi xel motion compensation. ? flexible input pixel selector. ? can operate on numerous different image storage formats. ? flexible output pixel inserter. ? scales and saturates the results back to 8-bit pixel values.
6 32003e?avr32?05/06 at32ap7000 ? supports packed and planar output formats. ? configurable coefficien ts with flexible fixe d-point representation. 2.1.3 debug and test system ? ieee1149.1 compliant jtag and boundary scan ? direct memory access and programming capabilities through jtag interface ? extensive on-chip debug features in compliance with ieee-isto 5001-2003 (nexus 2.0) class 3 ? auxiliary port for high-speed trace information ? hardware support for 6 program and 2 data breakpoints ? unlimited number of softw are breakpoints supported ? advanced program, data, ownership, and watchpoint trace supported 2.1.4 dma controller ? 2 ahb master interfaces ? 3 channels ? software and hardware handshaking interfaces ? 11 hardware handshaking interfaces ? memory/non-memory periph erals to memory/non-mem ory peripherals transfer ? single-block dma transfer ? multi-block dma transfer ? linked lists ? auto-reloading ? contiguous blocks ? dma controller is always the flow controller ? additional features ? scatter and gather operations ? channel locking ? bus locking ? fifo mode ? pseudo fly-by operation 2.1.5 peripheral dma controller ? transfers from/to peripheral to/from any memory space without interven tion of the processor. ? next pointer support, forbids strong real -time constraints on buffer management. ? eighteen channels ? two for each usart ? two for each serial synchronous controller ? two for each serial peripheral interface 2.1.6 bus system ? ahb bus matrix with 10 masters and 8 slaves handled ? handles requests from the cpu icache, cpu dcache, ahb bridge, hisi, usb 2.0 controller, lcd controller, ethernet controller 0, ethe rnet controller 1, dma controller 0, dma
7 32003e?avr32?05/06 at32ap7000 controller 1, and to internal sram 0, inte rnal sram 1, apb a, apb b, ebi, usb, lcd controller and dma controller. ? round-robin arbitration (three modes supported: no default master, last accessed default master, fixed default master) ? burst breaking with slot cycle limit ? one address decoder provided per master ? 2 apb buses allowing each bus to run on different bus speeds. ? apb a intended to run on low clock speed s, with peripherals connected to the pdc. ? apb b intended to run on higher clock speeds, with peripherals connected to the dmac. ? ahb-ahb bridge providing a low-speed ahb bus running at the same speed as apba ? allows pdc transfers between a low-speed apb bus and a bus matrix of higher clock speeds figure 2-2 gives an overview of the bus system. all modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the power manager. the figure identifies the number of master and slave interfaces of each module connected to the ahb bus, and which dma controller is connected to which peripheral. figure 2-2. buses in avr32ap7000 ahb bus matrix ahb/apb bridge b ebi mac0 intram0 lcdc ahb/apb bridge a ahb / ahb bridge pdc dmac low speed ahb bus mac1 isi intram1 system peripheral bus a mmm m m mm 2*m 2*s 6*s pico usb20 device tc0 tc1 smc pioa pioe piod pioc piob usart0 usart1 usart2 usart3 ssc0 ssc1 ssc2 s m mci ac97c dac twi spi0 spi1 ps2 intc s data cache instr. cache avr32ap cpu usb macb1 macb0 isi config registers rtc system manager hmatrix sdramc ecc pwm system peripheral bus b s s s wdt eim pm connected to dmac connected to pdc master interface slave interface s m
8 32003e?avr32?05/06 at32ap7000 3. package and pinout figure 3-1. 256 cabga pinout top view bottom view ball a1 avr32 cabga256 a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16151413121110 9 8 7 6 5 4 3 2 1 table 3-1. cabga256 packag e pinout a1..t8 12345678 a vddio pe15 pe13 pe11 pe07 pe02 agndpll oscen_n b gndio pe16 pe12 pe09 pe04 pll0 avddosc pc30 c pd01 pd00 pe14 pe10 pe06 pe00 pll1 pc31 d pe17 pe18 pd02 pe08 pe03 gnd agndosc pc29 e px48 px50 px49 px47 pe05 pe01 xout32 pc28 f px32 px00 px33 vddio px51 avddpll xin0 pc27 g px04 vddcore px05 px03 px02 px01 xout0 pc26 h pd06 vddio pd07 pd05 pd04 pd03 gnd xin32 j trst_n tms tdi tck tdo pd09 pd08 evti_n k pa05 pa01 pa02 pa00 reset_n pa03 pa04 hsdp l pa09 pb25 vddio pa08 gnd pb24 agndusb vddcore m pa 1 4 pa 1 1 pa 1 3 pa 1 0 pa 1 2 v d d i o v d d i o g n d n pa18 pa16 pa17 pa15 pd14 gnd fsdm vbg
9 32003e?avr32?05/06 at32ap7000 p pa20 pa19 pa21 pd11 pd16 xout1 gnd pa25 r pa22 pd10 pa23 pd13 pd17 avddusb hsdm pa26 t vddio gnd pa24 pd12 pd15 xin1 fsdp vddio table 3-1. cabga256 packag e pinout a1..t8 table 3-2. cabga256 package pinout a9..t16 9 10111213141516 a pc23 pa06 pb21 pb16 pb13 pb11 gnd vddio b pc25 pc19 pb23 pb18 pb14 pb10 pc17 pc16 c pc24 pa07 pb22 pb17 pb12 pb09 pb07 pb08 d pc22 pc18 pb20 pb15 pb03 pb05 pb04 pb06 e vddio gnd pb19 pb00 px46 pb01 vddio pb02 f pc21 vddcore gnd px44 px42 px43 px40 px45 g pc20 pc15 pc14 pc10 pc11 pc13 pc12 vddcore h pc09 pc05 pc06 pe26 vddio pc07 px39 pc08 j pb27 px27 px28 px29 px30 vddcore gnd px31 k pa27 gnd px22 px23 px24 px26 vddio px25 l pa28 vddio pe24 px38 px18 px20 px21 px19 m pa29 pb28 pe20 px08 px34 px36 px37 px35 n pa30 px53 pe22 px06 px11 px15 px17 px16 p wake_n px41 pe21 px09 pb30 pc02 px13 px14 r pa31 px52 pe23 px07 pb29 pc00 pc04 gnd t pb26 pe25 pe19 px10 px12 pc01 pc03 vddio
10 32003e?avr32?05/06 at32ap7000 4. signals description the following table gives details on the signal name classified by peripheral. the pinout multi- plexing of these signals is given in section 10.7 . table 4-1. signal description list signal name function type active level comments power avddpll pll power supply power 1.65 to 1.95 v avddusb usb power supply power 1.65 to 1.95 v avddosc oscillator power supply power 1.65 to 1.95 v vddcore core power supply power 1.65 to 1.95 v vddio i/o power supply power 3.0 to 3.6v agndpll pll ground ground agndusb usb ground ground agndosc oscillator ground ground gnd ground ground clocks, oscillators, and pll?s xin0, xin1, xin32 crystal 0, 1, 32 input analog xout0, xout1, xout32 crystal 0, 1, 32 output analog pll0, pll1 pll 0,1 filter pin analog jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input trst_n test reset input low auxiliary port - aux mcko trace data output clock output mdo0 - mdo5 trace data output output mseo0 - mseo1 trace frame control output evti_n event in output low
11 32003e?avr32?05/06 at32ap7000 evto_n event out output low power manager - pm gclk0 - gclk4 generic clock pins output oscen_n oscillator enable input low reset_n reset pin input low wake_n wake pin input low external interrup t module - eim extint0 - extint3 external interrupt pins input nmi_n non-maskable interrupt pin input low ac97 controller - ac97c sclk ac97 clock signal input sdi ac97 receive signal output sdo ac97 transmit signal output sync ac97 frame synchronization signal input dac - dac data0 - data1 d/a data out output datan0 - datan1 d/a inverted data out output ethernet mac - macb0, macb1 col collision detect input crs carrier sense and data valid input mdc management data clock output mdio management data input/output i/o rxd0 - rxd3 receive data input rx_clk receive clock input rx_dv receive data valid input rx_er receive coding error input speed speed output txd0 - txd3 transmit data output table 4-1. signal description list signal name function type active level comments
12 32003e?avr32?05/06 at32ap7000 tx_clk transmit clock or reference clock output tx_en transmit enable output tx_er transmit coding error output external bus interface - ebi addr0 - addr25 address bus output cas column signal output low cfce1 compact flash 1 chip enable output low cfce2 compact flash 2 chip enable output low cfrnw compact flash read not write output data0 - data31 data bus i/o nandoe nand flash output enable output low nandwe nand flash write enable output low ncs0 - ncs5 chip select output low nrd read signal output low nwait external wait signal input low nwe0 write enable 0 output low nwe1 write enable 1 output low nwe3 write enable 3 output low ras row signal output low sda10 sdram address 10 line output sdck sdram clock output sdcke sdram clock enable output sdcs sdram chip select output low sdwe sdram write enable output low image sensor interface - isi data0 - data11 image sensor data input hsync horizontal synchronization input pclk image sensor data clock input table 4-1. signal description list signal name function type active level comments
13 32003e?avr32?05/06 at32ap7000 vsync vertical synchronization input lcd controller - lcdc cc lcd contrast control output data0 - data23 lcd data bus input dval lcd data valid output gpl0 - gpl7 lcd general purpose lines output hsync lcd horizontal synchronization output mode lcd mode output pclk lcd clock output pwr lcd power output vsync lcd vertical synchronization output mulitmedia card interface - mmci clk multimedia card clock output cmd0 - cmd1 multimedia card command i/o data0 - data7 multimedia card data i/o parallel input/output 2 - pioa, piob, pioc, piod, pioe p0 - p31 parallel i/o controller pioa i/o p0 - p30 parallel i/o controller piob i/o p0 - p31 parallel i/o controller pioc i/o p0 - p17 parallel i/o controller piod i/o p0 - p26 parallel i/o controller pioe i/o ps2 interface - psif clock0 - clock1 ps2 clock input data0 - data1 ps2 data i/o serial peripheral in terface - spi0, spi1 miso master in slave out i/o mosi master out slave in i/o npcs0 - npcs3 spi peripheral chip select i/o low table 4-1. signal description list signal name function type active level comments
14 32003e?avr32?05/06 at32ap7000 sck clock output synchronous serial contro ller - ssc0, ssc1, ssc2 rx_clock ssc receive clock i/o rx_data ssc receive data input rx_frame_sync ssc receive frame sync i/o tx_clock ssc transmit clock i/o tx_data ssc transmit data output tx_frame_sync ssc transmit frame sync i/o dma controller - dmac dmarq0 - dmarq3 dma requests input timer/counter - timer0, timer1 a0 channel 0 line a i/o a1 channel 1 line a i/o a2 channel 2 line a i/o b0 channel 0 line b i/o b1 channel 1 line b i/o b2 channel 2 line b i/o clk0 channel 0 external clock input input clk1 channel 1 external clock input input clk2 channel 2 external clock input input two-wire interface - twi scl serial clock i/o sda serial data i/o universal synchronous asynchronous receiver transmitter - usart0, usart1, usart2, usart3 clk clock i/o cts clear to send input rts request to send output rxd receive data input table 4-1. signal description list signal name function type active level comments
15 32003e?avr32?05/06 at32ap7000 txd transmit data output pulse width modulator - pwm pwm0 - pwm3 pwm output pins output universal serial bus device - usb ddm usb device port data - analog ddp usb device port data + analog table 4-1. signal description list signal name function type active level comments
16 32003e?avr32?05/06 at32ap7000 5. power considerations 5.1 power supplies the at32ap7000 has several types of power supply pins: ? vddcore pins: power the core , memories, and peripherals. voltage is 1.8v nominal. ? vddio pins: power i/o lines. voltage is 3.3v nominal. ? vddpll pin: powers the pll. voltage is 1.8v nominal. ? vddusb pin: powers the usb. voltage is 1.8v nominal. ? vddosc pin: powers the oscillat ors. voltage is 1.8v nominal. the ground pins gnd are common to vddcore and vddio. the ground pin for vddpll is gndpll, and the gnd pin for vddosc is gndosc. see ?electrical characteristics - tbd? on page 910 for power consumption on the various supply pins. 5.2 power supply connections special considerations should be made when connecting the power and ground pins on a pcb. figure 5-1 shows how this should be done. figure 5-1. connecting analog power supplies avddusb avddpll avddosc agndusb agndpll agndosc vddcore vcc_1v8 3.3uh c54 0.10u c55 0.10u c56 0.10u
17 32003e?avr32?05/06 at32ap7000 6. i/o line considerations 6.1 jtag pins the tms, tdi and tck pins have pull-up resistors. tdo is an output, driven at up to vddio, and have no pull-up resistor. the trst_n pin is used to initialize the embedded jtag tap controller when asserted at a low level. it is a schmitt input and integrates permanent pull-up resistor to vddio, so that it can be left unconnected for normal operations. 6.2 wake_n pin the wake_n pin is a schmitt trig ger input integr ating a permanent pull-up resistor to vddio. 6.3 reset_n pin the reset_n pin is a schmitt input and integrates a permanent pull-up resistor to vddio. as the product integrat es a power-on reset cell, the reset_n pin can be left unconnected in case no reset from the system needs to be applied to the product. 6.4 evti_n pin the evti_n pin is a schmitt input and integrates a non-programmable pull-up resistor to vddio. 6.5 twi pins when these pins are used for twi, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. when used as gpio-pins or used for other peripherals, the pins have the same characteristics as pio pins. 6.6 pio pins all the i/o lines integrate a programmable pull-up resistor . programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. after reset, i/o lines default as inputs with pull-up resistors enabled, ex cept when indicated otherwise in the column ?reset state? of the pio controller multiplexing tables.
18 32003e?avr32?05/06 at32ap7000 7. avr32 ap cpu rev: 1.0.0 this chapter gives an overview of the avr32 ap cpu. avr32 ap is an implementation of the avr32 architecture. a summary of the programming model, instruction set, caches and mmu is presented. for further details, see the avr32 architecture manual and the avr32 ap technical reference manual . 7.1 avr32 architecture avr32 is a new, high-performance 32-bit risc mi croprocessor architectu re, designed for cost- sensitive embedded applications, with particul ar emphasis on low power consumption and high code density. in addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the avr32 to be im plemented as low-, mid- or high-performance processors. avr32 extends the avr? family into the world of 32- and 64-bit applications. through a quantitative approach, a large set of industry recognized benchmarks has been com- piled and analyzed to achieve the best code density in its class. in addition to lowering the memory requirements, a compact code size also contributes to the core?s low power characteris- tics. the processor supports byte and half-word data types without penalty in code size and performance. memory load and store operations are provided for byte, half-word, word and double word data with automatic sign- or zero extension of half-word and byte data. in order to reduce code size to a minimum, so me instructions have multiple addressing modes. as an example, instructions with immediates often have a compact format with a smaller imme- diate, and an extended format with a larger immediate. in this way, the compiler is able to use the format giving the smallest code size. another feature of the instruction set is that frequently used instructions, like add, have a com- pact format with two operands as well as an extended format with three operands. the larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. load and store instructions have seve ral different formats in order to reduce code size and speed up execution. the register file is organized as sixteen 32-bi t registers and includes the program counter, the link register, and the stack pointer. in addition, register r12 is designed to hold return values from function calls and is used im plicitly by some instructions. 7.2 the avr32 ap cpu avr32 ap targets high-performance applications, and provides an advanced ocd system, effi- cient data and instruction caches, and a full mmu. figure 7-1 on page 19 displays the contents of avr32 ap.
19 32003e?avr32?05/06 at32ap7000 figure 7-1. overview of the avr32 ap cpu 7.2.1 pipeline overview avr32 ap is a pipelined processor with seven pipe line stages. the pipeline has three subpipes, namely the multiply pipe, the execute pipe and the data pipe. these pipelines may execute dif- ferent instructions in parallel. instructions are issued in order, but may complete out of order (ooo) since the subpipes may be stalled individ ually, and certain operations may use a subpipe for several clock cycles. figure 7-2 on page 20 shows an overview of the avr32 ap pipeline stages. avr32 cpu pipeline with java accelerator dcache controller ahb lite master icache controller ahb lite master 32-entry tlb 8-entry utlb 4-entry utlb mmu ahb lite bus ahb lite bus cache ram interface cache ram interface btb ram interface tightly coupled bus ocd system ocd interface reset control reset interface interrupt controller interface jtag control jtag interface
20 32003e?avr32?05/06 at32ap7000 figure 7-2. the avr32 ap pipeline .the follwing abbreviations are used in the figure: ? if1, if2 - instruction fetch stage 1 and 2 ? id - instruction decode ? is - instruction issue ? a1, a2 - alu stage 1 and 2 ? m1, m2 - multiply stage 1 and 2 ? da - data address calculation stage ? d - data cache access ? wb - writeback 7.2.2 avr32b microarchitecture compliance avr32 ap implements an avr32b microarchitec ture. the avr32b microarchitecture is tar- geted at applications where interrupt latency is important. the avr32b therefore implements dedicated registers to hold the status register and return address for interrupts, exceptions and supervisor calls. this information does not need to be written to the stack, and latency is there- fore reduced. additionally, avr32b allows hardware shadowing of the registers in the register file. the scall , rete and rets instructions use the dedicated return status registers and return address registers in their operation. no stack accesses are performed by these instructions. 7.2.3 java support avr32 ap provides java hardware acceleration in the form of a java virtual machine hardware implementation. refer to the avr32 java technical reference manual for details. 7.2.4 memory management avr32 ap implements a full mmu as specified by the avr32 architecture. the page sizes pro- vided are 1k, 4k, 64k and 1m. a 32-entry fully-associative common tlb is implemented, as well as a 4-entry micro-itlb and 8-entry micro-dtlb. instruction and data accesses perform lookups in the micro-tlbs. if the access misses in the mi cro-tlbs, an access in the common tlb is per- formed. if this access misses, a page miss exception is issued. if2 id is a1 m1 m2 d wb prefetch unit decode unit alu pipe multiply pipe load-store pipe da a2 if1
21 32003e?avr32?05/06 at32ap7000 7.2.5 caches and write buffer avr32 ap implements 16k data and 16k instruction caches. the caches are 4-way set asso- ciative. each cache has a 32-bit system bus master interface connecting it to the bus. the instruction cache has a 32-bit interface to the fetch pipeline stage, and the data cache has a 64- bit interface to the load-store pipeline. the cac hes use a least recently used allocate-on-read- miss replacement policy. the caches are virtually tagged, physically indexed, avoiding the need to flush them on task switch. the caches provide locking on a per-line basis, allowing code and data to be permanently locked in the caches for timing-critical code. t he data cache also allows prefetching of data using the pref instruction. accesses to the instruction and data caches ar e tagged as cacheable or uncacheable on a per- page basis by the mmu. data cache writes are tagged as write-through or writeback on a per- page basis by the mmu. the data cache has a 32-byte combining write buffe r, to avoid stalling the cpu when writing to external memory. writes are tagged as bufferable or unbufferable on a per-page basis by the mmu. bufferable writes to sequential addresses are placed in the buffer, allowing for example a sequence of byte writes from the cpu to be combined into word transfers on the bus. a sync instruction is provided to explicitly flush the write buffer. 7.2.6 unaligned reference handling avr32 ap has hardware support for performing unaligned memory accesses. this will reduce the memory footprint needed by some applicatio ns, as well as speed up other applications oper- ating on unaligned data. avr32 ap is able to perform certain word-sized load and store instructions of any alignment, and word-aligned st.d and ld.d . any other unaligned memory a ccess will cause an mmu address exception. all coprocessor memory access inst ructions require word-a ligned pointers. double- word-sized accesses with word-aligned pointers will automatically be performed as two word- sized accesses. the following table shows the instructions with support for unaligned addresses. all other instructions require aligned addresses. ac cessing an unaligned address may require several clock cycles, refer to the avr32 ap technical reference manual for details. table 7-1. instructions with unaligned reference support instruction supported alignment ld.w any st.w any lddsp any lddpc any stdsp any ld.d word st.d word all coprocessor memory access instruction word
22 32003e?avr32?05/06 at32ap7000 7.2.7 unimplemented instructions the following instructions are unimplemented in avr32 ap, and will cause an unimplemented instruction exception if executed: ?mems ?memc ?memt 7.2.8 exceptions and interrupts avr32 ap incorporates a powerful exception handling scheme. the different exception sources, like illegal op-code and external interrup t requests, have different priority levels, ensur- ing a well-defined behavior when multiple except ions are received simu ltaneously. additionally, pending exceptions of a higher priority class ma y preempt handling of ongoing exceptions of a lower priority class. each priority class has dedicated registers to keep the return address and status register thereby removing the need to perform time-consuming memory operations to save this information. there are four levels of external interrupt req uests, all executing in their own context. the int3 context provides dedicated shadow registers ensuring low latency for these interrupts. an inter- rupt controller does the priority handling of th e external interrupts and provides the autovector offset to the cpu. the addresses and priority of si multaneous events are shown in table 7-2 on page 23 .
23 32003e?avr32?05/06 at32ap7000 table 7-2. priority and handler addresses for events priority handler address name event source stored return address 1 0xa000_0000 reset external input undefined 2 provided by ocd system ocd stop cpu ocd system first non-compl eted instruction 3 evba+0x00 unrecoverable exception int ernal pc of offending instruction 4 evba+0x04 tlb multiple hit internal signal pc of offending instruction 5 evba+0x08 bus error data fetch data bu s first non-completed instruction 6 evba+0x0c bus error instruction fetch dat a bus first non-completed instruction 7 evba+0x10 nmi external input first non-completed instruction 8 autovectored interrupt 3 request external input first non-completed instruction 9 autovectored interrupt 2 request external input first non-completed instruction 10 autovectored interrupt 1 request external input first non-completed instruction 11 autovectored interrupt 0 request external input first non-completed instruction 12 evba+0x14 instruction address itlb pc of offending instruction 13 evba+0x50 itlb miss itlb pc of offending instruction 14 evba+0x18 itlb protection itlb pc of offending instruction 15 evba+0x1c breakpoint ocd system firs t non-completed instruction 16 evba+0x20 illegal opcode instructio n pc of offending instruction 17 evba+0x24 unimplemented instruction instr uction pc of offending instruction 18 evba+0x28 privilege violation instruc tion pc of offending instruction 19 evba+0x2c floating-point fp hardware pc of offending instruction 20 evba+0x30 coprocessor absent instruct ion pc of offending instruction 21 evba+0x100 supervisor call instru ction pc(supervisor call) +2 22 evba+0x34 data address (read) dtlb pc of offending instruction 23 evba+0x38 data address (write) dtl b pc of offending instruction 24 evba+0x60 dtlb miss (read) dtlb pc of offending instruction 25 evba+0x70 dtlb miss (write) dtlb pc of offending instruction 26 evba+0x3c dtlb protecti on (read) dtlb pc of offending instruction 27 evba+0x40 dtlb protection (write) d tlb pc of offending instruction 28 evba+0x44 dtlb modified dtlb pc of offending instruction
24 32003e?avr32?05/06 at32ap7000 7.3 programming model 7.3.1 register file configuration the avr32b architecture specifies that the ex ception contexts may have a different number of shadowed registers in different implementations. figure 7-3 on page 24 shows the model used in avr32 ap. figure 7-3. the avr32 ap register file 7.3.2 status register configuration the status register (sr) is splitted into two halfwords, one upper and one lower, see figure 7-4 on page 24 and figure 7-5 on page 25 . the lower word contains the c, z, n, v and q condition code flags and the r, t and l bits, while the upper halfword contains information about the mode and state the processor executes in. refer to the avr32 architecture manual for details. figure 7-4. the status register high halfword application bit 0 supervisor bit 31 pc sr int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 bit 0 bit 31 pc sr r12 int0pc fintpc int1pc smpc r7 r5 r6 r4 r11 r9 r10 r8 r3 r1 r2 r0 rsr_int0 sr rsr_ex sr sp_app sp_sys rsr_nmi sr r12 r11 r9 r10 r8 bit 0 bit 31 pc int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 bit 0 bit 31 pc fintpc smpc r7 r5 r6 r4 r3 r1 r2 r0 bit 0 bit 31 pc lr_int3 r12_int3 r11_int3 r9_int3 r10_int3 r8_int3 sp_sys sp_sys sp_sys r12 r11 r9 r10 r8 bit 0 bit 31 pc int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 sp_sys r12 r11 r9 r10 r8 bit 0 bit 31 pc int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 sp_sys r12 r11 r9 r10 r8 bit 0 bit 31 pc int0pc fintpc int1pc smpc r7 r5 r6 r4 r3 r1 r2 r0 sp_sys r12 r11 r9 r10 r8 rsr_int1 sr rsr_int2 sr rsr_int3 sr int0 int1 int2 int3 exception nmi fintpc smpc r7 r5 r6 r4 r3 r1 r2 r0 r12 r11 r9 r10 r8 lr lr lr lr lr lr lr rsr_sup rar_int0 rar_ex rar_nmi rar_int1 rar_int2 rar_int3 rar_sup bit 31 0 0 0 bit 16 interrupt level 0 mask interrupt level 1 mask interrupt level 3 mask interrupt level 2 mask 1 0 0 0 0 1 1 0 0 0 0 0 0 reserved fe i0m gm m1 j d m0 em i2m dm - m2 lc 1 - initial value bit name i1m mode bit 0 mode bit 1 h mode bit 2 reserved debug state - i3m java state exception mask global interrupt mask debug state mask java handle reserved
25 32003e?avr32?05/06 at32ap7000 figure 7-5. the status register low halfword 7.3.3 processor states 7.3.3.1 normal risc state the avr32 processor supports several diff erent execution contexts as shown in table 7-3 on page 25 . mode changes can be made under software control, or can be caused by external interrupts or exception processing. a mode can be interrupted by a higher priority mode, but never by one with lower priority. nested exceptions can be supported with a minimal software overhead. when running an operating syste m on the avr32, user processes will typically execute in the application mode. the programs executed in this mode are restricted from executing certain instructions. furthermore, most system registers together with the upper halfword of the status register cannot be accessed. protected memory areas are also not available. all other operating modes are privileged and are collectively called system modes. they have full access to all priv- ileged and unprivileged re sources. after a reset, the proc essor will be in su pervisor mode. 7.3.3.2 debug state the avr32 can be set in a debug state, which allows implementation of software monitor rou- tines that can read out and alter system information for use during application development. this implies that all system and application regist ers, including the status registers and program counters, are accessible in debug state. th e privileged instructions are also available. bit 15 bit 0 reserved carry zero sign 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - - - t r bit name initial value 0 0 l q v n z c - overflow saturation - - - lock register remap enable scratch table 7-3. overview of execution modes, their priorities and pr ivilege levels. priority mode securi ty description 1 non maskable interrupt privileged non maskable high priority interrupt mode 2 exception privileged execute exceptions 3 interrupt 3 privileged general purpose interrupt mode 4 interrupt 2 privileged general purpose interrupt mode 5 interrupt 1 privileged general purpose interrupt mode 6 interrupt 0 privileged general purpose interrupt mode n/a supervisor privileged runs supervisor calls n/a application unprivileged normal program execution mode
26 32003e?avr32?05/06 at32ap7000 all interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. debug state can be entered as described in the avr32 ap technical reference manual . debug state is exited by the retd instruction. 7.3.3.3 java state avr32 ap implements a java extension module (jem). the processor can be set in a java state where normal risc operations are suspended. refer to the avr32 java technical refer- ence manual for details.
27 32003e?avr32?05/06 at32ap7000 8. pixel coprocessor (pico) rev: 1.0.0 8.1 features ? coprocessor coupled to the avr3 2 cpu core through the tcb bus. ? three parallel vector multiplicati on units (vmu) where each unit can: ? multiply three pixel componen ts with three coefficients. ? add the products from the multiplications together. ? accumulate the result or add an o ffset to the sum of the products. ? can be used for accelerating: ? image color space conversion. ?configurable conver sion coefficients. ? supports packed and planar input and output formats. ? supports subsampled input color spaces (i.e 4:2:2, 4:2:0). ? image filtering/scaling. ? configurable filter coefficients. ? throughput of one sample per cycle for a 9-tap fir filter. ? can use the built-in accumulator to extend the fir filter to more than 9-taps. ? can be used for bilinear/bicubic interpolations. ? mpeg-4/h.264 quarter pi xel motion compensation. ? flexible input pixel selector. ? can operate on numerous different image storage formats. ? flexible output pixel inserter. ? scales and saturates the results back to 8-bit pixel values. ? supports packed and planar output formats. ? configurable coefficien ts with flexible fixe d-point representation. 8.2 description the pixel coprocessor (pico) is a coprocesso r coupled to the avr32 cpu through the tcb (tightly coupled bus) interface. the pico consists of three ve ctor multiplication units (vmu0, vmu1, vmu2), an input pixel selector and an output pixel inserter. each vmu can perform a vector multiplication of a 1x3 12-bit coefficient vector with a 3x1 8-bit pixel vector. in addition a 12-bit offset can be added to the result of this vector multiplication. the pico can be used for transforming the pixel components in a given color space (i.e. rgb, ycrcb, yuv) to any othe r color space as long as the transformation is linear. the flexibility of the input pixel selector and output pixel insertio n logic makes it easy to efficiently support dif- ferent pixel storage formats with regards to issues such as byte ordering of the color components, if the color components constituting an image are packed/interleaved or stored as separate images or if any of the color components are subsampled. the three vector multiplication units can also be connected together to form one large vector multiplier which can perform a vector multiplication of a 1x9 12-bit coefficient vector with a 9x1 8- bit pixel vector. this can be used to implement fir filters, bilinear interpolations filters for smoothing/scaling images etc. by allowing the outputs from the vector multiplication units to accumulate it is also possible to extend the order of the filter to more than 9-taps. the results from the vmus are scaled and saturated back to unsigned 8-bit pixel values in the output pixel inserter.
28 32003e?avr32?05/06 at32ap7000 the pico is divided into three pipeline stages with a throughput of one operation per cpu clock cycle. 8.3 block diagram figure 8-1. pixel coprocessor block diagram inpix0 vmu0_out input pixel selector vmu0 add vmu0_in0 vmu0_in1 vmu0_in2 inpix1 inpix2 coeff0_0 coeff0_1 coeff0_2 offset0 vmu1_out vmu1 vmu1_in0 vmu1_in1 vmu1_in2 coeff1_0 coeff1_1 coeff1_2 offset1 vmu2_out vmu2 vmu2_in0 vmu2_in1 vmu2_in2 coeff2_0 coeff2_1 coeff2_2 offset2 outpix0 outpix1 outpix2 output pixel inserter pipeline stage 1 pipeline stage 2 pipeline stage 3
29 32003e?avr32?05/06 at32ap7000 8.4 vector multiplication unit (vmu) each vmu consists of three mult ipliers used for multiplying uns igned 8-bit pixel components with signed 12-bit coefficients.the result from each multiplication is a 20-bit signed number that is input to a 22-bit vector adder along with an offset as shown in figure 8-2 on page 29 . the oper- ation is equal to the offsetted vector multiplication given in the following equation: figure 8-2. inside vmu n ( n {0,1,2}) 8.5 input pixel selector the input pixel selector uses the ism (input selection mode) field in the config register and the three input pixel source addresses given in the pico operation instructions to decide which pixels to select for inputs to the vmus. 8.5.1 transformation mode when the input selection mode is set to transformation mode the input pixel source addresses inx, iny and inz directly maps to three pixels in the inpix n registers. these three pixels are then input to each of the vmus. the following expression then represents what is computed by the vmus in transformation mode: vmu_out coeff0 coeff1 coeff2 vmu_in0 vmu_in1 vmu_in2 offset + = multiply vector adder multiply multiply vmu n offset n coeff n _1 coeff n _2 coeff n _0 vmu n _in0 vmu n _in1 vmu n _in2 vmu n _out vmu0_out vmu1_out vmu2_out coeff0_0 coeff0_1 coeff0_2 coeff1_0 coeff1_1 coeff1_2 coeff2_0 coeff2_1 coeff2_2 inx iny inz offset0 or vmu0_out offset1 or vmu1_out offset2 or vmu2_out + =
30 32003e?avr32?05/06 at32ap7000 8.5.2 horizontal filter mode in horizontal filter mode the input pixel source addresses inx, iny and inz represents the base pixel address of a pixel triplet. the pixel triplet {in(x), in(x+1), in(x+2)} is input to vmu0, the pixel triplet {in(y), in(y+1), in(y+2 )} is input to vmu1 and the pixe l triplet {in(z), in(z+1), in(z+2)} is input to vmu2. figure 8-3 on page 30 shows how the pixel triplet is found by taking the pixel addressed by the base address and following the arrow to find the next two pixels which makes up the triplet. figure 8-3. horizontal filter mode pixel addressing the following expression represents what is computed by the vmus in horizontal filter mode: 8.5.3 vertical filter mode in vertical filter mode the input pixel source addresses inx, iny and inz represent the base of a pixel triplet found by following the vertical arrow shown in figure 8-4 on page 31 . the pixel triplet {in(x), in((x+4)%11), in((x+8)%11)} is input to vmu0, the pixel triplet {in(y), in((y+4)%11), in((y+8)%11)} is input to vmu1 and the pixel trip let {in(z), in((z+4)%11), in((z+8)%11)} is input to vmu2. inpix0 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 inpix1 inpix2 vmu0_out coeff0_0 coeff0_1 coeff0_2 in(x+0) in(x+1) in(x+2) offset0 or vmu0_out () + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in(y+0) in(y+1) in(y+2) offset1 or vmu1_out () + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in(z+0) in(z+1) in(z+2) offset2 or vmu2_out () + =
31 32003e?avr32?05/06 at32ap7000 figure 8-4. vertical filter mode pixel addressing the following expression represents what is computed by the vmus in vertical filter mode: 8.6 output pixel inserter the output pixel inserter uses the oim (output insertion mode) field in the config register and the destination pixel address given in the pico operation instructions to decide which three of the twelve possible out n pixels to write back the scaled a nd saturated results from the vmus to. the 22-bit results from each vmu is first scal ed by performing an arithmetical right shift by coeff_frac_bits in order to remove the fractional part of the results and obtain the integer part. the integer part is then saturated to an unsigned 8-bit number in the range 0 to 255. 8.6.1 planar insertion mode in planar insertion mode the destination pixel address outd specifies which pixel in each of the registers outpix0, outpix1 and outpix2 will be updated. vmu n writes to outpix n . this can be seen in figure 8-5 on page 32 and table 8-2 on page 49 . this mode is useful when transforming from one color space to another where the resulting color components should be stored in separate images. inpix0 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 inpix1 inpix2 vmu0_out coeff0_0 coeff0_1 coeff0_2 in((x+0)%11) in((x+4)%11) in((x+8)%11) offset0 or vmu0_out () + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in((y+0)%11) in((y+4)%11) in((y+8)%11) offset1 or vmu1_out () + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in((z+0)%11) in((z+4)%11) in((z+8)%11) offset2 or vmu2_out () + =
32 32003e?avr32?05/06 at32ap7000 figure 8-5. planar pixel insertion 8.6.2 packed insertion mode in packed insertion mode the three output registers outpix0, outpix1 and outpix2 are divided into four pixel triplets as seen in figure 8-6 on page 32 and table 8-2 on page 49 . the destination pixel address is then the address of the pixel triplet. vmu n writes to pixel n of the pixel triplet.this mode is useful when transfo rming from one color space to another where the resulting color components sh ould be packed together. figure 8-6. packed pixel insertion. outpix0 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 outpix1 outpix2 d = 0 d = 2 d = 1 d = 3 = vmu0 = vmu1 = vmu2 outpix0 out0 out1 out2 out3 out4 out5 out6 out7 out8 out9 out10 out11 d = 0 d = 1 d = 2 d = 3 outpix1 outpix2 = vmu0 = vmu1 = vmu2
33 32003e?avr32?05/06 at32ap7000 8.7 user interface the pico uses the tcb interface to communicate with the cpu and the user can read from or write to the pico register file by using the pico load/store/move instructions which maps to generic coprocessor instructions. 8.7.1 register file the pico register file can be accessed from the cpu by using the picomv.x, picold.x, picost.x, picoldm and picostm instructions. table 8-1. pico register file cp reg # register name access cr0 input pixel register 2 inpix2 read/write cr1 input pixel register 1 inpix1 read/write cr2 input pixel register 0 inpix0 read/write cr3 output pixel register 2 outpix2 read only cr4 output pixel register 1 outpix1 read only cr5 output pixel register 0 outpix0 read only cr6 coefficient register a for vmu0 coeff0_a read/write cr7 coefficient register b for vmu0 coeff0_b read/write cr8 coefficient register a for vmu1 coeff1_a read/write cr9 coefficient register b for vmu1 coeff1_b read/write cr10 coefficient register a for vmu2 coeff2_a read/write cr11 coefficient register b for vmu2 coeff2_b read/write cr12 output from vmu0 vmu0_out read/write cr13 output from vmu1 vmu1_out read/write cr14 output from vmu2 vmu2_out read/write cr15 pico configuration register config read/write
34 32003e?avr32?05/06 at32ap7000 8.7.1.1 input pixel register 0 register name: inpix0 access type: read/write ? in0: input pixel 0 input pixel number 0 to the input pixel selector unit. ? in1: input pixel 1 input pixel number 1 to the input pixel selector unit. ? in2: input pixel 2 input pixel number 2 to the input pixel selector unit. ? in3: input pixel 3 input pixel number 3 to the input pixel selector unit. 31 30 29 28 27 26 25 24 in0 23 22 21 20 19 18 17 16 in1 15 14 13 12 11 10 9 8 in2 76543210 in3
35 32003e?avr32?05/06 at32ap7000 8.7.1.2 input pixel register 1 register name: inpix1 access type: read/write ? in0: input pixel 4 input pixel number 4 to the input pixel selector unit. ? in1: input pixel 5 input pixel number 5 to the input pixel selector unit. ? in2: input pixel 6 input pixel number 6 to the input pixel selector unit. ? in3: input pixel 7 input pixel number 7 to the input pixel selector unit. 31 30 29 28 27 26 25 24 in4 23 22 21 20 19 18 17 16 in5 15 14 13 12 11 10 9 8 in6 76543210 in7
36 32003e?avr32?05/06 at32ap7000 8.7.1.3 input pixel register 2 register name: inpix2 access type: read/write ? in0: input pixel 8 input pixel number 8 to the input pixel selector unit. ? in1: input pixel 9 input pixel number 9 to the input pixel selector unit. ? in2: input pixel 10 input pixel number 10 to the input pixel selector unit. ? in3: input pixel 11 input pixel number 11 to the input pixel selector unit. 31 30 29 28 27 26 25 24 in8 23 22 21 20 19 18 17 16 in9 15 14 13 12 11 10 9 8 in10 76543210 in11
37 32003e?avr32?05/06 at32ap7000 8.7.1.4 output pixel register 0 register name: outpix0 access type: read ? out0: output pixel 0 output pixel number 0 from the output pixel inserter unit. ? out1: output pixel 1 output pixel number 1 from the output pixel inserter unit. ? out2: output pixel 2 output pixel number 2 from the output pixel inserter unit. ? out3: output pixel 3 output pixel number 3 from the output pixel inserter unit. 31 30 29 28 27 26 25 24 out0 23 22 21 20 19 18 17 16 out1 15 14 13 12 11 10 9 8 out2 76543210 out3
38 32003e?avr32?05/06 at32ap7000 8.7.1.5 output pixel register 1 register name: outpix1 access type: read ? out4: output pixel 4 output pixel number 4 from the output pixel inserter unit. ? out5: output pixel 5 output pixel number 5 from the output pixel inserter unit. ? out6: output pixel 6 output pixel number 6 from the output pixel inserter unit. ? out7: output pixel 7 output pixel number 7 from the output pixel inserter unit. 31 30 29 28 27 26 25 24 out4 23 22 21 20 19 18 17 16 out5 15 14 13 12 11 10 9 8 out6 76543210 out7
39 32003e?avr32?05/06 at32ap7000 8.7.1.6 output pixel register 2 register name: outpix2 access type: read ? out8: output pixel 8 output pixel number 8 from the output pixel inserter unit. ? out9: output pixel 9 output pixel number 9 from the output pixel inserter unit. ? out10: output pixel 10 output pixel number 10 from the output pixel inserter unit. ? out11: output pixel 11 output pixel number 11 from the output pixel inserter unit. 31 30 29 28 27 26 25 24 out8 23 22 21 20 19 18 17 16 out9 15 14 13 12 11 10 9 8 out10 76543210 out11
40 32003e?avr32?05/06 at32ap7000 8.7.1.7 coefficient register a for vmu0 register name: coeff0_a access type: read/write ? coeff0_0: coefficient 0 for vmu0 coefficient 0 input to vmu0. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff0_0 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff0_0 is sign- extended to 16-bits in or der to fill in the unused bits in th e upper halfword of this register. ? coeff0_1: coefficient 1 for vmu0 coefficient 1 input to vmu0. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff0_1 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff0_1 is sign- extended to 16-bits in or der to fill in the unused bits in th e lower halfword of this register. 31 30 29 28 27 26 25 24 ---- coeff0_0 23 22 21 20 19 18 17 16 coeff0_0 15 14 13 12 11 10 9 8 ---- coeff0_1 76543210 coeff0_1 coeff0_0 2 coeff_frac_bits ? coeff0_1 2 coeff_frac_bits ?
41 32003e?avr32?05/06 at32ap7000 8.7.1.8 coefficient register b for vmu0 register name: coeff0_b access type: read/write ? coeff0_2: coefficient 2 for vmu0 coefficient 2 input to vmu0. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff0_2 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff0_2 is sign- extended to 16-bits in or der to fill in the unused bits in th e upper halfword of this register. ? offset0: offset for vmu0 offset input to vmu0 in case of non-accumulating operations. a signed 12-bit fixed-point number where the number of frac- tional bits is given by the offset_fra c_bits field in the config register. t he actual fractional number is equal to , where the offset0 value is interpreted as a 2?s complement integer. when reading this reg- ister, offset0 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 31 30 29 28 27 26 25 24 ---- coeff0_2 23 22 21 20 19 18 17 16 coeff0_2 15 14 13 12 11 10 9 8 ---- offset0 76543210 offset0 coeff0_2 2 coeff_frac_bits ? offset0 2 offset_frac_bits ?
42 32003e?avr32?05/06 at32ap7000 8.7.1.9 coefficient register a for vmu1 register name: coeff1_a access type: read/write ? coeff1_0: coefficient 0 for vmu1 coefficient 0 input to vmu1. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff1_0 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff1_0 is sign- extended to 16-bits in or der to fill in the unused bits in th e upper halfword of this register. ? coeff1_1: coefficient 1 for vmu1 coefficient 1 input to vmu0. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff1_1 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff1_1 is sign- extended to 16-bits in or der to fill in the unused bits in th e lower halfword of this register. 31 30 29 28 27 26 25 24 ---- coeff1_0 23 22 21 20 19 18 17 16 coeff1_0 15 14 13 12 11 10 9 8 ---- coeff1_1 76543210 coeff1_1 coeff1_0 2 coeff_frac_bits ? coeff1_1 2 coeff_frac_bits ?
43 32003e?avr32?05/06 at32ap7000 8.7.1.10 coefficient register b for vmu1 register name: coeff1_b access type: read/write ? coeff1_2: coefficient 2 for vmu1 coefficient 2 input to vmu1. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff1_2 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff1_2 is sign- extended to 16-bits in or der to fill in the unused bits in th e upper halfword of this register. ? offset1: offset for vmu1 offset input to vmu1 in case of non-accumulating operations. a signed 12-bit fixed-point number where the number of frac- tional bits is given by the offset_fra c_bits field in the config register. t he actual fractional number is equal to , where the offset1 value is interpreted as a 2?s complement integer. when reading this reg- ister, offset1 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 31 30 29 28 27 26 25 24 ---- coeff1_2 23 22 21 20 19 18 17 16 coeff1_2 15 14 13 12 11 10 9 8 ---- offset1 76543210 offset1 coeff1_2 2 coeff_frac_bits ? offset1 2 offset_frac_bits ?
44 32003e?avr32?05/06 at32ap7000 8.7.1.11 coefficient register a for vmu2 register name: coeff2_a access type: read/write ? coeff2_0: coefficient 0 for vmu2 coefficient 0 input to vmu2. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff2_0 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff2_0 is sign- extended to 16-bits in or der to fill in the unused bits in th e upper halfword of this register. ? coeff2_1: coefficient 1 for vmu2 coefficient 1 input to vmu2. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff2_1 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff2_1 is sign- extended to 16-bits in or der to fill in the unused bits in th e lower halfword of this register. 31 30 29 28 27 26 25 24 ---- coeff2_0 23 22 21 20 19 18 17 16 coeff2_0 15 14 13 12 11 10 9 8 ---- coeff2_1 76543210 coeff2_1 coeff2_0 2 coeff_frac_bits ? coeff2_1 2 coeff_frac_bits ?
45 32003e?avr32?05/06 at32ap7000 8.7.1.12 coefficient register b for vmu2 register name: coeff2_b access type: read/write ? coeff2_2: coefficient 2 for vmu2 coefficient 2 input to vmu2. a signed 12-bit fixed-point number where the number of fractional bits is given by the coeff_frac_bits field in the config register. the actual fractional number is equal to , where the coeff2_2 value is interpreted as a 2?s compleme nt integer. when reading this register, coeff2_2 is sign- extended to 16-bits in or der to fill in the unused bits in th e upper halfword of this register. ? offset2: offset for vmu2 offset input to vmu2 in case of non-accumulating operations. a signed 12-bit fixed-point number where the number of frac- tional bits is given by the offset_fra c_bits field in the config register. t he actual fractional number is equal to , where the offset2 value is interpreted as a 2?s complement integer. when reading this reg- ister, offset2 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 31 30 29 28 27 26 25 24 ---- coeff2_2 23 22 21 20 19 18 17 16 coeff2_2 15 14 13 12 11 10 9 8 ---- offset2 76543210 offset2 coeff2_2 2 coeff_frac_bits ? offset2 2 offset_frac_bits ?
46 32003e?avr32?05/06 at32ap7000 8.7.1.13 vmu0 output register register name: vmu0_out access type: read/write ? vmu0_out: output from vmu0 this register is used for directly accessing the output from vmu0 or for setting the initial value of the accumulator for accu- mulating operations. the output from vmu0 is a signed 22-bit fixed-point number where the number of fractional bits are given by the coeff_frac_bits field in the config register. wh en reading this register the signed 22-bit value is sign- extended to 32-bits. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - vmu0_out 15 14 13 12 11 10 9 8 vmu0_out 76543210 vmu0_out
47 32003e?avr32?05/06 at32ap7000 8.7.1.14 vmu1 output register register name: vmu1_out access type: read/write ? vmu1_out: output from vmu1 this register is used for directly accessing the output from vmu1 or for setting the initial value of the accumulator for accu- mulating operations. the output from vmu1 is a signed 22-bit fixed-point number where the number of fractional bits are given by the coeff_frac_bits field in the config register. wh en reading this register the signed 22-bit value is sign- extended to 32-bits. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - vmu1_out 15 14 13 12 11 10 9 8 vmu1_out 76543210 vmu1_out
48 32003e?avr32?05/06 at32ap7000 8.7.1.15 vmu2 output register register name: vmu2_out access type: read/write ? vmu2_out: output from vmu2 this register is used for directly accessing the output from vmu2 or for setting the initial value of the accumulator for accu- mulating operations. the output from vmu2 is a signed 22-bit fixed-point number where the number of fractional bits are given by the coeff_frac_bits field in the config register. wh en reading this register the signed 22-bit value is sign- extended to 32-bits. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 - - vmu2_out 15 14 13 12 11 10 9 8 vmu2_out 76543210 vmu2_out
49 32003e?avr32?05/06 at32ap7000 8.7.1.16 pico configuration register register name: config access type: read/write ? oim: output insertion mode the oim bit specifies the semantics of the outd output pixel address parameter to the pico(s)v(mul/mac) instructions. the oim together with the output pixel address parameter specify which of the 12 output bytes (out n ) of the outpix n regis- ters will be updated with th e results from the vmus. table 8-2 on page 49 describes the different output insertion modes. see section 8.6 ?output pixel inserter? on page 31 for a description of the output pixel inserter. ? ism: input selection mode the ism field specifies the semantics of the input pixel address parameters inx, iny and inz to the pico(s)v(mul/mac) instructions. together with the three input pixel addresses the ism field specifies to the input pixel selector which of th e input pixels (in n ) that should be selected as inputs to the vmus. table 8-3 on page 50 describes the 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -----oim ism 76543210 offset_frac_bits coeff_frac_bits table 8-2. output insertion modes oim mode description 0 packed insertion mode {outpix0, outpix1, outpix2} is treated as one large register containing 4 sequential 24- bit pixel triplets. the dst_adr field specifies wh ich of the sequential triplets will be updated. out(d*3 + 0) scaled and saturated output from vmu0 out(d*3 + 1) scaled and saturated output from vmu1 out(d*3 + 2) scaled and saturated output from vmu2 1 planar insertion mode each of the outpix n registers will get one of the resulting pixels. the triplet address specifies what byte in each of the outpix n registers the results will be written to. out(d + 0) scaled and saturated output from vmu0 out(d+ 4) scaled and saturated output from vmu1 out(d + 8) scaled and saturated output from vmu2
50 32003e?avr32?05/06 at32ap7000 different input selection modes. see section 8.5 ?input pixel selector? on page 29 for a description of the input pixel selector. ? offset_frac_bits: offset fractional bits specifies the number of fractional bits in the fixed-point offsets input to each vmu. must be in the range from 0 to coeff_frac_bits. other values gives undefined resu lts.this value is used for scaling the offset n values before being input to vmu n so that the offset will have the same fixed-point format as the outputs from the multiplication stages before performing the vector addition in the vmu. ? coeff_frac_bits: coefficient fractional bits specifies the number of fractional bits in the fixed-point coefficients input to each vmu. must be in the range from 0 to 11, since at least one bit of the coefficient must be us ed for the sign. other values gives undefined results. coeff_frac_bits is used in the output pixel inserter to sc ale the fixed-point results from the vmus back to unsigned 8- bit integers. table 8-3. input selection modes ism mode 0 0 transformation mode vmu0, vmu1 and vmu2 get the same pixel inputs. these three pixels can be freely selected from the inpix n registers. 0 1 horizontal filter mode pixel triplets are selected for input to each of the vmus by addressing horizontal pixel triplets from the inpix n registers. 1 0 vertical filter mode pixel triplets are selected for input to each of the vmus by addressing vertical pixel triplets from the inpix n registers. 1 1 reserved n.a
51 32003e?avr32?05/06 at32ap7000 8.8 pico instructions 8.8.1 pico instructions nomenclature 8.8.1.1 registers and operands r {d, s, ?} the uppercase ? r ? denotes a 32-bit (word) register. r d the lowercase ? d ? denotes the destination register number. r s the lowercase ? s ? denotes the source register number. r b the lowercase ? b ? denotes the base register number for indexed addressing modes. r i the lowercase ? i ? denotes the index register number for indexed addressing modes. r p the lowercase ? p ? denotes the pointer register number. in {x, y, z} the uppercase ? in ? denotes a pixel in the inpix n registers. in x the lowercase ? x ? denotes the first input pixel number for the pico operation instructions. in y the lowercase ? y ? denotes the second input pixel number for the pico operation instructions. in z the lowercase ? z ? denotes the third input pixel number for the pico operation instructions. out d the uppercase ? out ? denotes a pixel in the outpix n registers. out d the lowercase ? d ? denotes the destination pixel number for the pico operation instructions. pr pico register. see section 8.7.1 ?register file? on page 33 for a complete list of registers. prhi:prlo pico register pair. only register pairs corresponding to valid coprocessor double registers are valid. e.g. inpix1:inpix2 (cr1:cr0). the low part must correspond to an even coprocessor register number n and the high part must then correspond to coprocessor register n+1 . see table 8-1 on page 33 for a mapping between pico register names and coprocessor register numbers. pc program counter, equal to r15 lr link register, equal to r14 sp stack pointer, equal to r13 picoreglist register list used in the picoldm and picostm instructions. see instruct ion description for which register combinations are allowed in the register list. disp displacement sa shift amount [i] denotes bit i in a immediate value. example: imm6[4] denotes bit 4 in an 6-bit immediate value. [i:j] denotes bit i to j in an immediate value. some instructions access or use doubleword operands. these operands must be placed in two consecutive register addresses where the first register must be an even register . the even register contains the least significant part and the odd register contains the most significant part. this ordering is reversed in comparison with how data is organized in memory (where the most significant part would receive the lowest address) and is intentional.
52 32003e?avr32?05/06 at32ap7000 the programmer is responsible for placing these operands in properly aligned register pairs. this is also specified in the "operands" section in the detailed de scription of each instruct ion. failure to do so will result in an undefined behavior. 8.8.1.2 operations asr(x, n) se(x, bits(x) + n) >> n satsu(x, n) signed to unsigned saturation ( x is treated as a signed value ): if (x > (2 n -1)) then (2 n-1 -1); elseif ( x < 0 ) then 0; else x; se(x, n) sign extend x to an n-bit value 8.8.1.3 data type extensions .d double (64-bit) operation. .w word (32-bit) operation.
53 32003e?avr32?05/06 at32ap7000 8.8.2 pico instruction summary table 8-4. pico instruct ion summary mnemonics operands / syntax description operation picosvmac e outd, inx, iny, inz pico single vector multiplication and accumulation. see pico instruction set reference picosvmul e outd, inx, iny, inz pico single vector multiplication see pico instruction set reference picovmac e outd, inx, iny, inz pico vector multiplications and accumulations. see pico instruction set reference picovmul e outd, inx, iny, inz pico vector mult iplications. see pico instruction set reference picold.d e prhi:prlo, rp[disp] load pico register pair prhi:prlo *(rp+ze(disp8<<2)) e prhi:prlo, --rp load pico register pair with pre-decrement prhi:prlo *(--rp) e prhi:prlo, rb[ri< 54 32003e?avr32?05/06 at32ap7000 picosvmac ? pico single vector multiplication and accumulation description performs three vector multiplications where the input pixels taken from the inpix n registers depends on the input selection mode and the input pixel addresses given in the instruction. the values in the vmu n _out registers are then accumulated with the new results from the vector mult iplications. the results from each vector multiplication unit (vmu) are then added together for one of the outputs to the output pixels inserter to form the result of a single vector multiplication of two 9-ele - ment vectors. the results from the vmus are then scaled and saturated to unsigned 8-bit values before being inserted into the outpix n registers. which pixels to update in the outpix n registers depend upon the output insertion mode and the output pixel address given in the instruction. operation: i. if ( input selection mode == horizontal filter mode ) then else if ( input selection mode == vertical filter mode ) then else if ( input selection mode == transformation mode ) then if ( output insertion mode == packed insertion mode ) then out(d*3 + 0) satsu(asr(vmu0_out + vmu1_out + vmu2_out, coeff_frac_bits) , 8); out(d*3 + 1) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d*3 + 2) satsu(asr(vmu2_out, coeff_frac_bits), 8); else if ( output insertion mode == planar insertion mode ) then out(d + 0) satsu(asr(vmu0_out + vmu1_out+ vmu2_out, coeff_frac_bits), 8); out(d + 4) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d + 8) satsu(asr(vmu2_out, coeff_frac_bits), 8); vmu0_out coeff0_0 coeff0_1 coeff0_2 in(x+0) in(x+1) in(x+2) vmu0_out + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in(y+0) in(y+1) in(y+2) vmu1_out + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in(z+0) in(z+1) in(z+2) vmu2_out + = vmu0_out coeff0_0 coeff0_1 coeff0_2 in((x+0)%11) in((x+4)%11) in((x+8)%11) vmu0_out + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in((y+0)%11) in((y+4)%11) in((y+8)%11) vmu1_out + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in((z+0)%11) in((z+4)%11) in((z+8)%11) vmu2_out + = vmu0_out vmu1_out vmu2_out coeff0_0 coeff0_1 coeff0_2 coeff1_0 coeff1_1 coeff1_2 coeff2_0 coeff2_1 coeff2_2 inx iny inz vmu0_out vmu1_out vmu2_out + =
55 32003e?avr32?05/06 at32ap7000 syntax: i. picosvmac outd, inx, iny, inz operands: i. d {0, 1, 2, 3} x, y, z {0, 1, ..., 11} opcode: example: /* inner loop of a 16-tap symmetric fir filter with coefficients {c0, c1, c2, c3, c4, c5 , c6, c7, c7, ..., c0} set to filter the pixels pointed to by r12 storing the result to the memory poi nted to by r11. the coeffici ents in the pico are already set to the following values: coeff0_0 = c0, coeff0_1 = c1, coeff0_2 = c2, coeff1_0 = c3, coeff1_1 = c4, coeff1_2 = c5, coeff2_0 = c6, coeff2_1 = c7, coeff 2_2 = 0, offset0 = 0.5 (for rounding the result), offset1 = 0, offset2 = 0. the input selection mode is set to horizontal filter mode while the output insertion mode is set to planar insertion mode. the input image pointer might be unaligned, hence the use of ld.w instead of picold.w. */ ... ld.w r1, r12[0] /* r1 = *((int *)src) */ ld.w r0, r12[4] /* r0 = *(((int *)src) + 1) */ ld.w r2, r12[8] /* r2 = *(((int *)src) + 2) */ ld.w r3, r12[12] /* r3 = *(((int *)src) + 3) */ picomv.d inpix1:inpix2, r0 /* inpix1={src[0],src[1],sr c[2],src[3]}, inpix2={src[4],src[5],src[6],src[7]}*/ swap.b r2 /* r2 = {src[11],src[10],src[9],src[8]}*/ swap.b r3 /* r3 = {src[15],src[14],src[13],src[12]}*/ picosvmul out3, in4, in7, in10 /* vmu0_o ut = c0*src[0]+c1*src[1]+c2*src[2] + 0.5 vmu1_out = c3*src[3]+c4*src[4]+c5*src[5] vmu2_out = c6*src[6]+c7*src[7] */ picomv.d inpix1:inpix2, r2 /* inpix1 ={src[15],src[14], src[13],src[12]}, inpix2 ={src[11],src[ 10],src[9],src[8]} */ picosvmac out3, in4, in7, in10 /* vmu0_o ut += c0*src[15]+c1*src[14]+c2*src[13] vmu1_out += c3*src[12]+c4*src[11]+c5*src[10] vmu2_out += c6*src[9]+c7*src[8] out3 = satscaled(vmu0_out+vmu1_out+vmu2_out)*/ sub r12, -1 /* src++ */ picomv.w r4, outpix0 /* r4 = { out0, out1, out2, out3 } st.b r11++, r4 /* *dst = out3 */ ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111000011010011 out d[1] 1514131211109876543210 pico cp# out d[0] inx iny inz
56 32003e?avr32?05/06 at32ap7000 picosvmul ? pico single vector multiplication description performs three vector multiplications where the input pixels taken from the inpix n registers depends on the input selection mode and the input pixel addresses given in the instruction. the results from each vector multiplication unit (vmu) are then added together for one of the outputs to the output pixels inserter to form the result of a single vector multiplication of two 9-element vectors. the results from the vmus are then scaled and saturated to unsigned 8-bit values before being inserted into the outpix n registers. which pixels to update in the outpix n registers depend upon the output insertion mode and the output pixel address given in the instruction. operation: i. offset_scale = coeff_fr ac_bits - offset_frac_bits if ( input selection mode == horizontal filter mode ) then else if ( input selection mode == vertical filter mode ) then else if ( input selection mode == transformation mode ) then if ( output insertion mode == packed insertion mode ) then out(d*3 + 0) satsu(asr(vmu0_out + vmu1_out + vmu2_out, coeff_frac_bits), 8); out(d*3 + 1) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d*3 + 2) satsu(asr(vmu2_out, coeff_frac_bits), 8); else if ( output insertion mode == planar insertion mode ) then out(d + 0) satsu(asr(vmu0_out + vmu1_out+ vmu2_out, coeff_frac_bits), 8); out(d + 4) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d + 8) satsu(asr(vmu2_out, coeff_frac_bits), 8); vmu0_out coeff0_0 coeff0_1 coeff0_2 in(x+0) in(x+1) in(x+2) offset0 << offset_scale + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in(y+0) in(y+1) in(y+2) offset1 << offset_scale + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in(z+0) in(z+1) in(z+2) offset2 << offset_scale + = vmu0_out coeff0_0 coeff0_1 coeff0_2 in((x+0)%11) in((x+4)%11) in((x+8)%11) offset0 << offset_scale + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in((y+0)%11) in((y+4)%11) in((y+8)%11) offset1 << offset_scale + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in((z+0)%11) in((z+4)%11) in((z+8)%11) offset2 << offset_scale + = vmu0_out vmu1_out vmu2_out coeff0_0 coeff0_1 coeff0_2 coeff1_0 coeff1_1 coeff1_2 coeff2_0 coeff2_1 coeff2_2 inx iny inz offset0 << offset_scale offset1 << offset_scale offse20 << offset_scale + =
57 32003e?avr32?05/06 at32ap7000 syntax: i. picosvmul outd, inx, iny, inz operands: i. d {0, 1, 2, 3} x, y, z {0, 1, ... , 11} opcode: example: /* excerpt from inner loop of bilinear interpolation filter op erating on image component stor ed in an array pointed to by r12. the width of the image is stored in r11 while the result ing filtered image is pointed to by r10. the coefficients of the filter: a, b, c, d are already set before this code is executed. coeff0 _0 = a, coeff0_1 = b, coeff0_2 = 0, coeff1_0 = c, coeff1_1 = d, coeff1_2 = 0, coeff2_0 = 0, coeff2_1 = 0, coeff2_2 = 0, offset0 = 0.5 (for rounding the result), offset1 = 0, offset2 = 0. the input selection mode is set to horizontal filter mode while the output insertion mode is set to planar insertion mode. the input image pointer might be unaligned, hence the use of ld.w instead of picold.w, while the output image pointer is word aligned. four output pixels are computed in th is example which show an example of a bilinear inte rpolation filter found in the motion compensation used in the h.264 video standard. */ ... ld.w r1, r12[0] /* r1 = *((int *)src) */ ld.w r0, r12[r11] /* r0 = *((int *)(src + width)) */ sub r12, -2 /* src+=2 */ ld.w r3, r12[0] /* r3 = *((int *)src) */ ld.w r2, r12[r11] /* r2 = *((int *)(src + width)) */ picomv.d inpix1:inpix2, r0 /* inpix1 = r1, inpix2 = r0 */ picosvmul out0, in4, in8, in0 /* out0 = a*src[j][i+0] + b*src[j][i+1] c*src[j+1][i] + d*src[j+1][i+1] */ picosvmul out1, in5, in9, in0 /* out1 = a*src[j][i+1 ] + b*src[j][i+2] c*src[j+1] [i+1] + d*src[j+1][i+2] */ picomv.d inpix1:inpix2, r2 /* inpix1 = r3, inpix2 = r2 */ picosvmul out2, in4, in8, in0 /* out2 = a*src[j][i+2 ] + b*src[j][i+3] c*src[j+1] [i+2] + d*src[j+1][i+3] */ picosvmul out3, in5, in9, in0 /* out3 = a*src[j][i+3 ] + b*src[j][i+4] c*src[j+1] [i+3] + d*src[j+1][i+4] */ sub r12, -2 /* src+=2 */ picost.w r10++, outpix0 /* *((int *)src) = { out0, out1, out2, out3 } */ ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111000011010010 out d[1] 1514131211109876543210 pico cp# out d[0] inx iny inz
58 32003e?avr32?05/06 at32ap7000 picovmac ? pico vector mu ltiplication and accumulation description performs three vector multiplications where the input pixels taken from the inpix n registers depends on the input selection mode and the input pixel addresses given in the instruction. the values in the vmu n _out registers are then accumulated with the new results from the vector multiplications. the results from the vmus are then scaled and saturated to unsigned 8-bit values before being inserted into the outpix n registers. which pixels to update in the outpix n registers depend upon the output insertion mode and the output pixel address given in the instruction. operation: i. if ( input selection mode == horizontal filter mode ) then else if ( input selection mode == vertical filter mode ) then else if ( input selection mode == transformation mode ) then if ( output insertion mode == packed insertion mode ) then out(d*3 + 0) satsu(asr(vmu0_out, coeff_frac_bits), 8); out(d*3 + 1) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d*3 + 2) satsu(asr(vmu2_out, coeff_frac_bits), 8); else if ( output insertion mode == planar insertion mode ) then out(d + 0) satsu(asr(vmu0_out, coeff_frac_bits), 8); out(d + 4) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d + 8) satsu(asr(vmu2_out, coeff_frac_bits), 8); vmu0_out coeff0_0 coeff0_1 coeff0_2 in(x+0) in(x+1) in(x+2) vmu0_out + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in(y+0) in(y+1) in(y+2) vmu1_out + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in(z+0) in(z+1) in(z+2) vmu2_out + = vmu0_out coeff0_0 coeff0_1 coeff0_2 in((x+0)%11) in((x+4)%11) in((x+8)%11) vmu0_out + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in((y+0)%11) in((y+4)%11) in((y+8)%11) vmu1_out + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in((z+0)%11) in((z+4)%11) in((z+8)%11) vmu2_out + = vmu0_out vmu1_out vmu2_out coeff0_0 coeff0_1 coeff0_2 coeff1_0 coeff1_1 coeff1_2 coeff2_0 coeff2_1 coeff2_2 inx iny inz vmu0_out vmu1_out vmu2_out + =
59 32003e?avr32?05/06 at32ap7000 syntax: i. picovmac outd, inx, iny, inz operands: i. d {0, 1, 2, 3} x, y, z {0, 1, ... , 11} opcode: example: /* inner loop of a 6-tap symmetric fir filter with coefficients {c0, c1, c2, c2, c1, c0 } set to filter in the vertical direction of the image pointed to by r12 with the width of the image stored in r11 and the destinat ion image stored in r10. the coefficients in the pico are already set to the following values: coeff0_0 = c0, coeff0_1 = c1, coeff0_2 = c2, coeff1_0 = c0, coeff1_1 = c1, coeff1_2 = c2, coeff2_0 = c0, coeff2_1 = c1, coeff2_2 = c2, offset0 = offset1 = offset2 = 0.5 (for rounding the result). the input selection mode is set to vertical filter mode wh ile the output insertion mode is set to packed insertion mode. the input image is assumed to be word aligned. */ ... picold.w inpix0, r12[0] /* inpix0 = {src[0][0], src[0][1], src[0][2], src[0][3] }*/ picold.w inpix1, r12[r11] /* inpix1 = {src[1][0], src[1][1], src[1][2], src[1][3] }*/ picold.w inpix2, r12[r11 << 1] /* inpix2 = {src[2][0], src[2][1], src[2][2], src[2][3] }*/ add r9, r12, r11 /* r9 = src + width */ picovmul out0, in0, in1, in2 /* vmu0_out = c 0*src[0][0]+c1*src[1][0]+c2*src[2][0] + 0.5 vmu1_out = c0*src[0][1]+c1* src[1][1]+c2*src[2][1] + 0.5 vmu2_out = c0*src[0][2]+c1*sr c[1][2]+c2*src[2][2] + 0.5*/ picold.w inpix2, r9[r11 << 1] /* inpix2 = {src[3][0], src[3][1], src[3][2], src[3][3] }*/ picold.w inpix1, r12[r11 << 2] /* inpix1 = {src[4][0], src[4][1], src[4][2], src[4][3] }*/ picold.w inpix0, r9[r11 << 2] /* inpix0 = {src[5][0], src[5][1], src[5][2], src[5][3] }*/ picovmac out0, in0, in1, in2 /* vmu0_out += c0*src[5][0]+c1*src[4][0]+c2*src[3][0] vmu1_out += c0*src[5][1]+c1*src[4][1]+c2*src[3][1] vmu2_out += c0*src[5][2]+c1*src[4][2]+c2*src[3][2] out0 = satscale(vmu0_out), out1 = satscale(vmu1_out), out2 = satscale(vmu2_out) */ .... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111000011010001 out d[1] 1514131211109876543210 pico cp# out d[0] inx iny inz
60 32003e?avr32?05/06 at32ap7000 picovmul ? pico vector multiplication description performs three vector multiplications where the input pixels taken from the inpix n registers depends on the input selection mode and the input pixel addresses given in the instruction. the results from the vmus are then scaled and saturated to unsigned 8-bit values before being inserted into the outpix n registers. which pixels to update in the outpix n registers depend upon the output insertion mode and the output pixel address given in the instruction. operation: i. offset_scale = coeff_fr ac_bits - offset_frac_bits if ( input selection mode == horizontal filter mode ) then else if ( input selection mode == vertical filter mode ) then else if ( input selection mode == transformation mode ) then if ( output insertion mode == packed insertion mode ) then out(d*3 + 0) satsu(asr(vmu0_out, coeff_frac_bits), 8); out(d*3 + 1) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d*3 + 2) satsu(asr(vmu2_out, coeff_frac_bits), 8); else if ( output insertion mode == planar insertion mode ) then out(d + 0) satsu(asr(vmu0_out, coeff_frac_bits), 8); out(d + 4) satsu(asr(vmu1_out, coeff_frac_bits), 8); out(d + 8) satsu(asr(vmu2_out, coeff_frac_bits), 8); vmu0_out coeff0_0 coeff0_1 coeff0_2 in(x+0) in(x+1) in(x+2) offset0 << offset_scale + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in(y+0) in(y+1) in(y+2) offset1 << offset_scale + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in(z+0) in(z+1) in(z+2) offset2 << offset_scale + = vmu0_out coeff0_0 coeff0_1 coeff0_2 in((x+0)%11) in((x+4)%11) in((x+8)%11) offset0 << offset_scale + = vmu1_out coeff1_0 coeff1_1 coeff1_2 in((y+0)%11) in((y+4)%11) in((y+8)%11) offset1 << offset_scale + = vmu2_out coeff2_0 coeff2_1 coeff2_2 in((z+0)%11) in((z+4)%11) in((z+8)%11) offset2 << offset_scale + = vmu0_out vmu1_out vmu2_out coeff0_0 coeff0_1 coeff0_2 coeff1_0 coeff1_1 coeff1_2 coeff2_0 coeff2_1 coeff2_2 inx iny inz offset0 << offset_scale offset1 << offset_scale offse20 << offset_scale + =
61 32003e?avr32?05/06 at32ap7000 syntax: i. picovmul outd, inx, iny, inz operands: i. d {0, 1, 2, 3} x, y, z {0, 1, ... , 11} opcode: example: /* excerpt from inner loop of ycrcb 4:2:2 planar format to rgb packed format image colo r conversion. the coefficients of the transform is already set before this code is executed. in transforms like this, the inputs y, cr and cb are often offsetted with a given amount. this offset can be factored out and included in the offsets like this: 1.164*(y - 16) = 1.164*y - 18.625. the pointer to the y component is in r12, the pointer to the cr component in r11 and the pointer to the cb component in r10. the pointer to the rgb output image is in r9. the input selection mode is set to transform mode while the output insertion mode is set to packed insertion mode. it is assumed that all the input and output pointers are word aligned. four rgb triplets are com puted in this example. */ ... picold.w inpix0, r12++ /* inpix0= { y[0], y[1], y[ 2], y[3] }*/ picold.w inpix1, r11++ /* inpix1= { cr[0], cr[1], cr[2], cr[3] }*/ picold.w inpix2, r10++ /* inpix2= { cb[0], cb[1], cb[2], cb[3] }*/ picovmul out0, in0, in4, in8 /* out0 = r[0], out1 = g[0], out2 = b[0] */ picovmul out1, in1, in4, in8 /* out3 = r[1], out4 = g[1], out5 = b[1] */ picovmul out2, in2, in5, in9 /* out6 = r[2], out7 = g[2], out8 = b[2] */ picovmul out3, in3, in5, in9 /* out9 = r[3], out10 = g[3], out11 = b[3] */ picostm r9, outpix2, outpix1, outpix0/* rgb = {r[0],g[ 0],b[0],r[1],g[1],b[1],r[2],g[2],b[2],r[3],g[3],b[3]} */ ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111000011010000 out d[1] 1514131211109876543210 pico cp# out d[0] inx iny inz
62 32003e?avr32?05/06 at32ap7000 picold.{d,w} ? load pico register(s) description reads the memory location specified into the given coprocessor register(s). operation: i. prhi:prlo *(rp + (ze(disp8) << 2)); ii. rp rp-8; prhi:prlo *(rp); iii. prhi:prlo *(rb + (ri << sa2)); iv. pr *(rp + (ze(disp8) << 2)); v. r p rp-4; pr *(rp); vi. pr *(rb + (ri << sa2)); syntax: i. picold.d prhi:prlo, rp[disp] ii. picold.d prhi:prlo, --rp iii. picold.d prhi:prlo, rb[ri< 63 32003e?avr32?05/06 at32ap7000 iii. iv. v. vi. example: picold.d coeff0_b:coeff0_a, r12[4] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rp 1514131211109876543210 pico cp# 1 prlo[3:1] 0 0 1 shamt ri 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111010011010 rp 1514131211109876543210 pico cp# 0 pr disp8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rp 1514131211109876543210 pico cp# 0 pr 0 1 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rp 1514131211109876543210 pico cp# 1 pr 0 0 shamt ri
64 32003e?avr32?05/06 at32ap7000 picoldm ? load multiple pico registers description reads the memory locations specified into the given pico regist ers. the pointer register can optionally be updated after the operation. operation: i. ii. iii. loadaddress rp; if ( picoreglist contains config ) config *(loadaddress++); if ( picoreglist contains vmu2_out ) vmu2_out *(loadaddress++); if ( picoreglist contains vmu1_out ) vmu1_out *(loadaddress++); if ( picoreglist contains vmu0_out ) vmu0_out *(loadaddress++); if ( picoreglist contains coeff2_b) coeff2_b *(loadaddress++); if ( picoreglist contains coeff2_a) coeff2_a *(loadaddress++); if ( picoreglist contains coeff1_b) coeff1_b *(loadaddress++); if ( picoreglist contains coeff1_a) coeff1_a *(loadaddress++); if ( picoreglist contains coeff0_b) coeff0_b *(loadaddress++); if ( picoreglist contains coeff0_a) coeff0_a *(loadaddress++); if ( picoreglist contains outpix0) loadaddress++; if ( picoreglist contains outpix1) loadaddress++; if ( picoreglist contains outpix2) loadaddress++; if ( picoreglist contains inpix0) inpix0 *(loadaddress++); if ( picoreglist contains inpix1) inpix1 *(loadaddress++); if ( picoreglist contains inpix2) inpix2 *(loadaddress++); if opcode[++] == 1 then rp loadaddress; syntax: i. picoldm rp{++}, picoreglist ii. picoldm rp{++}, picoreglist iii. picoldm rp{++}, picoreglist operands: i. picoreglist { {inpix1, inpix2}, {out pix2, inpix0}, {outpix0, ou tpix1}, {coeff0_b, coeff0_a}, {coeff1_b, coeff1_a}, {coeff2_b, coeff2_a}, {vmu1_out, vmu0_out},
65 32003e?avr32?05/06 at32ap7000 {config, vmu2_out} } ii. picoreglist { inpix0, inpix1, inpix2, outpix0, outpix1, outpix2, coeff0_a, coeff0_b } iii. picoreglist { coeff1_a, coeff1_b, coeff2_a,coeff2_b, vmu0_out,vmu1_out, vmu2_out, config, } i-iii. p {0, 1, ?, 15} opcode i. ii. iii. example: i. picoldm r7++, coeff0_a, coeff0_b, co eff1_a, coeff1_b, coeff2_a, coeff2_b ii. picoldm r0, inpix0, inpix1, inpix2 iii. picoldm r12, vmu0_out, vmu1_out, vmu2_out 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11101101 1 0 1 0 rp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pico cp# w 0 1 0 0 config vmu2_out vmu1_out vmu0_out coeff2_b coeff2_a coeff1_b coeff1_a coeff0_b coeff0_a outpix0 outpix1 outpix2 inpix0 inpix1 inpix2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11101101 1 0 1 0 rp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pico cp# w 0 0 0 0 coeff0_b coeff0_a outpix0 outpi x1 outpix2 inpix0 inpix1 inpix2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11101101 1 0 1 0 rp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pico cp# w 0 0 0 1 config vmu2_out vmu1_out vmu0_out co eff2_b coeff2_a co eff1_b coeff1_a
66 32003e?avr32?05/06 at32ap7000 picomv.{d,w} ? move between pico register(s) and register file description move the specified pico register(s) to register(s) in the register file or move register(s) in th e register file to pico regis- ter(s). operation: i. prhi:prlo (rs+1:rs); ii. pr rs; iii. (rd+1:rd) prhi:prlo; iv. rd pr; syntax: i. picomv.d prhi:prlo, rs ii. picomv.w pr, rs iii. picomv.d rd, prhi:prlo iv. picomv.w rd, pr operands: i, ii. prhi:prlo { inpix1:inpix2, outpix2:inpix0, outpix0:outpix1, coeff0_b:coeff0_a, coeff1_b:coeff1_a, coeff2_b:coeff2_a, vmu1_out:vmu0_out, config:vmu2_out } ii, iv. pr { inpix0, inpix1, inpix2, outpix0, outpix1, outpix2, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0 _out, vmu1_out, vmu2_out, config} i. s {0, 2, 4, ?, 14} iii. d {0, 2, 4, ?, 14} ii. s {0, 1, ?, 15} iv. d {0, 1, ?, 15} opcode i. ii. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rs 0 1514131211109876543210 pico cp# 0 prlo[3:1] 000110000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rs 1514131211109876543210 pico cp# 0 pr 00100000
67 32003e?avr32?05/06 at32ap7000 iii. iv. example: picomv.d r2, outpix0:outpix1 picomv.w config, lr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rd 0 1514131211109876543210 pico cp# 0 prlo[3:1] 000010000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rd 1514131211109876543210 pico cp# 0 pr 00000000
68 32003e?avr32?05/06 at32ap7000 picost.{d,w} ? store pico register(s) description stores the pico register value(s) to the memory location specified by the addressing mode. operation: i. *(rp + (ze(disp8) << 2)) prhi:prlo; ii. *(rp) prhi:prlo; rp rp+8; iii. *(rb + (ri << sa2)) prhi:prlo; iv. *(rp + (ze(disp8) << 2)) pr; v. * ( r p ) pr; rp rp-4; vi. *(rb + (ri << sa2)) pr; syntax: i. picost.d rp[disp], prhi:prlo ii. picost.d rp++, prhi:prlo iii. picost.d rb[ri< 69 32003e?avr32?05/06 at32ap7000 iii. iv. v. vi. example: picost.w r10++, outpix0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rp 1514131211109876543210 pico cp# 1 prlo[3:1] 0 1 1 shamt ri 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111010111010 rp 1514131211109876543210 pico cp# 0 pr disp8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rp 1514131211109876543210 pico cp# 0 pr 0 1 1 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 111011111010 rp 1514131211109876543210 pico cp# 1 pr 1 0 shamt ri
70 32003e?avr32?05/06 at32ap7000 picostm ? store multiple pico registers description writes the pico registers specified in the regi ster list into the spec ified memory locations. operation: i. ii. iii. if opcode[--] == 1 then rp rp - 4*registersinlist; storeaddress rp; if ( picoreglist contains config ) *(storeaddress++) config; if ( picoreglist contains vmu2_out ) *(storeaddress++) vmu2_out; if ( picoreglist contains vmu1_out ) *(storeaddress++) vmu1_out; if ( picoreglist contains vmu0_out ) *(storeaddress++) vmu0_out; if ( picoreglist contains coeff2_b) *(storeaddress++) coeff2_b; if ( picoreglist contains coeff2_a) *(storeaddress++) coeff2_a; if ( picoreglist contains coeff1_b) *(storeaddress++) coeff1_b; if ( picoreglist contains coeff1_a) *(storeaddress++) coeff1_a; if ( picoreglist contains coeff0_b) *(storeaddress++) coeff0_b; if ( picoreglist contains coeff0_a) *(storeaddress++) coeff0_a; if ( picoreglist contains outpix0) *(storeaddress++) outpix0; if ( picoreglist contains outpix1) *(storeaddress++) outpix1; if ( picoreglist contains outpix2) *(storeaddress++) outpix2; if ( picoreglist contains inpix0) *(storeaddress++) inpix0 ; if ( picoreglist contains inpix1) *(storeaddress++) inpix1 ; if ( picoreglist contains inpix2) *(storeaddress++) inpix2 ; syntax: i. picostm {--}rp, picoreglist ii. picostm {--}rp, picoreglist iii. picostm {--}rp, picoreglist operands: i. picoreglist { {inpix1, inpix2}, {out pix2, inpix0}, {outpix0, ou tpix1}, {coeff0_b, coeff0_a}, {coeff1_b, coeff1_a}, {coeff2_b, coeff2_a}, {vmu1_out, vmu0_out},
71 32003e?avr32?05/06 at32ap7000 {config, vmu2_out} } ii. picoreglist { inpix0, inpix1, inpix2, outpix0, outpix1, outpix2, coeff0_a, coeff0_b } iii. picoreglist { coeff1_a, coeff1_b, coeff2_a,coeff2_b, vmu0_out,vmu1_out, vmu2_out, config, } i-iii. p {0, 1, ?, 15} opcode i. ii. iii. example: i. picostm --r7, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b ii. picostm r2, outpix0, outpix1, outpix2 iii. picostm r11, vmu0_out, vmu1_out, vmu2_out 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11101101 1 0 1 0 rp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pico cp# w 0 1 0 1 config vmu2_out vmu1_out vmu0_out coeff2_b coeff2_a coeff1_b coeff1_a coeff0_b coeff0_a outpix0 outpix1 outpix2 inpix0 inpix1 inpix2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11101101 1 0 1 0 rp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pico cp# w 0 0 1 0 coeff0_b coeff0_a outpix0 outpi x1 outpix2 inpix0 inpix1 inpix2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 11101101 1 0 1 0 rp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pico cp# w 0 0 1 1 config vmu2_out vmu1_out vmu0_out co eff2_b coeff2_a co eff1_b coeff1_a
72 32003e?avr32?05/06 at32ap7000 8.9 data hazards data hazards are caused by data dependencies between instructions which are in different stages of the pipeline and reads/writes registers which are common to several pipeline stages. because of the 3-stage pipeline employed in the pico data hazards might exist between instruc- tions. data hazards are handled by hardware interlocks which can stall a new read command from or write command to the pico register file. table 8-5. data hazards instruction next instruction condition stall cycles picovmul picovmac picosvmul picosvmac picomv.x pr,... picold.x picoldm write-after-read (war) or write-after-write (waw) hazard will occur if writing coeff n _a/b, vmu n _out or config since these ar e accessed when the pico command is in pipeline stage 2 and pipeline stage 3. 1 writes to inpix n registers produces no hazard since they are only accessed in pipeline stage 1. 0 picomv.x rd,... picost.x picostm read-after-write hazard (r aw) will occur if reading the pico register file while a command is in the pipeline. 2
73 32003e?avr32?05/06 at32ap7000 9. memories 9.1 embedded memories ? 32 kbyte sram ? implemented as two 16kbyte blocks ? single cycle access at full bus speed 9.2 physical memory map the system bus is implemented as an ahb bus matrix. all system bus addresses are fixed, and they are never remapped in any way, not even in boot. note that avr32ap7000 by default uses segment translation, as described in the avr 32 architecture manual. the 32 bit physical address space is mapped as follows: accesses to unused areas returns an error result to the master requesting such an access. the bus matrix has the several masters and slaves. each master has its own bus and its own decoder, thus allowing a different memory mapping per master. the master number in the table below can be used to index the hmatrix contro l registers. for example, mcfg2 is associated with the ahb-ahb bridge. table 9-1. avr32ap7000 physical memory map start address size device 0x0000_0000 64 mbyte ebi sram cs0 0x0400_0000 64 mbyte ebi sram cs4 0x0800_0000 64 mbyte ebi sram cs2 0x0c00_0000 64 mbyte ebi sram cs3 0x1000_0000 256 mbyte ebi sram/sdram cs1 0x2000_0000 64 mbyte ebi sram cs5 0x2400_0000 16 kbyte internal sram 0 0x2400_4000 16 kbyte internal sram1 0xff00_0000 4 kbyte lcdc configuration 0xff20_0000 1 kbyte dmac configuration 0xff30_0000 1 mbyte usb data 0xffe0_0000 1 mbyte apba 0xfff0_0000 1 mbyte apbb
74 32003e?avr32?05/06 at32ap7000 each slave has its own arbiter, thus allowing a different arbitration per slave. the slave number in the table below can be used to index the hmatrix control registers. for example, scfg3 is associated with apbb. table 9-2. ahb masters master 0 cpu dcache master 1 cpu icache master 2 ahb-ahb bridge master 3 isi dma master 4 usb dma master 5 lcd controller dma master 6 ethernet mac0 dma master 7 ethernet mac1 dma master 8 dmac master interface 0 master 9 dmac master interface 1 table 9-3. ahb slaves slave 0 internal sram 0 slave 1 internal sram1 slave 2 apba slave 3 apbb slave 4 ebi slave 5 usb data slave 6 lcdc configuration slave 7 dmac configuration
75 32003e?avr32?05/06 at32ap7000 10. peripherals 10.1 peripheral address map table 10-1. peripheral address mapping address peripheral name bus 0xff000000 lcdc lcd controller slave interface - lcdc ahb 0xff200000 dmac dma controller slave interface- dmac ahb 0xff300000 usb usb 2.0 slave interface - usb ahb 0xffe00000 spi0 serial peripheral interface - spi0 apb a 0xffe00400 spi1 serial peripheral interface - spi1 apb a 0xffe00800 twi two-wire interface - twi apb a 0xffe00c00 usart0 universal synchronous asynchronous receiver transmitter - usart0 apb a 0xffe01000 usart1 universal synchronous asynchronous receiver transmitter - usart1 apb a 0xffe01400 usart2 universal synchronous asynchronous receiver transmitter - usart2 apb a 0xffe01800 usart3 universal synchronous asynchronous receiver transmitter - usart3 apb a 0xffe01c00 ssc0 synchronous serial controller - ssc0 apb a 0xffe02000 ssc1 synchronous serial controller - ssc1 apb a 0xffe02400 ssc2 synchronous serial controller - ssc2 apb a 0xffe02800 pioa parallel input/output 2 - pioa apb a 0xffe02c00 piob parallel input/output 2 - piob apb a 0xffe03000 pioc parallel input/output 2 - pioc apb a
76 32003e?avr32?05/06 at32ap7000 0xffe03400 piod parallel input/output 2 - piod apb a 0xffe03800 pioe parallel input/output 2 - pioe apb a 0xffe03c00 psif ps2 interface - psif apb a 0xfff00000 sm system manager - sm apb b 0xfff00400 intc interrupt controller - intc apb b 0xfff00800 hmatrix ahb matrix - hmatrix apb b 0xfff00c00 tc0 timer/counter - tc0 apb b 0xfff01000 tc1 timer/counter - tc1 apb b 0xfff01400 pwm pulse width mo dulation controller - pwm apb b 0xfff01800 macb0 ethernet mac - macb0 apb b 0xfff01c00 macb1 ethernet mac - macb1 apb b 0xfff02000 dac dac - audio dac apb b 0xfff02400 mci mulitmedia card interface - mci apb b 0xfff02800 ac97c ac97 contro ller - ac97c apb b 0xfff02c00 isi image sensor interface - isi apb b 0xfff03000 usb usb 2.0 configurati on interface - usb apb b 0xfff03400 smc static memory controller - smc apb b 0xfff03800 sdramc sdram controller - sdramc apb b table 10-1. peripheral address mapping (continued) address peripheral name bus
77 32003e?avr32?05/06 at32ap7000 10.2 interrupt r equest signal map the various modules may output interrupt request signals. these signals are routed to the inter- rupt controller (intc), see section 13. ?interrupt controller? on page 128 . the interrupt controller supports up to 64 groups of interrupt requests. each group can have up to 32 interrupt request signals. all interrupt signals in the same group share the same autovector address and priority level. refer to the documentation for the individual submodules for a description of the semantic of the different interrupt requests. the interrupt request signals in avr32ap7000 are connected to the intc as follows: 0xfff03c00 ecc error correcting code controller - ecc apb b table 10-1. peripheral address mapping (continued) address peripheral name bus table 10-2. interrupt request signal map group line signal 0 0 count-compare match 1 performance counter overflow 1 0 lcdc eof 1 lcdc ln 2 lcdc lstln 3 lcdc mer 4 lcdc owr 5 lcdc uflw 2 0 dmac block 1 dmac dstt 2dmac err 3 dmac srct 4dmac tfr 3 0 spi 0 4 0 spi 1 50twi 6 0 usart 0 7 0 usart 1 8 0 usart 2 9 0 usart 3 10 0 ssc 0
78 32003e?avr32?05/06 at32ap7000 11 0 ssc 1 12 0 ssc 2 13 0 pio a 14 0 pio b 15 0 pio c 16 0 pio d 17 0 pio e 18 0 psif 19 0 eim 0 1eim 1 2eim 2 3eim 3 20 0 pm 21 0 rtc 22 0 tc0 0 1tc0 1 2tc0 2 23 0 tc1 0 1tc1 1 2tc1 2 24 0 pwm 25 0 macb0 26 0 macb1 27 0 dac 28 0 mci 29 0 ac97c 30 0 isi 31 0 usb 32 0 hebi table 10-2. interrupt request signal map group line signal
79 32003e?avr32?05/06 at32ap7000 10.3 dmac handshake interface map the following table details the hardware h andshake map between the dmac and the peripher- als attached to it: : table 10-3. hardware handshaking connection request hardware handshaking interface mci rx 0 mci tx 1 dac tx 2 ac97c channel a rx 3 ac97c channel a tx 4 ac97c channel b rx 5 ac97c channel b tx 6 external dma request 0 7 external dma request 1 8 external dma request 2 9 external dma request 3 10
80 32003e?avr32?05/06 at32ap7000 10.4 clock connections 10.4.1 timer/counters each timer/counter channel can independently select an internal or external clock source for its counter: 10.4.2 usarts each usart can be connected to an internally divided clock: table 10-4. timer/counter clock connections timer/counter source name connection 0 internal timer_clock1 clk_slow timer_clock2 clk_apbb / 4 timer_clock3 clk_apbb / 8 timer_clock4 clk_apbb / 16 timer_clock5 clk_apbb / 32 external xc0 see section 10.7 xc1 xc2 1 internal timer_clock1 clk_slow timer_clock2 clk_apbb / 4 timer_clock3 clk_apbb / 8 timer_clock4 clk_apbb / 16 timer_clock5 clk_apbb / 32 external xc0 see section 10.7 xc1 xc2 table 10-5. usart clock connections usart source name connection 0 internal clk_div clk_apba / 8 1 2 3
81 32003e?avr32?05/06 at32ap7000 10.4.3 spis each spi can be connected to an internally divided clock: 10.5 external inte rrupt pin mapping external interrupt requests are connected to the following pins:: 10.6 nexus ocd aux port connections if the ocd trace system is enabled, the trace system will take control over a number of pins, irre- spectively of the pio configuration. two different ocd trace pi n mappings are possible, depending on the configuration of the ocd axs register. for details, see the avr32 ap techni- cal reference manual. table 10-6. spi clock connections spi source name connection 0 internal clk_div clk_apba / 32 1 table 10-7. external interrupt pin mapping source connection nmi_n pb24 extint0 pb25 extint1 pb26 extint2 pb27 extint3 pb28 table 10-8. nexus ocd aux port connections pin axs=0 axs=1 evti_n evti_n evti_n mdo[5] pb09 pc18 mdo[4] pb08 pc14 mdo[3] pb07 pc12 mdo[2] pb06 pc11 mdo[1] pb05 pc06 mdo[0] pb04 pc05 evto_n pb03 pb28 mcko pb02 pc02 mseo[1] pb01 pc01 mseo[0] pb00 pc00
82 32003e?avr32?05/06 at32ap7000 10.7 peripheral multiplexing on io lines the at32ap7000 features five pio controllers, pioa to pioe, that multiplex the i/o lines of the peripheral set. each pio controller controls up to thirty-two lines. each line can be assigned to one of two peripheral functions, a or b. the tables in the following pages define how the i/o lines of the peripherals a and b are multiplexed on the pio controllers. note that some output only peripheral func tions might be duplicated within the tables. 10.7.1 pio controller a multiplexing table 10-9. pio controller a multiplexing i/o line peripheral a peripheral b pa00 spi0 - miso[0] ssc1 - rx_frame_sync[0] pa01 spi0 - mosi[0] ssc1 - tx_frame_sync[0] pa02 spi0 - sck[0] ssc1 - tx_clock[0] pa03 spi0 - npcs[0] ssc1 - rx_clock[0] pa04 spi0 - npcs[1] ssc1 - tx_data[0] pa05 spi0 - npcs[2] ssc1 - rx_data[0] pa06 twi - sda[0] usart0 - rts[0] pa07 twi - scl[0] usart0 - cts[0] pa08 psif - clock[0] usart0 - rxd[0] pa09 psif - data[0] usart0 - txd[0] pa10 mci - clk[0] usart0 - clk[0] pa11 mci - cmd[0] tc0 - clk0[0] pa12 mci - data[0] tc0 - a0[0] pa13 mci - data[1] tc0 - a1[0] pa14 mci - data[2] tc0 - a2[0] pa15 mci - data[3] tc0 - b0[0] pa16 usart1 - clk[0] tc0 - b1[0] pa17 usart1 - rxd[0] tc0 - b2[0] pa18 usart1 - txd[0] tc0 - clk2[0] pa19 usart1 - rts[0] tc0 - clk1[0] pa20 usart1 - cts[0] spi0 - npcs[3] pa21 ssc0 - rx_frame_sync[0] pwm - pwm[2] pa22 ssc0 - rx_clock[0] pwm - pwm[3] pa23 ssc0 - tx_clock[0] tc1 - a0[0] pa24 ssc0 - tx_frame_sync[0] tc1 - a1[0] pa25 ssc0 - tx_data[0] tc1 - b0[0] pa26 ssc0 - rx_data[0] tc1 - b1[0] pa27 spi1 - npcs[3] tc1 - clk0[0] pa28 pwm - pwm[0] tc1 - a2[0]
83 32003e?avr32?05/06 at32ap7000 10.7.2 pio controller b multiplexing pa29 pwm - pwm[1] tc1 - b2[0] pa30 sm - gclk[0] tc1 - clk1[0] pa31 sm - gclk[1] tc1 - clk2[0] table 10-9. pio controller a multiplexing table 10-10. pio controller b multiplexing i/o line peripheral a peripheral b pb00 isi - data[0] spi1 - miso[0] pb01 isi - data[1] spi1 - mosi[0] pb02 isi - data[2] spi1 - npcs[0] pb03 isi - data[3] spi1 - npcs[1] pb04 isi - data[4] spi1 - npcs[2] pb05 isi - data[5] spi1 - sck[0] pb06 isi - data[6] mci - cmd[1] pb07 isi - data[7] mci - data[4] pb08 isi - hsync[0] mci - data[5] pb09 isi - vsync[0] mci - data[6] pb10 isi - pclk[0] mci - data[7] pb11 psif - clock[1] isi - data[8] pb12 psif - data[1] isi - data[9] pb13 ssc2 - tx_data[0] isi - data[10] pb14 ssc2 - rx_data[0] isi - data[11] pb15 ssc2 - tx_clock[0] usart3 - cts[0] pb16 ssc2 - tx_frame_sync[0] usart3 - rts[0] pb17 ssc2 - rx_frame_sync[0] usart3 - txd[0] pb18 ssc2 - rx_clock[0] usart3 - rxd[0] pb19 sm - gclk[2] usart3 - clk[0] pb20 dac - data[1] ac97c - sdo[0] pb21 dac - data[0] ac97c - sync[0] pb22 dac - datan[1] ac97c - sclk[0] pb23 dac - datan[0] ac97c - sdi[0] pb24 nmi_n dmac - dmarq[0] pb25 extint0 dmac - dmarq[1] pb26 extint1 usart2 - rxd[0] pb27 extint2 usart2 - txd[0] pb28 extint3 usart2 - clk[0] pb29 sm - gclk[3] usart2 - cts[0] pb30 sm - gclk[4] usart2 - rts[0]
84 32003e?avr32?05/06 at32ap7000 10.7.3 pio controller c multiplexing table 10-11. pio controller c multiplexing i/o line peripheral a peripheral b pc00 macb0 - col[0] pc01 macb0 - crs[0] pc02 macb0 - tx_er[0] pc03 macb0 - txd[0] pc04 macb0 - txd[1] pc05 macb0 - txd[2] dmac - dmarq[2] pc06 macb0 - txd[3] dmac - dmarq[3] pc07 macb0 - tx_en[0] pc08 macb0 - tx_clk[0] pc09 macb0 - rxd[0] pc10 macb0 - rxd[1] pc11 macb0 - rxd[2] pc12 macb0 - rxd[3] pc13 macb0 - rx_er[0] pc14 macb0 - rx_clk[0] pc15 macb0 - rx_dv[0] pc16 macb0 - mdc[0] pc17 macb0 - mdio[0] pc18 macb0 - speed[0] pc19 lcdc - cc[0] macb1 - col[0] pc20 lcdc - hsync[0] pc21 lcdc - pclk[0] pc22 lcdc - vsync[0] pc23 lcdc - dval[0] macb1 - crs[0] pc24 lcdc - mode[0] macb1 - rx_clk[0] pc25 lcdc - pwr[0] pc26 lcdc - data[0] macb1 - tx_er[0] pc27 lcdc - data[1] macb1 - txd[2] pc28 lcdc - data[2] macb1 - txd[3] pc29 lcdc - data[3] macb1 - rxd[2] pc30 lcdc - data[4] macb1 - rxd[3] pc31 lcdc - data[5]
85 32003e?avr32?05/06 at32ap7000 10.7.4 pio controller d multiplexing table 10-12. pio controller d multiplexing i/o line peripheral a peripheral b pd00 lcdc - data[6] pd01 lcdc - data[7] pd02 lcdc - data[8] macb1 - mdio[0] pd03 lcdc - data[9] macb1 - mdc[0] pd04 lcdc - data[10] macb1 - rx_dv[0] pd05 lcdc - data[11] macb1 - rx_er[0] pd06 lcdc - data[12] macb1 - rxd[1] pd07 lcdc - data[13] pd08 lcdc - data[14] pd09 lcdc - data[15] pd10 lcdc - data[16] macb1 - rxd[0] pd11 lcdc - data[17] macb1 - tx_en[0] pd12 lcdc - data[18] macb1 - tx_clk[0] pd13 lcdc - data[19] macb1 - txd[0] pd14 lcdc - data[20] macb1 - txd[1] pd15 lcdc - data[21] macb1 - speed[0] pd16 lcdc - data[22] pd17 lcdc - data[23]
86 32003e?avr32?05/06 at32ap7000 10.7.5 pio controller e multiplexing table 10-13. pio controller e multiplexing i/o line peripheral a peripheral b pe00 hebi - data[16] lcdc - cc[0] pe01 hebi - data[17] lcdc - dval[0] pe02 hebi - data[18] lcdc - mode[0] pe03 hebi - data[19] lcdc - data[0] pe04 hebi - data[20] lcdc - data[1] pe05 hebi - data[21] lcdc - data[2] pe06 hebi - data[22] lcdc - data[3] pe07 hebi - data[23] lcdc - data[4] pe08 hebi - data[24] lcdc - data[8] pe09 hebi - data[25] lcdc - data[9] pe10 hebi - data[26] lcdc - data[10] pe11 hebi - data[27] lcdc - data[11] pe12 hebi - data[28] lcdc - data[12] pe13 hebi - data[29] lcdc - data[16] pe14 hebi - data[30] lcdc - data[17] pe15 hebi - data[31] lcdc - data[18] pe16 hebi - addr[23] lcdc - data[19] pe17 hebi - addr[24] lcdc - data[20] pe18 hebi - addr[25] lcdc - data[21] pe19 hebi - cfce1[0] pe20 hebi - cfce2[0] pe21 hebi - ncs[4] pe22 hebi - ncs[5] pe23 hebi - cfrnw[0] pe24 hebi - nwait[0] pe25 hebi - ncs[2] pe26 hebi - sdcs[0]
87 32003e?avr32?05/06 at32ap7000 10.7.6 io pins without multiplexing many of the external ebi pins are not controlled by the pio modules, but directly driven by the ebi. these pins have programmable pullup resistor s. these resistors are controlled by special function register 4 (sfr4) in the hmatrix. the pullup on the lines multiplexed with pio is controlled by the appropriate pio control register. this sfr can also control compactflash, smartmedia or nandflash support, see section ?16.? on page 155. 10.7.6.1 hmatrix sfr4 ebi control register name: hmatrix_sfr4 access type: read/write ? cs1a: chip select 1 assignment 0 = chip select 1 is assigned to the static memory controller. 1 = chip select 1 is assign ed to the sdram controller. ? cs3a: chip select 3 assignment 0 = chip select 3 is only assigned to the static memory contro ller and ncs3 behaves as defined by the smc. 1 = chip select 3 is assigned to the static memory controller and the nand flash/smartmedia logic is activated. ? cs4a: chip select 4 assignment 0 = chip select 4 is assigned to the stat ic memory controller and ncs4, ncs5 and ncs6 behave as defined by the smc. 1 = chip select 4 is assigned to the static memory controller and the compactflash logic is activated. ? cs5a: chip select 5 assignment 0 = chip select 5 is assigned to the stat ic memory controller and ncs4, ncs5 and ncs6 behave as defined by the smc. 1 = chip select 5 is assigned to the static memory controller and the compactflash logic is activated. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????ebi_dbpuc 76543210 ? ? ebi_cs5a ebi_cs4a ebi_cs3a ? ebi_cs1a -
88 32003e?avr32?05/06 at32ap7000 accessing the address space reserved to ncs5 and ncs6 may lead to an unpredictable outcome. ? ebi_dbpuc: ebi data bus pull-up control 0: ebi d[15:0] are internally pulled up to the vddio power supply. the pull-up resistors are enabled after reset. 1: ebi d[15:0] are not internally pulled up. table 10-14. io pins without multiplexing i/o line function px00 hebi - data[0] px01 hebi - data[1] px02 hebi - data[2] px03 hebi - data[3] px04 hebi - data[4] px05 hebi - data[5] px06 hebi - data[6] px07 hebi - data[7] px08 hebi - data[8] px09 hebi - data[9] px10 hebi - data[10] px11 hebi - data[11] px12 hebi - data[12] px13 hebi - data[13] px14 hebi - data[14] px15 hebi - data[15] px16 hebi - addr[0] px17 hebi - addr[1] px18 hebi - addr[2] px19 hebi - addr[3] px20 hebi - addr[4] px21 hebi - addr[5] px22 hebi - addr[6] px23 hebi - addr[7] px24 hebi - addr[8] px25 hebi - addr[9] px26 hebi - addr[10] px27 hebi - addr[11] px28 hebi - addr[12] px29 hebi - addr[13] px30 hebi - addr[14] px31 hebi - addr[15]
89 32003e?avr32?05/06 at32ap7000 px32 hebi - addr[16] px33 hebi - addr[17] px34 hebi - addr[18] px35 hebi - addr[19] px36 hebi - addr[20] px37 hebi - addr[21] px38 hebi - addr[22] px39 hebi - ncs[0] px40 hebi - ncs[1] px41 hebi - ncs[3] px42 hebi - nrd[0] px43 hebi - nwe0[0] px44 hebi - nwe1[0] px45 hebi - nwe3[0] px46 hebi - sdck[0] px47 hebi - sdcke[0] px48 hebi - ras[0] px49 hebi - cas[0] px50 hebi - sdwe[0] px51 hebi - sda10[0] px52 hebi - nandoe[0] px53 hebi - nandwe[0] px46 hebi - sdck[0] table 10-14. io pins without multiplexing (continued)
90 32003e?avr32?05/06 at32ap7000 10.8 peripheral overview 10.8.1 external bus interface ? optimized for application memory space support ? integrates three external memory controllers: ? static memory controller ? sdram controller ? ecc controller ? additional logic for nand flash/smartmedia tm and compactflash tm support ? smartmedia support: 8-bit as well as 16-bit devices are supported ? compactflash support: all modes (attribute memory, common memory, i/o, true ide) are supported but the signal s _iois16 (i/o and true ide modes) and _ata sel (true ide mode) are not handled. ? optimized external bus: ? 16- or 32-bit data bus ? up to 26-bit address bus, up to 64-mbytes addressable ? optimized pin multiplexing to redu ce latencies on external memories ? up to 6 chip selects, configurable assignment: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs 3, optional nand flash/smartmedia tm support ? static memory controller on ncs 4 - ncs5, optional compactflash tm support 10.8.2 static memory controller ? 6 chip selects available ? 64-mbyte address space per chip select ? 8-, 16- or 32-bit data bus ? word, halfword, byte transfers ? byte write or by te select lines ? programmable setup, pulse and hold ti me for read signals per chip select ? programmable setup, pulse and hold time for write signals per chip select ? programmable data float time per chip select ? compliant with lcd module ? external wait request ? automatic switch to slow clock mode ? asynchronous read in page mode supporte d: page size ranges from 4 to 32 bytes 10.8.3 sdram controller ? numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path ? programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable
91 32003e?avr32?05/06 at32ap7000 ? energy-saving capabilities ? self-refresh, power-down and deep power modes supported ? supports mobile sdram devices ? error detection ? refresh error interrupt ? sdram power-up initialization by software ? cas latency of 1, 2, 3 supported ? auto precharge command not used 10.8.4 error corrected code controller ? hardware error corrected code (ecc) generation ? detection and correction by software ? supports nand flash and smartmedia ? devices with 8- or 16-bit data path. ? supports nand flash/smartmedia with page size s of 528, 1056, 2112 and 4224 bytes, specified by software 10.8.5 serial peripheral interface ? supports communication with serial external devices ? four chip selects with extern al decoder support allow co mmunication with up to 15 peripherals ? serial memories, such as da taflash? and 3-wire eeproms ? serial peripherals, such as adcs, dacs, l cd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable da ta length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfer s on the same device 10.8.6 two-wire interface ? compatibility with standard two-wire serial memory ? one, two or three bytes for slave address ? sequential read/write operations
92 32003e?avr32?05/06 at32ap7000 10.8.7 usart ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in a synchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? optional manchester encoding ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes 46 ? remote loopback, local loopback, automatic echo 10.8.8 serial synchronous controller ? provides serial synchronous communication links used in audio and tel ecom applications (with codecs in master or slave modes, i2s, tdm buses, magnetic card reader, etc.) ? contains an independent receiver and transmitter and a common clock divider ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to st art automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal, a cloc k signal and a frame synchronization signal 10.8.9 ac97 controller ? compatible with ac97 comp onent specification v2.2 ? capable to interface with a single analog front end ? three independent rx channels and three independent tx channels ? one rx and one tx channel dedicated to the ac97 analog front end control ? one rx and one tx channel for data transfers, asso ciated with a pdc ? one rx and one tx channel fo r data transfers with no pdc ? time slot assigner allowing to assign up to 12 time slots to a channel ? channels support mono or stereo up to 20 bit sample length - variable sampling rate ac97 codec interface (48khz and below) 10.8.10 audio dac ? tbd
93 32003e?avr32?05/06 at32ap7000 10.8.11 timer counter ? three 16-bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-conf igurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? two global registers that ac t on all three tc channels 10.8.12 pulse width modulation controller ? 4 channels, one 16-bit counter per channel ? common clock generator, providing thirteen different clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channel programming ? independent enable disable commands ? independent clock ? independent period and duty cycle, with double bufferization ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform 10.8.13 multimedia card interface ? 2 double-channel multimedia card interface, allowing concurrent transfers with 2 cards ? compatibility with multimedia card specification version 2.2 ? compatibility with sd memory card specification version 1.0 ? compatibility with sdio specification version v1.0. ? cards clock rate up to master clock divided by 2 ? embedded power management to slow down clock rate when not used ? each mci has two slot, each supporting ? one slot for one multimediacard bus (up to 30 cards) or ?one sd memory card ? support for stream, block and multi-block data read and write
94 32003e?avr32?05/06 at32ap7000 10.8.14 ps/2 keyboard interface ? system bus apb slave ? ps/2 host ? receive and transmit capability ? parity generation and error detection ? overrun error detection 10.8.15 usb device port ? usb v2.0 high-speed compli ant, 480 mbits per second ? embedded usb v2.0 high-speed transceiver ? embedded dual-port ram for endpoints ? suspend/resume logic ? ping-pong mode (two memory banks) for isochronous and bulk endpoints ? six general-purpose endpoints ? endpoint 0, endpoint 3: 8 bytes, no ping-pong mode ? endpoint 1, endpoint 2: 64 bytes, ping-pong mode ? endpoint 4, endpoint 5: 256 bytes, ping-pong mode 10.8.16 lcd controller ? single and dual scan color and monoch rome passive stn lcd panels supported ? single scan active tft lcd panels supported ? 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan stn interfaces supported ? up to 24-bit single scan tft interfaces supported ? up to 16 gray levels for mono stn and up to 4096 colors for color stn displays ? 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono stn ? 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color stn ? 1, 2, 4, 8 bits per pixel (palletized), 16 , 24 bits per pixel (non-palletized) for tft ? single clock domain architecture ? resolution supported up to 2048x2048 ? 2d-dma controller for manageme nt of virtual frame buffer ? allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer ? automatic resynchronization of the fram e buffer pointer to prevent flickering ? configurable coefficien ts with flexible fixe d-point representation.
95 32003e?avr32?05/06 at32ap7000 10.8.17 ethernet 10/100 mac ? compatibility with ieee standard 802.3 ? 10 and 100 mbits per second data throughput capability ? full- and half-duplex operations ? mii or rmii interface to the physical layer ? register interface to address, da ta, status and control registers ? dma interface, operating as a ma ster on the memory controller ? interrupt generation to signal receive and transmit completion ? 28-byte transmit and 28-byte receive fifos ? automatic pad and crc genera tion on transmitted frames ? address checking logic to recognize four 48-bit addresses ? support promiscuous mode where all valid frames are copied to memory ? support physical layer management through mdio interface control of alarm and update time/calendar data in 10.8.18 image sensor interface ? itu-r bt. 601/656 8-bit mode external interface support ? support for itu-r bt.656-4 sav and eav synchronization ? vertical and horizontal re solutions up to 2048 x 2048 ? preview path up to 640*480 ? support for packed data formatting for ycbcr 4:2:2 formats ? preview scaler to generate smaller size image 50 ? programmable frame capture rate
96 32003e?avr32?05/06 at32ap7000 11. power manager rev: 1.0.2 11.1 features ? controls oscillators and pll?s ? generates clocks and resets for digital logic ? supports 2 crystal oscillators 10 to 27 mhz ? supports 2 pll?s 80 to 133 mhz ? supports 32khz ultra-low power oscillator ? on-the fly frequency change of cpu, ahb, and apb frequency ? sleep modes allow simple disabling of logic clocks, pll?s and oscillators ? module-level clock gating through maskable peripheral clocks ? wake-up from interrupts or external pin ? generic clocks with wide frequency range provided ? automatic identificat ion of reset sources 11.2 description the power manager (pm) controls the oscillators, pll?s, and generates the clocks and resets in the device. the pm controls two fast crystal oscillators, as well as two pll?s, which can multiply the clock from either oscillato r to provide higher frequencies. additionally, a low-power 32khz oscillator is used to generate a slow clock for real-time counters. the provided clocks are divided into synchr onous and generic clocks. the synchronous clocks are used to clock the main digital logic in the device, namely the cpu, and the modules and peripherals connected to the ahb, apba, and apbb buses. the generic clocks are asynchro- nous clocks, which can be tuned precisely wit hin a wide frequency ra nge, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules. the pm also contains advanced power-saving feat ures, allowing the user to optimize the power consumption for an application. the synchronous cl ocks are divided into four clock domains, for the cpu, and modules on the ahb, apba, and apbb buses. the four clocks can run at different speeds, so the user can save power by running pe ripherals at a relatively low clock, while main- taining a high cpu performance. additionally, the clocks can be independently changed on-the fly, without halting any peripherals. this enables the user to adjust the speed of the cpu and memories to the dynamic load of the applicati on, without disturbing or re-configuring active peripherals. each module also has a separate clock, enabling t he user to switch off the clock for inactive modules, to save further power. additionally, clocks and oscillators can be automatically swith- ced off during idle periods by using the sleep instruction on the cpu. the system will return to normal on occurence of interrupts or an event on the wake_n pin. the power manager also cointains a reset contro ller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identifed by software.
97 32003e?avr32?05/06 at32ap7000 11.3 block diagram sleep controller oscillator and pll control pll0 pll1 synchronous clock generator generic clock generator reset controller oscillator 0 oscillator 1 32 khz oscillator startup counter slow clock sleep instruction oscen_n wake_n reset_n power-on detector soft reset sources resets generic clocks synchronou s clocks osc/pll control signals
98 32003e?avr32?05/06 at32ap7000 11.4 product dependencies 11.4.1 i/o lines the pm provides a number of generic clock out puts, which can be connected to output pins, multiplexed with pio lines. the programmer must first program the pio controller to assign these pins to their peripheral function. if the i/o pins of the pm are not used by the application, they can be used for other purposes by the pio controller. the pm also has a dedicated w ake_n pin, as well as a number of pins for oscillators and pll?s, which do not require the pio controller to be programmed. 11.4.2 interrupt the pm interrupt line is connected to one of the internal sources of the interrupt controller. using the pm interrupt requires the interrupt controller to be programmed first. 11.5 functional description 11.5.1 oscillator 0 and 1 operation the two main oscillators are designed to be used with an external 10 to 27 mhz crystal, as shown in figure 11-1 . the main oscillators are enabled by default after reset, and are only switched off in sleep modes, as described in section 11.5.6 on page 103 . after a power-on reset, or when waking up from a sleep mode that disabled the main oscillators, the oscillators need 128 slow clock cycles to stabilize on the correc t frequency. the pm masks the main oscil- lator outputs during this start-up period, to ensure that no unstable clocks propagate to the digital logic. the oscillators can be bypassed by pulling the os cen_n pin high. this disables the oscillators, and an external clock must be applied on xin. no start-up time applies to this clock. figure 11-1. oscillator connections 11.5.2 32 khz oscillator operation the 32 khz oscillator operates similarly to oscillator 0 and 1 described above, and is used to generate the slow clock in the device. a 32768 hz crystal must be connected between xin32 and xout32 as shown in figure 11-1 . the 32 khz oscillator is is an ultra-low power design, and remains enabled in all sleep modes except static mode, as described in section 11.5.6 on page 103 . the oscillator has a rather lo ng start-up time of 32768 cl ock cycles, and no clocks will be generated in the device during this start-up time. xin xout c 2 c 1
99 32003e?avr32?05/06 at32ap7000 pulling oscen_n low will also disable the 32 khz oscillator, and a 32 khz clock must be applied on the xin32 pin. no start-up time applies to this clock. 11.5.3 pll operation the device contains two pll?s, pll0 and pll1. these are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. the pll?s can take either oscillator 0 or 1 as clock source. each pll has an input divider, which divides the source clock, creating the reference clock for the pll. the pll output is divided by a user- defined factor, and the pll compares the resulting clock to the reference cl ock. the pll will adjust its output frequency until the two compar ed clocks are equal, thus locking the output fre- quency to a multiple of the reference clock frequency. when the pll is switched on, or when changing the clock source or multiplication or division factor for the pll, the pll is unlocked and the output frequency is undefined. the pll clock for the digital logic is automatically masked when th e pll is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable. figure 11-2. pll with control logic and filters pll output divider input divider lft 0 1 osc0 clock osc1 clock pllosc pllen pllopt pllmul plldiv lock suppression pllcount lock mask pll clock c 1 r 1 c 2
100 32003e?avr32?05/06 at32ap7000 11.5.3.1 enabling the pll plln is enabled by writing the pllen bit in the pm_plln regist er. pllosc selects oscillator 0 or 1 as clock source. the plldiv and pllmul bitfields must be written with the division and multiplication factor, respectively, creating the pll frequency: f pll = (pllmul+1)/(plldiv+1) ? f osc the lockn flag in pm_isr is set when plln becomes locked. the bit will stay high until cleared by writing 1 to pm_icr:lockn. the power manager interrupt can be triggered by writ- ing pm_ier:lockn to 1. 11.5.3.2 lock suppression when using high division or multiplication factors, there is a possibility that the pll can give false lock indications while sweeping to the corr ect frequency. to prevent false lock indications from setting the lockn flag, the lock indication can be suppressed for a number of slow clock cycles indicated in the pm_plln:count field. typical start-up times can be found using the atmel filter caluclator (see below). 11.5.3.3 operating range selection to use plln, a passive rc filter should be connected to the lftn pin, as shown in figure 11-2 . filter values depend on the pll reference and output frequency range. atmel provides a tool named ?atmel pll lft filter calculator at91? available for download at the atmel web site. the pll for at32ap7000 can be selected in this tool by selecting ?at91rm9200 (58a07f)? and leave ?icp = ?1?? (default). similarly, the pm_plln:pllopt field should be set to proper values according to the pll oper- ating frequency, as described in section 11.6.4 on page 112 . 11.5.4 synchronous clocks oscillator 0 (default) or pll0 prov ides the source for the main cl ocks, which is the common root for the synchronous clocks for the cpu, and ahb, apba, and apbb module s. the main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tap- ping of this prescaler, or the undivided main clock, as long as f cpu f ahb f apba, . the synchronous clock source can be changed on-the fly, responding to varying load in the applica- tion. the clock domains can be shut down in sleep mode, as described in ?sleep modes? on page 103 . additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules.
101 32003e?avr32?05/06 at32ap7000 figure 11-3. synchronous clock generation 11.5.4.1 selecting pll or os cillator for the main clock the common main clock can be c onnected to oscillator 0 or pll0 . by default, the main clock will be connected to the osc illator 0 output. the user can connec t the main clock to the pll0 output by writing the pllsel bit in th e main clock control register (p m_mcctrl) to 1. this must only be done after pll0 has been enabled, otherwise a deadlock will occur. care should also be taken that the new frequency of the synchr onous clocks does not ex ceed the maximum fre- quency for each clock domain. 11.5.4.2 selecting synchronous clock division ratio the main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. by default, the synchronous clocks run on the undivided main clock. the user can select a pres- caler division for the cpu clock by writin g pm_cksel:cpudiv to 1 and cpusel to the prescaling value, resulting in a cpu clock frequency: f cpu = f main / 2 (cpusel+1) similarly, the clock for ahb, apb a, and apbb can be divided by writ ing their respective bitfields. to ensure correct operation, frequencies must be selected so that f cpu f ahb f apba,b . also, fre- quencies must never exceed the specified maximum frequency for each clock domain. pm_cksel can be written without halting or disabling peripheral modules. writing pm_cksel allows a new clock setting to be written to all synchronous clocks at the same time. it is possible to keep one or more clocks unch anged by writing the same val ue a before to the xxxdiv and xxxsel bitfields. this way, it is possible to e.g. scale cpu and ahb speed according to the required performance, while keeping the apba and apbb frequency constant. mask prescaler 0 1 osc0 clock pll0 clock pllsel 0 1 cpusel cpudiv main clock sleep controller cpumask cpu clocks ahb clocks apbaclocks apbb clocks sleep instruction
102 32003e?avr32?05/06 at32ap7000 11.5.4.3 clock ready flag there is a slight delay from pm_cksel is written and the new clock setting becomes effective. during this interval, the clock r eady (ckrdy) flag in pm_isr will read as 0. if pm_ier:ckrdy is written to 1, the power manager interrupt can be triggered when the new clock setting is effec- tive. pm_cksel must not be re-written while ckrd y is 0, or the system may become unstable or hang. 11.5.5 peripheral clock masking by default, the clock for all modules are enabled, regardless of which modules are actually being used. it is possible to disable the clock for a module in the cpu, ahb, apba, or apbb clock domain by writing th e corresponding bit in the clock ma sk register (pm_cpu/ahb/apba/apbb) to 0. when a module is not clocked, it will cease operation, and its registers cannot be read or written. the module can be re-enabled later by writing the corresponding mask bit to 1. a module may be connected to several clock domains, in which case it will have several mask bits. table 11-1 contains a list of impl emented maskable clocks. 11.5.5.1 cautionary note note that clocks should only be switched off if it is certain that the module will not be used. switching off the clock for the internal ram will cause a pr oblem if the stack is mapped there. switching off the clock to the system manager (sm), which contains the mask registers, or the corresponding apb bridge, will make it impossible to write the mask registers again. in this case, they can only be re-enabled by a system reset. 11.5.5.2 mask ready flag due to synchronization in the clock generator, there is a slight delay from a mask register is writ- ten until the new mask setting goes into effect. when clearing mask bits, this delay can usually be ignored. however, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. the status flag mskrdy in pm_isr provides the required mask status information. when writing either mask register with any value, this bit is cleared. the bit is set when the clocks have been enabled and disabled according to the new mask setting. optionally, the power ma nager interrupt can be enabled by writing the mskrdy bit in pm_ier.
103 32003e?avr32?05/06 at32ap7000 11.5.6 sleep modes in normal operation, all clock domains are active, allowing software execution and peripheral operation. when the cpu is idle, it is possible to switch off the cpu clock and optionally other clock domains to save power. this is activate d by the sleep instruction, which takes the sleep mode index number as argument. 11.5.6.1 entering and exiting sleep modes the sleep instruction will halt the cpu and all modules belonging to t he stopped clock domains. the modules will be halted regardless of th e bit settings of the mask registers. oscillators and pll?s can also be switched off to save power. these modules have a relatively long start-up time, and are only switched off when very low power consumption is required. the cpu and affected modules are restarted when the sleep mode is exited. this occurs when an interrupt trigge rs, or the wake_n pin is asserted. no te that even though an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked. table 11-1. maskable module cl ocks in at32ap7000. bit cpumask ahbmask apbamask apbbmask 0 pico ebi spi0 sm 1 - apba spi1 intc 2 - apbb twi hmatrix 3 - hramc usart0 tc0 4 - ahb-ahb bridge usart1 tc1 5 - isi usart2 pwm 6 - usb usart3 macb0 7 - lcdc ssc0 macb1 8 - macb0 ssc1 dac 9 - macb1 ssc2 mci 10 - dma pioa ac97c 11 - - piob isi 12 - - pioc usb 13 - - piod smc 14 - - pioe sdramc 15 - - piof ecc 16 - - pdc - 31: 17 ----
104 32003e?avr32?05/06 at32ap7000 11.5.6.2 supported sleep modes the following sleep modes are supported. these are detailed in table 11-2 . ?idle: the cpu is stopped, the rest of the chip is operating. wake-up sources are any interrupt, or wake_n pin. ?frozen: the cpu and ahb modules are stopped, peripherals are operating. wake-up sources are any interr upt from apb modules, or wake_n pin. ?standby: all synchronous clocks are stopped, but oscillators and pll?s are running, allowing quick wake-up to normal mode. wake-up sources are rtc or external interrupt, or wake_n pin. ?stop: as standby, but oscilla tor 0 and 1, and the pll?s are stopped. 32 khz oscillator and rtc/wdt still operates. wake-up sources are rtc or external inte rrupt, or wake_n pin. ?static: all oscillators and clocks are stoppe d. wake-up sources are external interrupt or wake_n pin.? 11.5.6.3 precautions when entering sleep mode modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the mo dule operation. this prevents erra tic behavior when entering or exiting sleep mode. please refer to the re levant module documentation for recommended actions. communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. this means that bus transactions are not allowed between clock domains affected by the sleep mode. the system may hang if th e bus clocks are stopped in the middle of a bus transaction. the cpu and caches are automatically stopped in a safe state to ensure that all cpu bus oper- ations are complete when the sleep mode goes into effect. thus, when entering idle mode, no further action is necessary. when entering a deeper sleep mode than idle mode, all other ahb masters must be stopped before entering the sleep mode. also, if there is a chance that any apb write operations are incomplete, the cpu should perform a read operation from any register on the apb bus before executing the sleep instruction. this will stall the cpu while wa iting for any pending apb opera- tions to complete. table 11-2. sleep modes index sleep mode cpu ahb apba,b + gclk osc0,1 + pll0,1 osc32 + rtc/wdt 0 idle off on on on on 1frozenoffoffononon 2 standby off off off on on 3 stop off off off off on 5 static off off off off off
105 32003e?avr32?05/06 at32ap7000 11.5.7 generic clocks timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly . the power manager contains an implementation defined number of generic clocks, that can prov ide a wide range of accurate clock frequencies. each generic clock module runs from either oscilla tor 0 or 1, or pll0 or 1. the selected source can optionally be divided by any even integer up to 512. each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the sleep controller. figure 11-4. generic clock generation 11.5.7.1 enabling a generic clock a generic clock is enabled by writing the cen bit in pm_gcctrl to 1. each generic clock can use either oscillator 0 or 1 or pll0 or 1 as source, as sele cted by the pllsel and oscsel bits. the source clock can optionally be divided by writing diven to 1 and the division factor to div, resulting in the output frequency: f gclk = f src / (2*(div+1)) 11.5.7.2 disabling a generic clock the generic clock can be disabled by writing cen to 0 or entering a sleep mode that disables the apb clocks. in either case, the ge neric clock will be switched o ff on the first falling edge after the disabling event, to ensu re that no glitches occur. if cen is written to 0, the bit will still read as 1 until the next falling edge occu rs, and the clock is actually sw itched off. when writing cen to 0, the other bits in pm_gcctrl should not be chang ed until cen reads as 0, to avoid glitches on the generic clock. when the clock is disabled, both the prescaler and output are reset. divider 0 1 osc0 clock pll0 clock pllsel oscsel osc1 clock pll1 clock generic clock div 0 1 diven mask cen sleep controller
106 32003e?avr32?05/06 at32ap7000 11.5.7.3 changing clock frequency when changing generic clock frequency by writ ing pm_gcctrl, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division set- ting. this prevents glitches during the transition. 11.5.7.4 generic clock implementation in at32ap7000, there are 8 generic clocks. these are allocated to different functions as shown in table 11-3 . 11.5.8 divided apb clocks the clock generator in the power manager pr ovides divided apba and apbb clocks for use by peripherals that require a prescaled apb clock. this is described in the documentation for the relevant modules. the divided clocks are not directly maskable , but are stopped in sleep modes where the apb clocks are stopped. 11.5.9 debug operation during a debug session, the user may need to halt the system to inspect memory and cpu reg- isters. the clocks normally keep running during this debug opera tion, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. for this reason, peripherals on t he apba and apbb buses may use ?debug qualified? apb clocks. this is described in the documentat ion for the relevant modules. the divided apb clocks are always debug qualified clocks. debug qualified apb clocks ar e stopped during debug operation. th e debug system can option- ally keep these clocks running during the debug operation. this is described in the documentation for the on-chip debug system. table 11-3. generic clock allocation clock number function 0gclk0 pin 1gclk1 pin 2gclk2 pin 3gclk3 pin 4gclk4 pin 5 reserved for internal use 6dac 7 lcd controller
107 32003e?avr32?05/06 at32ap7000 11.5.10 reset controller the reset controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. the device contains a power-on detector, which keeps the system reset until power is stable. this eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. it is also possible to reset the device by asserting the reset_n pin. this pin has an internal pul- lup, and does not need to be driven externally when negated. table 11-4 lists these and other reset sources supported by the reset controller. figure 11-5. reset controller block diagram reset sources are divided into hard and soft resets. hard resets imply that the system could have become unstable, and virtually all logic will be reset. t he clock generator, which also con- trols the oscillators, will also be reset. if the device is reset due to a power-on reset, or reset occurred when the device was in a sleep mode that disabled the oscillators , the normal oscillator startup time will apply. a soft reset will reset most digital logic in the device, such as cp u, ahb, and apb modules, but not the ocd system, clock generator, watchdog timer and rtc, allowing some functions, including the oscillators, to remain active during the reset. the startup time from a soft reset is thus negligible. note that all apb registers are reset, except those in the rtc/wdt. the pm_mcctrl and pm_cksel register s are reset, and the device will restart using oscillator 0 as clock source for all synchronous clocks. in addition to the listed reset types, the jtag can keep parts of the device statically reset through the jtag reset register. see jtag documentation for details. ntae reset controller reset_n power-on detector dbr watchdog reset rc_rcause hard reset soft reset cpu, ahb, apba, apbb ocd, rtc/wdt, clock generator
108 32003e?avr32?05/06 at32ap7000 the cause of the last reset can be read from the rc_rcause register. this register contains one bit for each reset source, and can be identified during the boot sequence of an application to determine the proper action to be taken. table 11-4. reset types reset source description type power-on reset supply voltage below the power-on reset detector threshold voltage hard external reset_n pin asserted hard nanotrace access error see on-chip debug documentation. soft watchdog timer see watchdog timer documentation. soft ocd see on-chip debug documentation soft
109 32003e?avr32?05/06 at32ap7000 11.6 user interface 11.6.1 main clock control name: pm_mcctrl access type: read/write ? pllsel: pll select 0: oscillator 0 is source for the main clock 1: pll0 is source for the main clock offset register register name access reset 0x00 main clock control pm_mcctrl read/write 0x0 0x04 clock select pm_cksel read/write 0x0 0x08 cpu clock mask pm_cpumask read/write impl. defined 0x0c ahb clock mask pm_ahbmask read/write impl. defined 0x10 apba clock mask pm_apbamask read/write impl. defined 0x14 apbb clock mask pm_apbbmask read/write impl. defined 0x20 pll0 control pm_pll0 read/write 0x0 0x24 pll1 control pm_pll1 read/write 0x0 0x40 interrupt enable pm_ier write-only 0x0 0x44 interrupt disable pm_idr write-only 0x0 0x48 interrupt mask pm_imr read-only 0x0 0x4c interrupt status pm_isr read-only 0x0 0x50 interrupt clear pm_icr write-only 0x0 0x60 generic clock control pm_gcctrl read/write 0x0 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ------pllsel-
110 32003e?avr32?05/06 at32ap7000 11.6.2 clock select name: pm_cksel access type: read/write ? apbbdiv, apbbsel: apbb division and clock select apbbdiv = 0: apbb clock equals main clock. apbbdiv = 1: apbb clock equals main clock divided by 2 (apbbsel+1) . ? apbadiv, apbasel: apba division and clock select apbadiv = 0: apba clock equals main clock. apbadiv = 1: apba clock equals main clock divided by 2 (apbasel+1) . ? ahbdiv, ahbsel: ahb division and clock select ahbdiv = 0: ahb clock equals main clock. ahbdiv = 1: ahb clock equals main clock divided by 2 (ahbsel+1) . ? cpudiv, cpusel: cpu divi sion and clock select cpudiv = 0: cpu clock equals main clock. cpudiv = 1: cpuclock equals main clock divided by 2 (cpusel+1) . note that if xxxdiv is written to 0, xxxsel should also be written to 0 to ensure correct operation. also note that writing this register clears pm_isr:ckrdy. the register must not be re-written until ckrdy goes high. 31 30 29 28 27 26 25 24 apbbdiv - - - - apbbsel 23 22 21 20 19 18 17 16 apbbdiv - - - - apbbsel 15 14 13 12 11 10 9 8 ahbdiv - - - - ahbsel 76543210 cpudiv - - - - cpusel
111 32003e?avr32?05/06 at32ap7000 11.6.3 clock mask name: pm_cpu/ahb/apba/apbbmask access type: read/write ? mask: clock mask if bit n is cleared, the clock for module n is stopped. if bit n is set, the clock for module n is enabled according to the cur rent power mode. the number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is implementation dependent. 31 30 29 28 27 26 25 24 mask[31:24] 23 22 21 20 19 18 17 16 mask[23:16] 15 14 13 12 11 10 9 8 mask[15:8] 76543210 mask[7:0]
112 32003e?avr32?05/06 at32ap7000 11.6.4 pll control name: pm_pll0,1 access type: read/write ? plltest: pll test reserved for internal use. always write to 0. ? pllcount: pll count specifies the number of slow clock cycles before pm_isr:lockn will be set after pm_pl ln has been wr itten, or after plln has been automatically re-enabled after exiting a sleep mode. ? pllmul: pll multiply factor ? plldiv: pll division factor these bitfields determine the ratio of the pll out put frequency to the source oscillator frequency: f pll = (pllmul+1)/(plldiv+1) ? f osc ? pllopt: pll option select the operating range for the pll. note: operation beyond the speed indicated in ?electrical characteristics - tbd? is not implied. 100: 80-160 mhz 110: 150-200mhz other values: reserved ? pllosc: pll os cillator select 0: oscillator 0 is t he source for the pll. 1: oscillator 1 is t he source for the pll. ? pllopt: pll option 0: pll is disabled. 1: pll is enabled. 31 30 29 28 27 26 25 24 plltest - pllcount 23 22 21 20 19 18 17 16 pllmul 15 14 13 12 11 10 9 8 plldiv 76543210 - - - pllopt pllosc pllen
113 32003e?avr32?05/06 at32ap7000 11.6.5 interrupt enable/disable/mask/status/clear name: pm_ier/idr/imr/isr/icr access type: pm_ier/idr/icr: write-only pm_imr/isr: read-only ? mskrdy: mask ready 0: either pm_xxxmask register has been written, and clocks are not yet enabled or disabled according to the new mask value. 1: clocks are enabled and disabled as indicated in the pm_xxxmask registers. note: writing pm_icr:mskrdy to 1 has no effect. ? ckrdy: clock ready 0: the pm_cksel register has been written, and the new clock setting is not yet effective. 1: the synchronous clocks have frequencies as indicated in the pm_cksel register. note: writing pm_icr:ckrdy to 1 has no effect. ? vmrdy, vok these bits are for internal use only. in pm_isr, the value of t hese bits is undefined. in pm_ier, these bits should be written to 0. ? wake: wake pin asserted 0: the wake_n pin is not asserted, or has been asserted for less than one apb clock period. 1: the wake_n pin is asserted for longer than one apb clock period. ? lock1: pll1 locked ? lock0: pll0 locked 0: the pll is unlocked, and cannot be used as clock source. 1: the pll is locked, and can be used as clock source. the effect of writing or reading the bits listed above depends on which register is being accessed: ? ier (write-only) 0: no effect 1: enable interrupt ? idr (write-only) 0: no effect 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - mskrdy ckrdy vmrdy vok wake lock1 lock0
114 32003e?avr32?05/06 at32ap7000 1: disable interrupt ? imr (read-only) 0: interrupt is disabled 1: interrupt is enabled ? isr (read-only) 0: an interrupt event has occurred 1: an interrupt even has not occurred ? icr (write-only) 0: no effect 1: clear interrupt event
115 32003e?avr32?05/06 at32ap7000 11.6.6 generic clock control name: pm_gcctrl access type: read/write there is one pm_gcctrl register per generic clock in the design. ? div: division factor ? diven: divide enable 0: the generic clock equals the undivided source clock. 1: the generic clock equals the source clock divided by 2*(div+1). ? cen: clock enable 0: clock is stopped. 1: clock is running. ? pllsel: pll select 0: oscillator is source for the generic clock. 1: pll is source for the generic clock. ? oscsel: oscillator select 0: oscillator (or pll) 0 is source for the generic clock. 1: oscillator (or pll) 1is source for the generic clock. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 div[7:0] 76543210 - - - diven - cen pllsel oscsel
116 32003e?avr32?05/06 at32ap7000 11.6.7 reset cause name: rc_rcause access type: read-only ? ntae: nanotrace access error this bit is set if a reset occurred due to a nanotrace access error. ? wdt: watchdog timer this bit is set if a reset occurred due to a timeout of the watchdog timer. ? ext: external reset this bit is set if a reset occurred due to assertion of the reset_n pin. ? por: power-on detector this bit is set if a reset was caused by the power-on detector. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - ntae wdt ext - por
117 32003e?avr32?05/06 at32ap7000 12. real time counter rev: 1.0.1 12.1 features ? 32-bit real-time counte r with 16-bit prescaler ? clocked from 32 khz oscillator ? high resoluti on: max count frequency 16khz ? long delays ? max timeout 272 years ? extremely low power consumption ? available in all sleep modes except deepdown ? optional wrap at max value ? interrupt on wrap ? watchdog timer support 12.2 description the real time counter (rtc) enables periodic in terrupts at long intervals, or accurate mea- surement of real-time sequences. the rtc is fed from a 16-bit prescaler, which is clocked from the 32 khz oscillator. any tapping of the prescaler can be select ed as clock source for the rtc, enabling both high resolution and long timeouts. the prescaler cannot be written directly, but can be cleared by the user. the rtc can generate an interrupt when the counter wraps around the top value of 0xffffffff. optionally, the rtc can wrap at a lower value, producing accurate periodic interrupts. the rtc prescaler also feeds an independent watchdog timer (wdt), which uses any tapping of the prescaler as timeout period. the watc hdog timer must be periodically reset by software within the timeout period, otherwise, the device is reset and starts executing from the boot vec- tor. this allows the device to recover from a condition that has caused the system to be unstable.
118 32003e?avr32?05/06 at32ap7000 12.3 block diagram figure 12-1. real time counter module block diagram 16-bit prescaler 32 khz 32-bit counter wdt_clr rtc_val rtc_top topi irq watchdog detector wdt_ctrl watchdog reset
119 32003e?avr32?05/06 at32ap7000 12.4 product dependencies 12.4.1 i/o lines the rtc can optionally be connected to an output pin, multiplexed with pio lines. the program- mer must first program the pio controller to assi gn the rtc pin to its peripheral function. if the i/o pin of the rtc is not used by the application, it can be used for other purposes by the pio controller. 12.4.2 power management the rtc is continously clocked, and remains operating in all sleep modes except deepdown. 12.4.3 interrupt the rtc interrupt line is connected to one of the internal sources of the interrupt controller. using the rtc interrupt requires the interrupt controller to be programmed first. 12.4.4 debug operation the rtc prescaler and watchdog timer are frozen during debug operation, unless the ocd sys- tem keeps peripherals running in debug operation.
120 32003e?avr32?05/06 at32ap7000 12.5 functional description 12.5.1 rtc operation 12.5.1.1 source clock the rtc is enabled by writing th e en bit in the rtc_ctrl register. this also enables the clock for the prescaler. the psel bitfield in the same register selects the prescaler tapping, selecting the source clock for the rtc: f rtc = 2 -(psel+1) * 32khz 12.5.1.2 counter operation the rtc count value can be read from or written to the register rtc_val. the prescaler can- not be written directly, but can be reset by writing the strobe pclr in rtc_ctrl. when enabled, the rtc will then up -count until it reac hes 0xffffffff, and then wrap to 0x0. writing rtc_ctrl:topen to one causes the rtc to wrap at the value written to rtc_top. the status bit topi in rtc_isr is set when this occurs. 12.5.1.3 rtc interrupt writing the topi bit in rtc_ier enables the rtc in terrupt, while writing the corresponding bit in rtc_idr disables the rtc interrupt. rtc_imr can be read to see whether or not the interrupt is enabled. if enabled, an interrupt will be generated if the to pi flag in rtc_isr is set. the flag can be cleared by writing topi in rtc_icr to one. 12.5.2 watchdog timer the wdt is enabled by writing the en bit in the wdt_ctrl register. this also enables the clock for the prescaler. the prescaler is the same as for the rtc. the psel bitfield in the same register selects the watchdog timeout period: t wdt = 2 (psel+1) * 30.518 s to avoid accidental disabling of the watchdog, the wdt_ctrl register must be written twice, first with the key field set to 0x 55, then 0xaa without ch anging the other bitfie lds. failure to do so will cause the write operation to be ignor ed, and wdt_ctrl does not change value. the wdt_clr register must be written with any value with regu lar intervals shorter than the watchdog timeout period. otherwise, the device will receive a soft reset, and the code will start executing from the boot vector.
121 32003e?avr32?05/06 at32ap7000 12.6 user interface offset register register name access reset 0x00 rtc control rtc_ctrl read/write 0x0 0x04 rtc value rtc_val read/write 0x0 0x08 rtc top rtc_top read/write 0x0 0x10 rtc interrupt enable rtc_ier write-only 0x0 0x14 rtc interrupt disable rtc_idr write-only 0x0 0x18 rtc interrupt mask rtc_imr read-only 0x0 0x1c rtc interrupt status rtc_isr read-only 0x0 0x20 rtc interrupt clear rtc_icr write-only 0x0 0x30 wdt control wdt_ctrl read/write 0x0 0x34 wdt clear wdt_clr write-only 0x0
122 32003e?avr32?05/06 at32ap7000 12.6.1 rtc control name: rtc_ctrl access type: read/write ? psel: prescale select selects prescaler bit psel as source clock for the rtc. ? topen: top enable 0: rtc wraps at 0xffffffff 1: rtc wraps at rtc_top ? pclr: prescaler clear writing this strobe clears the prescaler. note that this also resets the watchdog timer. ? en: enable 0: rtc is disabled 1: rtc is enabled 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - psel[3:0] 76543210 - - - - - topen pclr en
123 32003e?avr32?05/06 at32ap7000 12.6.2 rtc value name: rtc_val access type: read/write ? val: rtc value this value is incremented on every rising edge of the source clock. 31 30 29 28 27 26 25 24 val[31:24] 23 22 21 20 19 18 17 16 val[23:16] 15 14 13 12 11 10 9 8 val[15:8] 76543210 val[7:0]
124 32003e?avr32?05/06 at32ap7000 12.6.3 rtc top name: rtc_top access type: read/write ? top: rtc top value rtc_val wraps at this value if rtc_ctrl:topen is 1. 31 30 29 28 27 26 25 24 top[31:24] 23 22 21 20 19 18 17 16 top[23:16] 15 14 13 12 11 10 9 8 top[15:8] 76543210 top[7:0]
125 32003e?avr32?05/06 at32ap7000 12.6.4 rtc interrupt enable/disable/mask/status/clear name: rtc_ier/idr/imr/isr/icr access type: rtc_ier/idr/icr: write-only rtc_imr/isr: read-only ? topi: top interrupt rtc_val has wrapped at its rtc_top. the effect of writing or reading this bit depends on which register is being accessed: ? ier (write-only) 0: no effect 1: enable interrupt ? idr (write-only) 0: no effect 1: disable interrupt ? imr (read-only) 0: interrupt is disabled 1: interrupt is enabled ? isr (read-only) 0: an interrupt event has not occurred 1: an interrupt event has occurred. note that this is only set when the rtc is configured to wrap at rtc_top. ? icr (write-only) 0: no effect 1: clear interrupt event 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------topi
126 32003e?avr32?05/06 at32ap7000 12.6.5 wdt control name: wdt_ctrl access type: read/write ? key this bitfield must be written twice, first with key value 0x55, then 0xaa, for a write operation to be effective. this bitfield always reads as zero. ? psel: prescale select prescaler bit psel is used as watchdog ti meout period. ? en: wdt enable 0: wdt is disabled. 1: wdt is enabled. 31 30 29 28 27 26 25 24 key[7:0] 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - - psel[3:0] 76543210 -------en
127 32003e?avr32?05/06 at32ap7000 12.6.6 wdt clear name: wdt_clr access type: write-only when the watchdog timer is enabled, this register must be periodically written, with any value, within the watchdog timeout period, to prevent a watchdog reset.
128 32003e?avr32?05/06 at32ap7000 13. interrupt controller rev: 1.0.0 13.1 description the intc collects interrupt requests from the peripherals, prioritizes them, and delivers an inter- rupt request and an autovector to the cpu. the avr32 architecture supports 4 priority levels for regular, maskable interrupts, and a non-maskable interrupt (nmi). the intc supports up to 64 groups of interrupts. each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. each group has an interrupt priority register (ipr) and an interrupt request register (irr). the iprs are used to assign a priority level and an autovector to each group, and the irrs are used to identify the active interrupt request within each group. if a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding irr is not needed. the intc also provides one interrupt cause register (icr) per priority level. these registers identify the group that has a pending interrupt of the corresponding priority level. if several groups have an pending interrupt of the same level, the group with the highest number takes priority. 13.2 block diagram figure 13-1 on page 128 gives an overview of the intc. the grey boxes represent registers that can be accessed via the apb bus. the interrupt requests from the peripherals (ireqn) and the nmi are input on the left side of the figure. signals to and from the cpu are on the right side of the figure. figure 13-1. overview of the interrupt controller request masking or ireq0 ireq1 ireq2 ireq31 grpreq0 masks sreg masks i[3-0]m gm intlevel autovector prioritizer cpu interrupt controller or grpreqn nmireq or ireq32 ireq33 ireq34 ireq63 grpreq1 irr registers ipr registers icr registers int_level, offset int_level, offset int_level, offset ipr0 ipr1 iprn irr0 irr1 irrn valreq0 valreq1 valreqn
129 32003e?avr32?05/06 at32ap7000 13.3 operation all of the incoming interrupt requests (ireqs) are sampled into the corresponding interrupt request register (irr). the irrs must be accessed to identify which ireq within a group that is active. if several ireqs within the same group is active, the interrupt service routine must pri- oritize between them. all of the input lines in each group are logically-ored together to form the grpreqn lines, indicating if there is a pending interrupt in the corresponding group. the request masking hardware maps each of the grpreq lines to a priority level from int0 to int3 by associating each group with the intlevel field in the corresponding ipr register. the grpreq inputs are then masked by the i0m, i1m, i2m, i3m and gm mask bits from the cpu sta- tus register. any interrupt group that has a pending interrupt of a priority level that is not masked by the cpu status register, gets its corresponding valreq line asserted. the prioritizer hardware uses th e valreq lines and the intlevel fi eld in the iprs to select the pending interrupt of the highest priority. if a nmi interrupt is pending, it automatically gets high- est priority of any pending interrupt. if several interrupt groups of the highest pending interrupt level have pending interrupts, the interrupt group with the highest number is selected. interrupt level (intlevel) and han dler autovector offset (autovec tor) of the selected inter- rupt are transmitted to the cpu for interrupt handling and context switching. the cpu doesn't need to know which interrupt is requesting handling, but only the level and the offset of the han- dler address. the irr registers contain the interr upt request lines of the groups and can be read via apb for checking which interrupts of the group are actually active. masking of the interrupt requests is done based on five interrupt mask bits of the cpu status register, namely interrupt level 3 mask (i3m) to interrupt level 0 mask (i0m), and global interrupt mask (gm). an interrupt request is masked if either the global interrupt mask or the correspond- ing interrupt level mask bit is set. 13.3.1 non maskable interrupts a nmi request has priority over all other interrupt requests. nmi has a dedicated exception vec- tor address defined by the avr32 archit ecture, so autovector is undefined when intlevel indicates that an nmi is pending. 13.3.2 cpu response when the cpu receives an interr upt request it checks if any othe r exceptions are pending. if no exceptions of higher priority are pending, interr upt handling is initiated. when initiating interrupt handling, the corresponding interrupt mask bit is se t automatically for this and lower levels in sta- tus register. e.g, if interrupt on level 3 is approved for handling the interrupt mask bits i3m, i2m, i1m, and i0m are set in status register. if interrupt on level 1 is approved the masking bits i1m, and i0m are set in status register. the handler offset is calculated from autovector and evba and a change-of-fl ow to this address is performed. setting of the interrupt mask bits prevents the interrupts from the same and lower levels to be passed trough the interrupt controller. setting of the same level mask bit prevents also multiple request of the same interrupt to happen. it is the responsibility of the ha ndler software to clear the interrupt request that caused the inter- rupt before returning from the interrupt handler. if the conditions that caused the interrupt are not cleared, the interrupt request remains active.
130 32003e?avr32?05/06 at32ap7000 13.3.3 clearing an interrupt request clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding nmireq/ireq signal. the recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operat ion from the same register. this causes a pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.
131 32003e?avr32?05/06 at32ap7000 13.4 user interface this chapter lists the in tc registers are accessible throu gh the apb bus. the registers are used to control the behaviour and read the status of the intc. 13.4.1 memory map the following table shows the address map of the intc registers, relative to the base address of the intc. 13.4.2 interrupt request map the mapping of interrupt requests from peripher als to intreqs is presented in the peripherals section. table 13-1. intc address map offset register name access reset value 0 interrupt priority regist er 0 ipr0 read/write 0x0000_0000 4 interrupt priority regist er 1 ipr1 read/write 0x0000_0000 ... ... ... ... ... 252 interrupt priority regist er 63 ipr63 read/write 0x0000_0000 256 interrupt request register 0 irr0 read-only n/a 260 interrupt request register 1 irr1 read-only n/a ... ... ... ... ... 508 interrupt request register 63 irr63 read-only n/a 512 interrupt cause register 0 icr3 read-only n/a 516 interrupt cause register 1 icr2 read-only n/a 520 interrupt cause register 2 icr1 read-only n/a 524 interrupt cause register 3 icr0 read-only n/a
132 32003e?avr32?05/06 at32ap7000 13.4.3 interrupt request registers register name : irr0...irr63 access type: read-only ? irr: interrupt request line 0 = no interrupt request is pending on this input request input. 1 = an interrupt request is pending on this input request input. the are 64 irrs, one for each group. each irr has 32 bits, one for each possible interrupt request, for a total of 2048 pos- sible input lines. the irrs are read by the software interrupt handler in order to determine which interrupt request is pending. the irrs are sampled continuously, and are read-only. 31 30 29 28 27 26 25 24 irr(32*x+31) irr(32*x+30) irr(32*x+29) irr(32*x+28) ir r(32*x+27) irr(32*x+26) irr(32*x+25) irr(32*x+24) 23 22 21 20 19 18 17 16 irr(32*x+23) irr(32*x+22) irr(32*x+21) irr(32*x+20) ir r(32*x+19) irr(32*x+18) irr(32*x+17) irr(32*x+16) 15 14 13 12 11 10 9 8 irr(32*x+15) irr(32*x+14) irr(32*x+13) irr(32*x+12) ir r(32*x+11) irr(32*x+10) irr(32*x+9) irr(32*x+8) 76543210 irr(32*x+7) irr(32*x+6) irr(32*x+5) irr(32*x+4) i rr(32*x+3) irr(32*x+2) irr(32*x+1) irr(32*x+0)
133 32003e?avr32?05/06 at32ap7000 13.4.4 interrupt priority registers register name : ipr0...ipr63 access type: read/write ? intlevel: interrupt level associated with this group indicates the evba-relative offs et of the interrupt handler of the corresponding group: ? autovector: autovector address for this group handler offset is used to give the address of the interrupt handler. the lsb should be written to zero to give halfword alignment 31 30 29 28 27 26 25 24 intlevel[1:0] ------ 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - autovector[13:8] 76543210 autovector[7:0] intlevel[1:0] priority 00int0 01int1 10int2 11int3
134 32003e?avr32?05/06 at32ap7000 13.4.5 interrupt cause registers register name : icr0...icr3 access type: read-only ? cause: interrupt group causing interrupt of priority n icrn identifies the group with the highest priority that has a pending interrupt of level n. if no interrupts of level n are pe nd- ing, or the priority level is mask ed, the value of icrn is undefined. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -- cause
135 32003e?avr32?05/06 at32ap7000 14. external interrupts rev: 1.0.0 14.1 features ? dedicated interrupt requ ests for each interrupt ? individually maskable interrupts ? interrupt on rising or falling edge ? interrupt on high or low level ? maskable nmi interrupt 14.2 description the external interrupt module allows 4 pins to be configured as external interrupts. each pin has its own interrupt request, and can be individually masked. each pin can generate an interrupt on rising or falling edge, or high or low level. the module also masks the nmi_n pin, which generates the nmi interrupt for the cpu. 14.3 block diagram figure 14-1. external interrupt module block diagram sync edge/level detector mask irqn extintn intn eim_level eim_mode eim_ier eim_idr eim_icr eim_isr eim_imr nmi_n sync mask nmi_irq eim_nmic
136 32003e?avr32?05/06 at32ap7000 14.4 product dependencies 14.4.1 i/o lines the external interrupt and nmi pins are multiplexed with pio lines. to act as external interrupts, these pins must be configured as inputs pins by th e pio controller. it is also possible to trigger the interrupt by driving these pins from registers in the pio controller, or another peripheral out- put connected to the same pin. 14.4.2 power management edge triggered interrupts are available in al l sleep modes except deepdown. level triggered interrupts and the nmi interrupt are available in all sleep modes. 14.4.3 interrupt the eim interrupt lines are connected to internal sources of the interrupt controller. using the external interrutps requires the interrupt controller to be programmed first. using the non-maskable interrupt does not require the interrupt controller to be programmed. 14.5 functional description 14.5.1 external interrupts each external interrupt pin extintn can be configured to produce an interrupt on rising or fall- ing edge, or high or low level. external interrupts are configured by the eim_mode, eim_edge, and eim_level regi sters. each interrupt n has a bit intn in each of these registers. similarly, each interrupt has a corresponding bit in each of the interrupt control and status regis- ters. writing 1 to the intn strobe in eim_ier enables the external interrupt on pin extintn, while writing 1 to intn in eim_idr disables the external interrupt. eim_imr can be read to check which interrupts are enabled. when the interrupt triggers, the corresponding bit in eim_isr will be set. for edge triggered interrupt s, the flag remains set until the corresponding strobe bit in eim_icr is written to 1. for level triggered interrupts, the flag remains set for as long as the interrupt condition is present on the pin. writing intn in eim_mode to 0 enables edge triggered interrupts, while writing the bit to 1 enables level triggered interrupts. if extintn is configured as an ed ge triggered inte rrupt, writing in tn in eim_edge to 0 will trig- ger the interrupt on falling edge, while writing the bit to 1 will trigger the interr upt on risi ng edge. if extintn is configured as a le vel triggered interrupt, writing intn in eim_level to 0 will trig- ger the interrupt on low level, while writin g the bit to 1 will trigger the interrupt on high level. 14.5.1.1 synchronization of external interrupts the pin value of the extintn pins is normally sy nchronized to the cpu clo ck, so spikes shorter than a cpu clock cycle are not guaranteed to produce an interrupt. in stop mode, spikes shorter than a 32khz clock cycle are not guaranteed to produce an interrupt. in deepdown mode, only unsynchronized level interr upts remain active, and any short sp ike on this interrupt will wake up the device.
137 32003e?avr32?05/06 at32ap7000 14.5.2 nmi control the non-maskable interrupt of the cpu is connected to the nmi_n pin through masking logic in the external interrupt module. this masking ensures that the nmi will not trigger before the cpu has been set up to handle interrupts. writing the en bit in the eim_nmic register enables the nmi interrupt, while writing en to 0 disables the nmi interrupt. when enabled, the interrupt trig- gers whenever the nmi_n pin is negated. the nmi_n pin is synchronized the same way as external level interrupts.
138 32003e?avr32?05/06 at32ap7000 14.6 user interface offset register register name access reset 0x00 eim interrupt enable eim_ier write-only 0x0 0x04 eim interrupt disable eim_idr write-only 0x0 0x08 eim interrupt mask eim_imr read-only 0x0 0x0c eim interrupt status eim_isr read-only 0x0 0x10 eim interrupt clear eim_icr write-only 0x0 0x14 external interrupt mode eim_mode read/write 0x0 0x18 external interrupt edge eim_edge read/write 0x0 0x1c external interrupt le vel eim_level read/write 0x0 0x24 external interrupt nmi control eim_nmic read/write 0x0
139 32003e?avr32?05/06 at32ap7000 14.6.1 eim interrupt enable/disable/mask/status/clear name: eim_ier/idr/imr/isr/icr access type: eim_ier/idr/icr: write-only eim_imr/isr: read-only ? intn: external interrupt n 0: external interrupt has not triggered 1: external interrupt has triggered the effect of writing or reading the bits listed above depends on which register is being accessed: ? ier (write-only) 0: no effect 1: enable interrupt ? idr (write-only) 0: no effect 1: disable interrupt ? imr (read-only) 0: interrupt is disabled 1: interrupt is enabled ? isr (read-only) 0: an interrupt event has occurred 1: an interrupt even has not occurred ? icr (write-only) 0: no effect 1: clear interrupt event 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - int3 int2 int1 int0
140 32003e?avr32?05/06 at32ap7000 14.6.2 external interrupt mode/edge/level name: eim_mode/edge/level access type: read/write ? intn: external interrupt n the bit interpretation is register specific: ? eim_mode 0: interrupt is edge triggered 1: interrupt is level triggered ? eim_edge 0: interrupt triggers on falling edge 1: interrupt triggers on rising edge ? eim_level 0: interrupt triggers on low level 1: interrupt triggers on high level 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - - - int3 int2 int1 int0
141 32003e?avr32?05/06 at32ap7000 14.6.3 nmi control name: eim_nmic access type: read/write ? en: enable 0: nmi disabled. asserting the nmi_n pin does not generate an nmi request. 1: nmi enabled. asserting the nm i_n pin generate an nmi request. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -------en
142 32003e?avr32?05/06 at32ap7000 15. ahb bus matrix (hmatrix) rev: 6029a 15.1 features ? system bus advanced high-performance bus (ahb lite) compliant interfaces ? apb compliant user interface ? configurable number of masters (up to sixteen) ? configurable number of slaves (up to sixteen) ? one decoder for each master ? three different memory mappin gs for each master (interna l and external boot, remap) ? one remap function for each master ? programmable arbitration for each slave ? round-robin ? fixed priority ? programmable default master for each slave ? no default master ? last accessed default master ? fixed default master ? one cycle latency for the first access of a burst ? zero cycle latency for default master ? one special function register for each slave (not dedicated) 15.2 description the bus matrix implements a multi-layer ahb, based on the ahb-lite protocol, that enables par- allel access paths between multiple ahb master s and slaves in a system, thus increasing the overall bandwidth. the bus matrix interconnects up to 16 ahb masters to up to 16 ahb slaves. the normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). the bus matrix user inter- face is compliant with arm ? advance peripheral bus and provides 16 special function registers (sfr) that allow the bus matrix to support application specific features. 15.3 memory mapping the bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. in fact, depending on the product, each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e. external ram, internal rom or internal flash, etc.) becomes possible. the bus matrix user interface provides master remap control register (mrcr) that performs remap action for every master independently. 15.4 special bus granting mechanism the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this mechanism reduc es latency at first access of a burst or single transfer. this bus granting mechanism sets a different default master for every slave. at the end of the current access, if no other re quest is pending, the slave remains connected to its associated default master. a slave can be as sociated with three kinds of default masters: no default master, last access master and fixed default master.
143 32003e?avr32?05/06 at32ap7000 15.5 no default master at the end of the current access, if no other request is pending, the slave is disconnected from all masters. no default ma ster suits low-power mode. 15.6 last access master at the end of the current access, if no other re quest is pending, the slave remains connected to the last master that performed an access request. 15.7 fixed default master at the end of the current access, if no other r equest is pending, the slave connects to its fixed default master. unlike last access master, the fixed master does not change unless the user modifies it by a software action (field fixed_defmstr of the related scfg). to change from one kind of default master to another, the bus matrix user interface provides the slave configuration registers, one for each slave, that set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr. the 2-bit defmstr_type field selects the default mast er type (no default, last access master, fixed default master), whereas the 4-bit fixed_defmstr field selects a fixed default master pro- vided that defmstr_type is set to fixed default master. please refer to the bus matrix user interface description. 15.8 arbitration the bus matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. one arbiter per ahb slave is provided, thus ar bitrating each slave differently. the bus matrix provides the user with the possibility of choosing between 2 arbitration types for each slave: 1. round-robin arbitration (default) 2. fixed priority arbitration this choice is made via the field arbt of the slave configuration registers (scfg). each algorithm may be complemented by selecting a default master configuration for each slave. when a re-arbitration must be done, specific condi tions apply. see section 15.8.1 ?arbitration rules? on page 143 . 15.8.1 arbitration rules each arbiter has the ability to arbitrate between two or more different master requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra- tion may only take place during the following cycles: 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. see section ?15.8.1.1? on page 144.
144 32003e?avr32?05/06 at32ap7000 4. slot cycle limit: when the slot cycle counte r has reached the limit value indicating that the current master access is too long and must be broken. see section ?15.8.1.2? on page 144. 15.8.1.1 undefined length burst arbitration in order to avoid long slave handling during unde fined length bursts (incr), the bus matrix pro- vides specific logic in order to re-arbitrate before the end of the incr transfer. a predicted end of burst is used as a defined length burst transfer and can be selected from among the following five possibilities: 1. infinite: no predicted end of burst is gen erated and therefore i ncr burst transfer will never be broken. 2. one beat bursts: predicted end of burst is generated at each single transfer inside the incp transfer. 3. four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside incr transfer. 4. eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside incr transfer. 5. sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside incr transfer. this selection can be done through the field ulbt of the master configuration registers (mcfg). 15.8.1.2 slot cycle limit arbitration the bus matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). at the beginning of the burst access, a counter is loaded with the value previously written in the slot_cycle field of the related slave configuration register (scfg) and decreased at each clock cycle. when the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer. 15.8.2 round-robin arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. if two or more master requests arise at the same time, the master with the lowest number is first serviced, then the others are serviced in a round-robin manner. there are three round-robin algorithms implemented: ? round-robin arbitration without default master ? round-robin arbitration with last default master ? round-robin arbitration with fixed default master 15.8.2.1 round-robin arbitration without default master this is the main algorithm used by bus matrix arbiters. it allows the bus matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. at the end of the current access, if no other request is pending, the slave is disconnected from all masters. this configuration incurs one latency cycle for the first access of a burst. arbitration without default master can be used for masters that perform significant bursts.
145 32003e?avr32?05/06 at32ap7000 15.8.2.2 round-robin arbitration with last default master this is a biased round-robin algorithm used by bus matrix arbiters. it allows the bus matrix to remove the one late ncy cycle for the last master that acce ssed the slave. in fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. other non priv ileged masters still get one latency cycle if they want to access the same slave. this technique can be used for masters that mainly perform single accesses. 15.8.2.3 round-robin arbitration with fixed default master this is another biased round-robin algorithm. it a llows the bus matrix arbiters to remove the one latency cycle for the fixed default master per slav e. at the end of the current access, the slave remains connected to its fixed default master. every request attempted by this fixed default mas- ter will not cause any latency whereas other non privileged masters w ill still get one latency cycle. this technique can be used for masters that mainly perform single accesses. 15.8.3 fixed priority arbitration this algorithm allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. if two or more master requests are active at the same time, the master with the highest priority number is serviced first. if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. for each slave, the priority of each master may be defined through the priority registers for slaves (pras and prbs).
146 32003e?avr32?05/06 at32ap7000 15.9 ahb generic bus ma trix user interface table 15-1. register mapping offset register name access reset value 0x0000 master configuration register 0 mcfg0 read/write 0x00000002 0x0004 master configuration register 1 mcfg1 read/write 0x00000002 0x0008 master configuration register 2 mcfg2 read/write 0x00000002 0x000c master configuration register 3 mcfg3 read/write 0x00000002 0x0010 master configuration register 4 mcfg4 read/write 0x00000002 0x0014 master configuration register 5 mcfg5 read/write 0x00000002 0x0018 master configuration register 6 mcfg6 read/write 0x00000002 0x001c master configuration register 7 mcfg7 read/write 0x00000002 0x0020 master configuration register 8 mcfg8 read/write 0x00000002 0x0024 master configuration register 9 mcfg9 read/write 0x00000002 0x0028 master configuration register 10 mcfg10 read/write 0x00000002 0x002c master configuration regi ster 11 mcfg11 read/write 0x00000002 0x0030 master configuration register 12 mcfg12 read/write 0x00000002 0x0034 master configuration register 13 mcfg13 read/write 0x00000002 0x0038 master configuration register 14 mcfg14 read/write 0x00000002 0x003c master configuration regi ster 15 mcfg15 read/write 0x00000002 0x0040 slave configuration register 0 scfg0 read/write 0x00000010 0x0044 slave configuration register 1 scfg1 read/write 0x00000010 0x0048 slave configuration register 2 scfg2 read/write 0x00000010 0x004c slave configuration register 3 scfg3 read/write 0x00000010 0x0050 slave configuration register 4 scfg4 read/write 0x00000010 0x0054 slave configuration register 5 scfg5 read/write 0x00000010 0x0058 slave configuration register 6 scfg6 read/write 0x00000010 0x005c slave configuration register 7 scfg7 read/write 0x00000010 0x0060 slave configuration register 8 scfg8 read/write 0x00000010 0x0064 slave configuration register 9 scfg9 read/write 0x00000010 0x0068 slave configuration register 10 scfg10 read/write 0x00000010 0x006c slave configuration register 11 scfg11 read/write 0x00000010 0x0070 slave configuration register 12 scfg12 read/write 0x00000010 0x0074 slave configuration register 13 scfg13 read/write 0x00000010 0x0078 slave configuration register 14 scfg14 read/write 0x00000010 0x007c slave configuration register 15 scfg15 read/write 0x00000010 0x0080 priority register a for slave 0 pras0 read/write 0x00000000 0x0084 priority register b for slave 0 prbs0 read/write 0x00000000 0x0088 priority register a for slave 1 pras1 read/write 0x00000000
147 32003e?avr32?05/06 at32ap7000 0x008c priority register b for slave 1 prbs1 read/write 0x00000000 0x0090 priority register a for slave 2 pras2 read/write 0x00000000 0x0094 priority register b for slave 2 prbs2 read/write 0x00000000 0x0098 priority register a for slave 3 pras3 read/write 0x00000000 0x009c priority register b for slave 3 prbs3 read/write 0x00000000 0x00a0 priority register a for slave 4 pras4 read/write 0x00000000 0x00a4 priority register b for slave 4 prbs4 read/write 0x00000000 0x00a8 priority register a for slave 5 pras5 read/write 0x00000000 0x00ac priority register b for slave 5 prbs5 read/write 0x00000000 0x00b0 priority register a for slave 6 pras6 read/write 0x00000000 0x00b4 priority register b for slave 6 prbs6 read/write 0x00000000 0x00b8 priority register a for slave 7 pras7 read/write 0x00000000 0x00bc priority register b for slave 7 prbs7 read/write 0x00000000 0x00c0 priority register a for slave 8 pras8 read/write 0x00000000 0x00c4 priority register b for slave 8 prbs8 read/write 0x00000000 0x00c8 priority register a for slave 9 pras9 read/write 0x00000000 0x00cc priority register b for slave 9 prbs9 read/write 0x00000000 0x00d0 priority register a for slave 10 pras10 read/write 0x00000000 0x00d4 priority register b for slave 10 prbs10 read/write 0x00000000 0x00d8 priority register a for slave 11 pras11 read/write 0x00000000 0x00dc priority register b for slave 11 prbs11 read/write 0x00000000 0x00e0 priority register a for slave 12 pras12 read/write 0x00000000 0x00e4 priority register b for slave 12 prbs12 read/write 0x00000000 0x00e8 priority register a for slave 13 pras13 read/write 0x00000000 0x00ec priority register b for slave 13 prbs13 read/write 0x00000000 0x00f0 priority register a for slave 14 pras14 read/write 0x00000000 0x00f4 priority register b for slave 14 prbs14 read/write 0x00000000 0x00f8 priority register a for slave 15 pras15 read/write 0x00000000 0x00fc priority register b for slave 15 prbs15 read/write 0x00000000 0x0100 master remap control register mrcr read/write 0x00000000 0x0104 - 0x010c reserved ? ? ? 0x0110 special function register 0 sfr0 read/write 0x00000000 0x0114 special function register 1 sfr1 read/write 0x00000000 0x0118 special function register 2 sfr2 read/write 0x00000000 0x011c special function register 3 sfr3 read/write 0x00000000 0x0120 special function register 4 sfr4 read/write 0x00000000 table 15-1. register mapping (continued) offset register name access reset value
148 32003e?avr32?05/06 at32ap7000 0x0124 special function register 5 sfr5 read/write 0x00000000 0x0128 special function register 6 sfr6 read/write 0x00000000 0x012c special function register 7 sfr7 read/write 0x00000000 0x0130 special function register 8 sfr8 read/write 0x00000000 0x0134 special function register 9 sfr9 read/write 0x00000000 0x0138 special function register 10 sfr10 read/write 0x00000000 0x013c special function register 11 sfr11 read/write 0x00000000 0x0140 special function register 12 sfr12 read/write 0x00000000 0x0144 special function register 13 sfr13 read/write 0x00000000 0x0148 special function register 14 sfr14 read/write 0x00000000 0x014c special function register 15 sfr15 read/write 0x00000000 0x0150 - 0x01f8 reserved ? ? ? table 15-1. register mapping (continued) offset register name access reset value
149 32003e?avr32?05/06 at32ap7000 15.10 bus matrix master configuration registers register name: mcfg0...mcfg15 access type: read/write ? ulbt: undefined length burst type 0: infinite length burst no predicted end of burst is generated and therefore incr bursts coming from this master cannot be broken. 1: single access the undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the incr burst. 2: four beat burst the undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. 3: eight beat burst the undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. 4: sixteen beat burst the undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? ulbt
150 32003e?avr32?05/06 at32ap7000 15.11 bus matrix slave configuration registers register name: scfg0...scfg15 access type: read/write ? slot_cycle: maximum number of allowed cycles for a burst when the slot_cycle limit is reached for a burst, it may be broken by another master tr ying to access this slave. this limit has been placed to avoid locking a very slow slave when very long bursts are used. this limit must not be very small. un reasonably small values break every burst and the bus matrix arbitrates without per- forming any data transfer. 16 cycles is a reasonable value for slot_cycle. ? defmstr_type: default master type 0: no default master at the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in a one cycle latency for the first access of a burst transfer or for a single access. 1: last default master at the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. this results in not having one cycle latency when the last master tries to access the slave again. 2: fixed default master at the end of the current slave access, if no other master r equest is pending, the slave connec ts to the fixed master the number that has been written in the fixed_defmstr field. this results in not having one cycle latency when the fixed master tries to access the slave again. ? fixed_defmstr: fixed default master this is the number of the defa ult master for this slave. only used if defmstr_type is 2. specifying the number of a mas- ter which is not connected to the selected slave is equivalent to setting defmstr_type to 0. ? arbt: arbitration type 0: round-robin arbitration 1: fixed priority arbitration 31 30 29 28 27 26 25 24 ???????arbt 23 22 21 20 19 18 17 16 ? ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????? 76543210 slot_cycle
151 32003e?avr32?05/06 at32ap7000 15.12 bus matrix priority registers a for slaves register name: pras0...pras15 access type: read/write ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. 31 30 29 28 27 26 25 24 ?? m7pr ?? m6pr 23 22 21 20 19 18 17 16 ?? m5pr ?? m4pr 15 14 13 12 11 10 9 8 ?? m3pr ?? m2pr 76543210 ?? m1pr ?? m0pr
152 32003e?avr32?05/06 at32ap7000 15.13 bus matrix priority registers b for slaves register name: prbs0...prbs15 access type: read/write ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. 31 30 29 28 27 26 25 24 ? ? m15pr ? ? m14pr 23 22 21 20 19 18 17 16 ? ? m13pr ? ? m12pr 15 14 13 12 11 10 9 8 ? ? m11pr ? ? m10pr 76543210 ?? m9pr ?? m8pr
153 32003e?avr32?05/06 at32ap7000 15.14 bus matrix master remap control register register name: mrcr access type: read/write reset: 0x0000_0000 ? rcb: remap command bit for master x 0: disable remapped address decoding for the selected master 1: enable remapped address decoding for the selected master 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rcb15 rcb14 rcb13 rcb12 rcb11 rcb10 rcb9 rcb8 76543210 rcb7 rcb6 rcb5 rcb4 rcb3 rcb2 rcb1 rcb0
154 32003e?avr32?05/06 at32ap7000 15.15 bus matrix speci al function registers register name: sfr0...sfr15 access type: read/write reset: 0x0000_0000 ? sfr: special function register fields the sfr fields are a set of d-type flip-flops whic h are only connected to outputs of the bus matrix. they are readable/writable from the user interface and may be used to implement configuration registers which cannot be implemented in any of the other embedded peripherals of the product. each bit of the sfr may be removed by hard- ware customization at synthesis if not used. 31 30 29 28 27 26 25 24 sfr 23 22 21 20 19 18 17 16 sfr 15 14 13 12 11 10 9 8 sfr 76543210 sfr
155 32003e?avr32?05/06 at32ap7000 16. external bus interface (ebi) rev: 1.0.0 16.1 features ? optimized for application memory space support ? integrates three external memory controllers: ? static memory controller ? sdram controller ? ecc controller ? additional logic for nand flash/smartmedia tm and compactflash tm support ? smartmedia support: 8-bit as well as 16-bit devices are supported ? compactflash support: all modes (attribute memory, common memory, i/o, true ide) are supported but the signal s _iois16 (i/o and true ide modes) and _ata sel (true ide mode) are not handled. ? optimized external bus: ? 16- or 32-bit data bus ? up to 26-bit address bus, up to 64-mbytes addressable ? optimized pin multiplexing to redu ce latencies on external memories ? up to 6 chip selects, configurable assignment: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs 3, optional nand flash/smartmedia tm support ? static memory controller on ncs 4 - ncs5, optional compactflash tm support 16.2 description the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an avr32 device. the static memory, sdram and ecc controllers are all featured external memory controllers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram , prom, eprom, eeprom, flash, and sdram. the ebi also supports the compactflash and the nand flash/smartmedia protocols via inte- grated circuitry that greatly reduces the requirements for external components. furthermore, the ebi handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (ncs[5:0]) and sev- eral control pins that are generally multip lexed between the different external memory controllers.
156 32003e?avr32?05/06 at32ap7000 16.3 block diagram 16.3.1 external bus interface figure 16-1 shows the organization of the external bus interface. figure 16-1. organization of the external bus interface external bus interface 0 d[15:0] a[15:2], a[22:18] pio mux logic user interface chip select assignor static memory controller sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2 a17/ba1 ncs0 ncs3/nandcs nrd/noe/cfoe ncs1/sdcs0 nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras cas sdwe d[31:16] a[25:23] cfrnw ncs4/cfcs0 ncs5/cfcs1 ncs2 cfce1 cfce2 nwait sda10 nandoe nandwe nand flash smartmedia logic compactflash logic ecc controller sdcs1
157 32003e?avr32?05/06 at32ap7000 16.4 i/o lines description table 16-1. ebi i/o lines description name function type active level ebi d0 - d31 data bus i/o a0 - a25 address bus output nwait external wait signal input low smc ncs0 - ncs5 chip select lines output low nwr0 - nwr3 write signals output low noe output enable output low nrd read signal output low nwe write enable output low nbs0 - nbs3 byte mask signals output low ebi for compactflash support cfce1 - cfce2 compactflash chip enable output low cfoe compactflash output enable output low cfwe compactflash write enable output low cfior compactflash i/o read signal output low cfiow compactflash i/o write signal output low cfrnw compactflash read not write signal output cfcs0 - cfcs1 compactflash chip select lines output low ebi for nand flash/smartmedia support nandcs smartmedia chip select line output low nandoe smartmedia output enable output low nandwe smartmedia write enable output low sdram controller sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select line output low ba0 - ba1 bank select output sdwe sdram write enable output low ras - cas row and column signal output low nwr0 - nwr3 write signals output low nbs0 - nbs3 byte mask signals output low sda10 sdram address 10 line output
158 32003e?avr32?05/06 at32ap7000 depending on the memory controller in use, all signals are not connected directly through the mux logic. table 16-2 on page 158 details the connections between the two memory controllers and the ebi pins. table 16-2. ebi pins and memory controllers i/o lines connections ebi pins sdramc i/o lines smc i/o lines nwr1/nbs1/cfior nbs1 nwr1/nub a0/nbs0 not supported smc_a0/nlb a1/nbs2/nwr2 not supported smc_a1 a[11:2] sdramc_a[9:0] smc_a[11:2] sda10 sdramc_a10 not supported a12 not supported smc_a12 a[14:13] sdramc_a[12:11] smc_a[14:13] a[22:15] not supported smc_a[22:15] a[25:23] not supported smc_a[25:23] d[31:0] d[31:0] d[31:0]
159 32003e?avr32?05/06 at32ap7000 16.5 application example 16.5.1 hardware interface table 16-3 on page 159 details the connections to be applied between the ebi pins and the external devices for each memory controller. notes: 1. nwr1 enables upper byte writes. nwr0 enables lower byte writes. 2. nwrx enables corresponding byte x writes. (x = 0,1,2 or 3) 3. nbs0 and nbs1 enable respectively lower and upper bytes of the lower 16-bit word. 4. nbs2 and nbs3 enable respectively lower and upper bytes of the upper 16-bit word. 5. bex: byte x enable (x = 0,1,2 or 3) table 16-3. ebi pins and external static devices connections signals pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 ? d8 - d15 d8 - d15 d8 - d15 d8 - 15 d8 - 15 d16 - d23 ? ? ? d16 - d23 d16 - d23 d16 - d23 d24 - d31 ? ? ? d24 - d31 d24 - d31 d24 - d31 a0/nbs0 a0 ? nlb ? nlb (3) be0 (5) a1/nwr2/nbs2 a1 a0 a0 we (2) nlb (4) be2 (5) a2 - a22 a[2:22] a[1:21] a[1:21] a[0:20] a[0:20] a[0:20] a23 - a25 a[23:25] a[22:24] a[22:24] a[21:23] a[21:23] a[21:23] ncs0 cs cs cs cs cs cs ncs1/sdcs0 cs cs cs cs cs cs ncs2 cs cs cs cs cs cs ncs3/nandcs cs cs cs cs cs cs ncs4/cfcs0 cs cs cs cs cs cs ncs5/cfcs1 cs cs cs cs cs cs nrd/noe/cfoe oe oe oe oe oe oe nwr0/nwe we we (1) we we (2) we we nwr1/nbs1 ? we (1) nub we (2) nub (3) be1 (5) nwr3/nbs3 ? ? ? we (2) nub (4) be3 (5) sdsc1 ? ? ? ? ? cs
160 32003e?avr32?05/06 at32ap7000 table 16-4. ebi pins and external devices connections signals pins of the interfaced device sdram compact flash compact flash true ide mode smart media or nand flash controller sdramc smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 ad0-ad7 d8 - d15 d8 - d15 d8 - 15 d8 - 15 ad8-ad15 d16 - d31 d16 - d31 ? ? ? a0/nbs0 dqm0 a0 a0 ? a1/nwr2/nbs2 dqm2 a1 a1 ? a2 - a10 a[0:8] a[2:10] a[2:10] ? a11 a9 ? ? ? sda10 a10 ? ? ? a12 ? ? ? ? a13 - a14 a[11:12] ? ? ? a15 ? ? ? ? a16/ba0 ba0 ? ? ? a17/ba1 ba1 ? ? ? a18 - a20 ? ? ? ? a21 ? ? ? cle (3) a22 ? reg reg ale (3) a23 - a24 ? ? ? ? a25 ? cfrnw (1) cfrnw (1) ? ncs0 ? ? ? ? ncs1/sdcs0 cs[0] ? ? ? ncs2 ? ? ? ? ncs2/nandcs ? ? ? ? ncs3/nandcs ? ? ? ? ncs4/cfcs0 ? cfcs0 (1) cfcs0 (1) ? ncs5/cfcs1 ? cfcs1 (1) cfcs1 (1) ? nandoe ? ? ? oe nandwe ? ? ? we nrd/noe/cfoe ? oe ? ? nwr0/nwe/cfwe ? we we ? nwr1/nbs1/cfior dqm1 ior ior ? nwr3/nbs3/cfiow dqm3 iow iow ? cfce1 ? ce1 cs0 ? cfce2 ? ce2 cs1 ?
161 32003e?avr32?05/06 at32ap7000 note: 1. not directly connected to t he compactflash slot. permits the co ntrol of the bidirectional buffer between the ebi data bus a nd the compactflash slot. 2. any pio line. 3. the cle and ale signals of the smartmedia device may be driven by any address bit. for details, see ?smartmedia and nand flash support? on page 168 . sdck clk ? ? ? sdcke cke ? ? ? ras ras ? ? ? cas cas ? ? ? sdwe we ? ? ? nwait ? wait wait ? pxx (2) ? cd1 or cd2 cd1 or cd2 ? pxx (2) ???ce pxx (2) ???rdy sdcs1 cs[1] ? ? ? table 16-4. ebi pins and external devices connections (continued) signals pins of the interfaced device sdram compact flash compact flash true ide mode smart media or nand flash controller sdramc smc
162 32003e?avr32?05/06 at32ap7000 16.5.2 connection examples figure 16-2 shows an example of connections be tween the ebi and external devices. figure 16-2. ebi connections to memory devices ebi d0-d31 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a25 a10 sda10 sda10 a2-a11, a13 ncs0 ncs2 ncs3 ncs4 ncs5 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 nbs0 nbs1 nbs3 nbs2 nrd/noe nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe sdwe sdwe
163 32003e?avr32?05/06 at32ap7000 16.6 product dependencies 16.6.1 i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus interface pins to their peripheral function. if i/o lines of the external bus interface are not used by the applica- tion, they can be used for other purposes by the pio controller. 16.7 functional description the ebi transfers data between the internal ahb bus (handled by the hmatrix) and the external memories or peripheral devices. it controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements: ? the static memory controller (smc) ? the sdram controller (sdramc) ? the ecc controller (ecc) ? a chip select assignment feature that assigns an ahb address space to the external devices ? a multiplex controller circuit that shares the pins between the different memory controllers ? programmable compactflash support logic ? programmable smartmedia and nand flash support logic 16.7.1 bus multiplexing the ebi offers a complete set of control signal s that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. multiplexing is specifically organized in or der to guarantee the maintenance of the address and output control lines at a stable state while no ex ternal access is being pe rformed. mult iplexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the sdram are executed independently by the sdram controller without delaying the other external memory controller accesses. 16.7.2 pull-up control a specific hmatrix_sfr register in the matrix user interface permit enabling of on-chip pull-up resistors on the data bu s lines not multiplexed with the pio controller lines. for details on this register, refer to the peripherals section. the pull-up resistors are enabled after reset. setting the ebi_dbpuc bit disables the pull-up resistors on lines not muxed with pio. enabling the pull- up resistor on lines multiplexed with pio lines can be performed by programming the appropri- ate pio controller. 16.7.3 static memory controller for information on the static memory controller, refer to the static memory controller section. 16.7.4 sdram controller for information on the sdram contro ller, refer to the sdram section. 16.7.5 ecc controller for information on the ecc contro ller, refer to the ecc section.
164 32003e?avr32?05/06 at32ap7000 16.7.6 compactflash support the external bus interface integrates circuitry that interfaces to compactflash devices. the compactflash logic is driven by the st atic memory controller (smc) on the ncs4 and/or ncs5 address space. programming the ebi_cs4 a and/or ebi_cs5a bits in a hmatrix_sfr register to the appropriate value enables this logic. for details on this register, refer to the peripherals section. access to an external compactflash device is then made by accessing the address space reserved to ncs4 and/or ncs5 (i.e., between 0x5000 0000 and 0x5fff ffff for ncs4 and between 0x6000 0000 and 0x6fff ffff for ncs5). all compactflash modes (attribute memory, common memory, i/o and true ide) are sup- ported but the signals _iois16 (i/o and true ide modes) and _ata sel (true ide mode) are not handled. 16.7.6.1 i/o mode, common memory mode, attribute memory mode and true ide mode within the ncs4 and/or ncs5 address space, the current transfer address is used to distinguish i/o mode, common memory mode, attribute memory mode and true ide mode. the different modes are accessed through a specific memory mapping as illustrated on figure 16-3 . a[23:21] bits of the transfer address are used to select the desired mode as described in table 16-5 on page 165 . figure 16-3. compactflash memory mapping note: the a22 pin is used to drive the reg signal of the compactflash device (except in true ide mode). cf address space attribute memory mode space common memory mode space i/o mode space true ide mode space true ide alternate mode space offset 0x00e0 0000 offset 0x00c0 0000 offset 0x0080 0000 offset 0x0040 0000 offset 0x0000 0000
165 32003e?avr32?05/06 at32ap7000 16.7.6.2 cfce1 and cfce2 signals to cover all types of access, the smc must be al ternatively set to drive 8-bit data bus or 16-bit data bus. the odd byte access on the d[7:0] bus is only possible when the smc is configured to drive 8-bit memory devices on the corresponding ncs pin (ncs4 or ncs5). the chip select register (dbw field in the corresponding chip select register) of the ncs4 and/or ncs5 address space must be set as shown in table 16-6 to enable the required access type. nbs1 and nbs0 are the byte selection signals from smc and are available when the smc is set in byte select mode on the corresponding chip select. the cfce1 and cfce2 waveforms are identical to the corresponding ncsx waveform. for details on these waveforms and timings, refer to the static memory controller section. table 16-5. compactflash mode selection a[23:21] mode base address 000 attribute memory 010 common memory 100 i/o mode 110 true ide mode 111 alternate true ide mode table 16-6. cfce1 and cfce2 truth table mode cfce2 cfce1 dbw comment smc access mode attribute memory nbs1 nbs0 16 bits access to even byte on d[7:0] byte select common memory nbs1 nbs0 16bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] i/o mode nbs1 nbs0 16 bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] true ide mode task file 1 0 8 bits access to even byte on d[7:0] access to odd byte on d[7:0] data register 1 0 16 bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select alternate true ide mode control register alternate status read 01 don?t care access to even byte on d[7:0] don?t care drive address 0 1 8 bits access to odd byte on d[7:0] standby mode or address space is not assigned to cf 11? ? ?
166 32003e?avr32?05/06 at32ap7000 16.7.6.3 read/write signals in i/o mode and true ide mode, the compactflash logic drives the read and write command signals of the smc on cfior and cfiow signals, while the cfoe and cfwe signals are deac- tivated. likewise, in common memory mode and attribute memory mode, the smc signals are driven on the cfoe and cfwe signals, while the cfior and cfiow are deactivated. figure 16-4 on page 166 demonstrates a schematic representation of this logic. attribute memory mode, common memory mode and i/o mode are supported by setting the address setup and hold time on the ncs4 (and/or ncs5) chip select to the appropriate values. for details on these signal waveforms, please refer to the section: setup and hold cycles of the static memory controller section. figure 16-4. compactflash read/write control signals 16.7.6.4 multiplexing of compactflash signals on ebi pins table 16-8 on page 167 and table 16-9 on page 167 illustrate the multiple xing of the compact- flash logic signals with other ebi signals on the ebi pins. the ebi pins in table 16-8 are strictly dedicated to the compactflash interface as soon as the ebi_cs4a and/or ebi_cs5a field of a specific hmatrix_sfr register is set, see the peripherals section for details. these pins must not be used to drive any other memory devices. the ebi pins in table 16-9 on page 167 remain shared between all memory areas when the cor- responding compactflash interface is enabled (ebi_cs4a = 1 and/or ebi_cs5a = 1). table 16-7. compactflash mode selection mode base address cfoe cfwe cfior cfiow attribute memory common memory nrd_noe nwr0_nwe 1 1 i/o mode 1 1 nrd_noe nwr0_nwe true ide mode 0 1 nrd_noe nwr0_nwe smc nrd_noe nwr0_nwe a23 cfior cfiow cfoe cfwe 1 1 compactflash logic external bus interface 1 1 1 0 a22 1 0 1 0 1 0
167 32003e?avr32?05/06 at32ap7000 16.7.6.5 application example figure 16-5 on page 168 illustrates an example of a comp actflash application. cfcs0 and cfrnw signals are not directly connected to the compactflash slot 0, but do control the direc- tion and the output enable of the buffers between the ebi and the compactflash device. the timing of the cfcs0 signal is identical to the ncs4 signal. moreover, the cfrnw signal remains valid throughout the transfer, as does the address bus. the compactflash _wait sig- nal is connected to the nwait input of the static memory controller. for details on these waveforms and timings, refer to the static memory controller section. table 16-8. dedicated compactflash interface multiplexing pins compactflash signals ebi signals cs4a = 1 cs5a = 1 cs4a = 0 cs5a = 0 ncs4/cfcs0 cfcs0 ncs4 ncs5/cfcs1 cfcs1 ncs5 table 16-9. shared compactflash interface mu ltiplexing pins access to compactflash device access to other ebi devices compactflash sign als ebi signals noe/nrd/cfoe cfoe nrd/noe nwr0/nwe/cfwe cfwe nwr0/nwe nwr1/nbs1/cfior cfior nwr1/nbs1 nwr3/nbs3/cfiow cfiow nwr3/nbs3 a25/cfrnw cfrnw a25
168 32003e?avr32?05/06 at32ap7000 figure 16-5. compactflash application example 16.7.7 smartmedia and nand flash support the external bus interface integrates circuitry that interfaces to smartmedia and nand flash devices. the smartmedia logic is driven by the static memory controller on the ncs3 address space. programming the ebi_cs3a field in a specific hmatrix_sfr register to the appropriate value enables the smartmedia logic. for details on this register, refer to the peripherals section. access to an external smartmedia device is then made by accessing the address space reserved to ncs3 (i.e., between 0x4000 0000 and 0x4fff ffff). the smartmedia logic drives the read and write command signals of the smc on the nandoe and nandwe signals when the ncs3 signal is active. nandoe and nandwe are invalidated as soon as the transfer address fails to lie in the ncs3 address space. see figure ?smartmedia signal multiplexing on ebi pins? on page 169 for more informations. fo r details on these wave- forms, refer to the static memory controller section. compactflash connecto r ebi d[15:0] /oe dir _cd1 _cd2 /oe d[15:0] a25/cfrnw ncs4/cfcs0 cd (pio) a[10:0] a22/reg noe/cfoe a[10:0] _reg _oe _we _iord _iowr _ce1 _ce2 nwe/cfwe nwr1/cfior nwr3/cfiow cfce1 cfce2 _wait nwait
169 32003e?avr32?05/06 at32ap7000 figure 16-6. smartmedia signal mult iplexing on ebi pins 16.7.7.1 smartmedia signals the address latch enable and command latch enable signals on the smartmedia device are driven by address bits a22 and a21 of the ebi a ddress bus. the user should note that any bit on the ebi address bus can also be used for this purpose. the command, address or data words on the data bus of the smartmedia device are distinguished by using their address within the ncsx address space. the chip enable (ce) signal of the device and the ready/busy (r/b) sig- nals are connected to pio lines. the ce signal then remains asserted even when ncsx is not selected, preventing the device from returning to standby mode. smc nrd_noe nwr0_nwe nandoe nandwe smartmedia logic ncsx nandwe nandoe
170 32003e?avr32?05/06 at32ap7000 figure 16-7. smartmedia application example note: the external bus interfaces is also able to support 16-bits devices. d[7:0] ale nandwe nandoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce smartmedia pio ncsx/nandcs not connected
171 32003e?avr32?05/06 at32ap7000 17. dma controller (dmac) rev: 6140b 17.1 features ? 2 ahb master interfaces ? 3 channels ? software and hardware handshaking interfaces ? 11 hardware handshaking interfaces ? memory/non-memory periph erals to memory/non-mem ory peripherals transfer ? single-block dma transfer ? multi-block dma transfer ? linked lists ? auto-reloading ? contiguous blocks ? dma controller is always the flow controller ? additional features ? scatter and gather operations ? channel locking ? bus locking ? fifo mode ? pseudo fly-by operation 17.2 description the dma controller (dmac) is an ahb-central dma controller core that transfers data from a source peripheral to a destination peripheral over one or more system bus. one channel is required for each source/destination pair. in the most basic configuration, the dmac has one master interface and one channel. the master interface reads the data from a source and writes it to a destination. two system bus transfers are required for each dma data transfer. this is also known as a dual-access transfer. the dmac is programmed via the ahb slave interface.
172 32003e?avr32?05/06 at32ap7000 17.3 block diagram figure 17-1. dma controller (dmac) block diagram 17.4 functional description 17.4.1 basic definitions source peripheral: device on a system bus layer from where the dmac reads data, which is then stored in the channel fifo. the source peripheral teams up with a destination peripheral to form a channel. destination peripheral: device to which the dmac writes the stored data from the fifo (previ- ously read from the source peripheral). memory: source or destination that is always ?ready? for a dma transfer and does not require a handshaking interface to interact with the dmac. a peripheral should be assigned as memory only if it does not insert more than 16 wait states. if more than 16 wait states are required, then the peripheral should use a handshaking interface (the default if the peripheral is not pro- grammed to be memory) in order to signal when it is ready to accept or supply data. channel: read/write datapath between a source peripheral on one configured system bus layer and a destination peripheral on the same or different system bus layer that occurs through the channel fifo. if the source peripheral is not memory, then a source handshaking interface is assigned to the channel. if the destination pe ripheral is not memory, then a destination hand- shaking interface is assigned to the channel. so urce and destination handshaking interfaces can be assigned dynamically by programming the channel registers. master interface: dmac is a master on the ahb bus reading data from the source and writing it to the destination over the ahb bus. slave interface: the ahb interface over which the dmac is programmed. the slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. handshaking interface: a set of signal registers that conform to a protocol and handshake between the dmac and source or destination peri pheral to control the transfer of a single or burst transaction between them. this interface is used to request, acknowledge, and control a ahb slave i/f ahb master i/f cfg interrupt generator fifo channel 0 src fsm dst fsm channel 1 dma controller irq_dma ahb slave ahb master
173 32003e?avr32?05/06 at32ap7000 dmac transaction. a channel can receive a request through one of three types of handshaking interface: hardware, software, or peripheral interrupt. hardware handshaking interface: uses hardware signals to control the transfer of a single or burst transaction between the dmac and the source or destination peripheral. software handshaking interface: uses software registers to control the transfer of a single or burst transaction between the dmac and the source or destination peripheral. no special dmac handshaking signals are needed on the i/o of the peripheral. this mode is useful for interfacing an existing peripheral to the dmac without modifying it. peripheral interrupt handshaking interface: a simple use of the hardware handshaking inter- face. in this mode, the interrupt line from the peripheral is tied to the dma_req input of the hardware handshaking interface. other interface signals are ignored. flow controller: the device (either the dmac or source/destination peripheral) that determines the length of and terminates a dma block transfe r. if the length of a block is known before enabling the channel, then the dmac should be programmed as the flow controller. if the length of a block is not known prior to enabling the channel, the source or destination peripheral needs to terminate a block transfer. in this mode, the peripheral is the flow controller. flow control mode (cfgx.fcmode): special mode that only applies when the destination peripheral is the flow controller. it controls the pre-fetching of data from the source peripheral. transfer hierarchy: figure 17-2 on page 173 illustrates the hierarchy between dmac transfers, block transfers, transactions (single or burst), an d system bus transfers (single or burst) for non- memory peripherals. figure 17-3 on page 174 shows the transfer hierarchy for memory. figure 17-2. dmac transfer hierarchy for non-memory peripheral dmac transfer dma transfer level block block block block transfer level burst transaction burst transaction burst transaction single transaction dma transaction level burst transfer system bus burst transfer system bus burst transfer system bus single transfer system bus system bus transfer level single transfer system bus
174 32003e?avr32?05/06 at32ap7000 figure 17-3. dmac transfer hierarchy for memory block: a block of dmac data. the amount of data (block length) is determined by the flow con- troller. for transfers between the dmac and memo ry, a block is broken directly into a sequence of system bus bursts and single transfers. for transfers between the dmac and a non-memory peripheral, a block is broken into a sequence of dmac transactions (single and bursts). these are in turn broken into a sequence of system bus transfers. transaction: a basic unit of a dmac transfer as determined by either the hardware or software handshaking interface. a transaction is only relevant for transfers between the dmac and a source or destination peripheral if the source or destination peripheral is a non-memory device. there are two types of transactions: single and burst. ? single transaction: the length of a single transaction is always 1 and is converted to a single system bus transfer. ? burst transaction: the length of a burst transaction is programmed into the dmac. the burst transaction is converted into a sequence of system bus bursts and single transfers. dmac executes each burst transfer by performing incremental bursts that are no longer than the maximum system bus burst size set. the burst transaction length is under program control and normally bears some relationship to the fifo sizes in the dmac and in the source and destination peripherals. dma transfer: software controls the number of blo cks in a dmac transfer. once the dma transfer has completed, then hardware within the dmac disables the channel and can generate an interrupt to signal the completion of the dma transfer. you can then re-program the channel for a new dma transfer. single-block dma transfer: consists of a single block. dmac transfer dma transfer level block block block block transfer level burst transfer system bus burst transfer system bus burst transfer system bus single transfer system bus system bus transfer level
175 32003e?avr32?05/06 at32ap7000 multi-block dma transfer: a dma transfer may consist of mu ltiple dmac blocks. multi-block dma transfers are supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks. the source and destination can independently select which method to use. ? linked lists (block chaining) ? a linked list pointer (llp) points to the location in system memory where the next linked list item (lli) exists. the lli is a set of registers that describe the next block (block descriptor) and an llp register. the dmac fetches the lli at the beginning of every block when block chaining is enabled. ? auto-reloading ? the dmac automatically reloads the channel registers at the end of each block to the value when the channel was first enabled. ? contiguous blocks ? where the address between successive blocks is selected to be a continuation from the end of the previous block. scatter: relevant to destination transfers within a block. the destination system bus address is incremented/decremented by a programmed amount when a scatter boundary is reached. the number of system bus transfers between successive scatter boundaries is under software control. gather: relevant to source transfers within a block. the source system bus address is incre- mented/decremented by a programmed amount when a gather boundary is reached. the number of system bus transfers between successive gather boundaries is under software control. channel locking: software can program a channel to keep the ahb master interface by locking the arbitration for the master bus interface for the duration of a dma transfer, block, or transac- tion (single or burst). bus locking: software can program a channel to maintain control of the system bus bus by asserting hlock for the duration of a dma transfer, block, or transaction (single or burst). chan- nel locking is asserted for the duration of bus locking at a minimum. fifo mode: special mode to improve bandwidth. when enabled, the channel waits until the fifo is less than half full to fetch the data from the source peripheral and waits until the fifo is greater than or equal to half full to send data to the destination peripheral. thus, the channel can transfer the data using system bus bursts, eliminating the need to arbitrate for the ahb master interface for each single system bus transfer. when this mode is not enabled, the channel only waits until the fifo can transmit/accept a single system bus transfer before requesting the master bus interface. pseudo fly-by operation: typically, it takes two system bu s cycles to complete a transfer, one for reading the source and one for writing to the destination. however, when the source and des- tination peripherals of a dma transfer are on differ ent system bus layers, it is possible for the dmac to fetch data from the source and store it in the channel fifo at the same time as the dmac extracts data from the channel fifo and writes it to the destination peripheral. this activ- ity is known as pseudo fly-by operation . for this to occur, the master interface for both source and destination layers must win arbitration of their ahb layer. similarly, the source and destina- tion peripherals must win ownership of their respective master interfaces.
176 32003e?avr32?05/06 at32ap7000 17.5 memory peripherals figure 17-3 on page 174 shows the dma transfer hierarchy of the dmac for a memory periph- eral. there is no handshaking interface with the dmac, and therefore the memory peripheral can never be a flow controller. once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. the alternative to not having a transaction-level hand- shaking interface is to allow the dmac to attempt system bus transfers to the peripheral once the channel is enabled. if the peripheral slave cannot accept these system bus transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. by using the handshaking interface, the peripheral can signal to the dmac that it is ready to transmit/receive data, and then the dmac can access the periph- eral without the peripheral inserting wait states onto the bus. 17.6 handshaking interface handshaking interfaces are used at the transactio n level to control the flow of single or burst transactions. the operation of the handshaking interface is different and depends on whether the peripheral or the dmac is the flow controller. the peripheral uses the handshaking interface to in dicate to the dmac that it is ready to trans- fer/accept data over the system bus. a non-memory peripheral can request a dma transfer through the dmac using one of two handshaking interfaces: ? hardware handshaking ? software handshaking software selects between the hardware or software handshaking interface on a per-channel basis. software handshaking is accomplished through memory-mapped registers, while hard- ware handshaking is accomplished usin g a dedicated handshaking interface. 17.6.1 software handshaking when the slave peripheral requires the dmac to perform a dma transaction, it communicates this request by sending an interrupt to the cpu or interrupt controller. the interrupt service routine then uses the software registers to initiate and control a dma trans- action. these software registers are used to implement the software handshaking interface. the hs_sel_src/hs_sel_dst bit in the cfgx channel configuration register must be set to enable software handshaking. when the peripheral is not the flow controller, then the last transaction registers lstsrcreg and lstdstreg are not used, and the values in these registers are ignored. 17.6.1.1 burst transactions writing a 1 to the reqsrcreg[x]/reqdstreg[x] register is always interpreted as a burst transac- tion request, where x is the channel number. however, in order for a burst transaction request to start, software must write a 1 to the sglreqsrcreg[x]/sglreqdstreg[x] register. you can write a 1 to the sglreqsrcreg[ x ]/sglreqdstreg[ x ] and reqsrcreg[ x ]/reqdstreg[ x ] registers in any order, but both registers must be asserted in order to initiate a burst transaction. upon completion of the burst transaction, the hardware clears the sglreqsrcreg[ x ]/sglreqd- streg[ x ] and reqsrcreg[ x ]/reqdstreg[ x ] registers.
177 32003e?avr32?05/06 at32ap7000 17.6.1.2 single transactions writing a 1 to the sg lreqsrcreg/sglreqdstreg initiates a single transaction. upon completion of the single transaction, both the sglreq srcreg/sglreqdstreg and reqsrcreg/reqdstreg bits are cleared by hardware. therefore, writ ing a 1 to the reqsrcreg/reqdstreg is ignored while a single transaction has been initiated, and the requested burst transaction is not serviced. again, writing a 1 to the reqsrcreg/reqdstre g register is always a burst transaction request. however, in order for a burst transaction request to start, the corresponding channel bit in the sglreqsrcreg/sglreqdstreg must be asserted. therefore, to ensure that a burst transaction is serviced, you must write a 1 to the reqsrcr eg/reqdstreg before writing a 1 to the sglreqsr- creg/sglreqdstreg register. software can poll the relevant channel bit in the sglreqsrcreg/ sglreqdstreg and reqsr- creg/reqdstreg registers. when both are 0, then either the requested burst or single transaction has completed. alternatively, the intsrctran or intdsttran interrupts can be enabled and unmasked in order to generate an interrupt when the requested source or destination trans- action has completed. note: the transaction-complete interrupts are trigger ed when both single and burst transactions are complete. the same transaction-complete interrupt is used for both single and burst transactions. 17.6.2 hardware handshaking there are 11 hardware handshaking interfaces between the dmac and peripherals. refer to the ?peripherals? chapter for the device-s pecific mapping of these interfaces. 17.6.2.1 external dma request definition when an external slave peripheral requires the dmac to perform dma transactions, it communi- cates its request by asserting the external ndmareqx signal. this signal is resynchronized to ensure a proper functionality (see ?external dma request timing? on page 178 ). the external ndmareqx is asserted when the s ource threshold level is reached. after resyn- chronization, the rising edge of dma_req starts the transfer. dma_req is de-asserted when dma_ack is asserted. the external ndmareqx signal must be de-ass erted after the last transfer and re-asserted again before a new transaction starts. for a source fifo, an active edge is triggered on ndmareqx when the source fifo exceeds a watermark level. for a destination fifo, an active edge is triggered on ndmareqx when the destination fifo drops below the watermark level. the source transaction length, ctlx.src_msize, and destination transaction length, ctlx.dest_msize, must be set according to watermark levels on the source/destination peripherals.
178 32003e?avr32?05/06 at32ap7000 figure 17-4. external dma request timing dma transfers dma transfers hclk ndmareqx dma_req dma_ack dma transfers dma transaction
179 32003e?avr32?05/06 at32ap7000 17.7 dmac transfer types a dma transfer may consist of single or multi-block transfers. on successive blocks of a multi- block transfer, the sarx/darx register in the dm ac is reprogrammed using either of the follow- ing methods: ? block chaining using linked lists ? auto-reloading ? contiguous address between blocks on successive blocks of a multi-block transfer, the ctlx register in the dmac is re-programmed using either of the following methods: ? block chaining using linked lists ? auto-reloading when block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the llpx register in the dmac is re-programmed using the following method: ? block chaining using linked lists a block descriptor (lli) consists of following registers, sarx, darx, llpx, ctlx, sstatx, dstatx. the first four registers, along with the cfgx register, are used by the dmac to set up and describe the block transfer. 17.7.1 multi-block transfers 17.7.1.1 block chaining using linked lists in this case, the dmac re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory. this is known as an lli update. dmac block chaining is supported by using a linked list pointer register (llpx) that stores the address in memory of the next linked list item. each lli (block descriptor) contains the corre- sponding block descriptor (sarx, darx, llpx, ctlx, sstatx, dstatx). to set up block chaining, a sequence of linked lists must be programmed in memory. the sarx, darx, llpx and ctlx registers are fetched from system memory on an lli update. the updated contents of the ctlx, sstatx, and dstatx registers are written back to memory on block completion. figure 17-5 on page 180 shows how to use chained linked lists in memory to define multi-block transfers using block chaining. the linked list multi-block transfers is initiated by programming llpx with llpx(0) (lli(0) base address) and ctlx with ctlx.llp_s_en and ctlx.llp_d_en.
180 32003e?avr32?05/06 at32ap7000 figure 17-5. multi-block transfer using linked lists system memory sarx darx llpx(1) ctlx[31..0] ctlx[63..32] write back for sstatx write back for dstatx sarx darx llpx(2) ctlx[31..0] ctlx[63..32] write back for sstatx write back for dstatx llpx(0) llpx(2) llpx(1) lli(0) lli(1)
181 32003e?avr32?05/06 at32ap7000 table 17-1. programming of transfer types and channel register update method (dmac state machine table) transfer type llp. loc = 0 llp_s_en ( ctlx) reload _sr ( cfgx) llp_d_en ( ctlx) reload_ ds ( cfgx) ctlx, llpx update method sarx update method darx update method write back 1) single block or last transfer of multi-block ye s 0 0 0 0 none, user reprograms none (single) none (single) no 2) autoreload multi-block transfer with contiguous sar ye s 0 0 0 1 ctlx,llpx are reloaded from initial values. contiguous auto- reload no 3) autoreload multi-block transfer with contiguous dar ye s 0 1 0 0 ctlx,llpx are reloaded from initial values. auto-reload con- tiguous no 4) autoreload multi-block transfer ye s 0 1 0 1 ctlx,llpx are reloaded from initial values. auto-reload auto- reload no 5) single block or last transfer of multi-block no 0 0 0 0 none, user reprograms none (single) none (single) ye s 6) linked list multi-block transfer with contiguous sar no 0 0 1 0 ctlx,llpx loaded from next linked list item contiguous linked list ye s 7) linked list multi-block transfer with auto-reload sar no 0 1 1 0 ctlx,llpx loaded from next linked list item auto-reload linked list ye s 8) linked list multi-block transfer with contiguous dar no 1 0 0 0 ctlx,llpx loaded from next linked list item linked list con- tiguous ye s 9) linked list multi-block transfer with auto-reload dar no 1 0 0 1 ctlx,llpx loaded from next linked list item linked list auto- reload ye s 10) linked list multi-block transfer no 1 0 1 0 ctlx,llpx loaded from next linked list item linked list linked list ye s
182 32003e?avr32?05/06 at32ap7000 17.7.1.2 auto-reloading of channel registers during auto-reloading, the channel registers are reloaded with their initial values at the comple- tion of each block and the new values used for the new block. depending on the row number in table 17-1 on page 181 , some or all of the sarx, darx and ctlx channel registers are reloaded from their initial value at the start of a block transfer. 17.7.1.3 contiguous address between blocks in this case, the address between successive bloc ks is selected to be a continuation from the end of the previous block. enabling the source or destination address to be contiguous between blocks is a function of ctlx.llp_s_en, cfgx.reloa d_sr, ctlx.llp_d_en, and cfgx.reload_ds registers (see figure 17-1 on page 181 ). note: both sarx and darx updates cannot be se lected to be contiguous. if this functionality is required, the size of the block tr ansfer (ctlx.block_ts) must be increased. if this is at the max- imum value, use row 10 of table 17-1 on page 181 and setup the lli.sarx address of the block descriptor to be equal to the end sarx address of the previous block. similarly, setup the lli.darx address of the block descriptor to be equal to the end darx address of the previous block. 17.7.1.4 suspension of transfers between blocks at the end of every block transfer, an end of block interrupt is asserted if: ? interrupts are enabled, ctlx.int_en = 1 ? the channel block interrupt is unmasked, maskblock[n] = 0, where n is the channel number. note: the block complete interrupt is generated at the completion of the block transfer to the destination. for rows 6, 8, and 10 of table 17-1 on page 181 , the dma transfer does not stall between block transfers. for example, at the end of block n, the dmac automatically proceeds to block n + 1. for rows 2, 3, 4, 7, and 9 of table 17-1 on page 181 (sarx and/or darx auto-reloaded between block transfers), the dma transfer automatically stalls after the end of block. interrupt is asserted if the end of block interrupt is enabled and unmasked. the dmac does not proceed to the next block transfer until a write to the block interrupt clear register, clearblock[n], is performed by software. this clears the channel block complete interrupt. for rows 2, 3, 4, 7, and 9 of table 17-1 on page 181 (sarx and/or darx auto-reloaded between block transfers), the dma transfer does not stall if either: ? interrupts are disabled, ctlx.int_en = 0, or ? the channel block interrupt is masked, maskblock[n] = 1, where n is the channel number. channel suspension between blocks is used to ensu re that the end of block isr (interrupt ser- vice routine) of the next-to-last block is serviced before the start of the final block commences. this ensures that the isr has cleared the cfgx.reload_sr and/or cfgx.reload_ds bits before completion of the final block. the reload bits cfgx.reload_sr and/or cfgx.reload_ds should be cleared in the ?end of block isr? for the next-to-last block transfer. 17.7.2 ending multi-block transfers all multi-block transfers must end as shown in either row 1 or row 5 of table 17-1 on page 181 . at the end of every block transfer, the dmac samples the row number, and if the dmac is in
183 32003e?avr32?05/06 at32ap7000 row 1 or row 5 state, then the previous block transferred was the last block and the dma trans- fer is terminated. note: row 1 and row 5 are used for single block transfers or terminating multiblock transfers. ending in row 5 state enables status fetch and writeback for the last block. ending in row 1 state disables status fetch and writeback for the last block. for rows 2,3 and 4 of table 17-1 on page 181 , (llpx = 0 and cfgx.reload_sr and/or cfgx.reload_ds is set), multi-block dma transfers continue until both the cfgx.reload_sr and cfgx.reload_ds registers are cleared by software. they should be programmed to zero in the end of block interrupt service routine that services the next-to-last block transfer. this puts the dmac into row 1 state. for rows 6, 8, and 10 (both cfgx.reload_sr and cfgx.reload_ds cleared) the user must setup the last block descriptor in memory such that both lli.ctlx.llp_s_en and lli.ctlx.llp_d_en are zero. if the lli.llpx register of the last block descriptor in memory is non-zero, then the dma transfer is terminated in row 5. if the lli.llpx register of the last block descriptor in memory is zero, then the dma transfer is terminated in row 1. for rows 7 and 9, the end-of-block interrupt serv ice routine that services the next-to-last block transfer should clear the cfgx.reload_sr and cfgx.reload_ds reload bits. the last block descriptor in memory should be set up so that both the lli.ctlx.llp_s_en and lli.ctlx.llp_d_en are zero. if the lli.llpx register of the last block descriptor in memory is non-zero, then the dma transfer is terminated in row 5. if the lli.llpx register of the last block descriptor in memory is zero, then the dma transfer is terminated in row 1. note: the only allowed transitions between the rows of table 17-1 on page 181 are from any row into row 1 or row 5. as already stated, a transition in to row 1 or row 5 is used to terminate the dma transfer. all other transitions between rows are not allowed. software must ensure that illegal tran- sitions between rows do not occur between blocks of a multi-block transfer. for example, if block n is in row 10 then the only allowed rows for block n + 1 are rows 10, 5 or 1. 17.8 programming a channel three registers, the llpx, the ctlx and cfgx, need to be programmed to set up whether single or multi-block transfers take place, and which type of multi-block transfer is used. the different transfer types are shown in table 17-1 on page 181 . the dmac can be programmed to fetch status from the source/destination peripheral. this sta- tus is stored in the sstatx and dstatx registers. when the dmac is programmed to fetch this status from the source/destination peripheral it writes this status and the contents of the ctlx register back to memory at the end of a block transfer. the ?write back? column of table 17-1 on page 181 shows when this occurs. the ?update method? column indicates where the values of sarx, darx, ctlx, and llpx are obtained for the next block transfer when multi-block dmac transfers are enabled. note: in table 17-1 on page 181 , all other combinations of ll px.loc = 0, ctlx.llp_s_en, cfgx.reload_sr, ctlx.llp_d_en, and cfgx.r eload_ds are illegal, and causes indeter- minate or erroneous behavior. 17.8.1 programming examples 17.8.1.1 single-block transfer (row 1) row 5 in table 17-1 on page 181 is also a single block transfer with writeback of control and sta- tus information enabled at the end of the single block transfer.
184 32003e?avr32?05/06 at32ap7000 1. read the channel enable register to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 3. program the following channel registers: a. write the starting source address in the sarx register for channel x. b. write the starting destination address in the darx register for channel x. c. program ctlx and cfgx according to row 1 as shown in table 17-1 on page 181 . program the llpx register with ?0?. d. write the control information for the dma transfer in the ctlx register for channel x. for example, in the register, you can program the following: ? i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the tt_fc of the ctlx register. ? ii. set up the transfer characteristics, such as: ? transfer width for the source in the src_tr_width field. ? transfer width for the destination in the dst_tr_width field. ? source master layer in the sms field where source resides. ? destination master layer in the dms field where destination resides. ? incrementing/decrementing or fixed address for source in sinc field. ? incrementing/decrementing or fixed address for destination in dinc field. e. write the channel configuration information into the cfgx register for channel x. ? i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests. writing a ?1? activates the software handshaking interface to handle source/destination requests. ? ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. f. if gather is enabled (ctlx.s_gath_en is enabled), program the sgrx register for channel x. g. if scatter is enabled (ctlx.d_scat_en, program the dsrx register for channel x. 4. after the dmac selected channel has been programmed, enable the channel by writing a ?1? to the chenreg.ch_en bit. make sure that bit 0 of the dmacfgreg register is enabled. 5. source and destination request single and burst dma transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges at the comple- tion of every transaction (burst and single) in the block and carry out the block transfer. 6. once the transfer completes, hardware sets the interrupts and disables the channel. at this time you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (chenreg.ch_en) bit until it is cleared by hardware, to detect when the transfer is complete.
185 32003e?avr32?05/06 at32ap7000 17.8.1.2 multi-block transfer with linked list for source and linked list for destination (row 10) 1. read the channel enable register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as block descriptors) in memory. write the control information in the lli.ctlx register location of the block descriptor for each lli in memory (see figure 17-5 on page 180 ) for channel x. for example, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the tt_fc of the ctlx register. b. set up the transfer characteristics, such as: ? i. transfer width for the source in the src_tr_width field. ? ii. transfer width for the destination in the dst_tr_width field. ? iii. source master layer in th e sms field where source resides. ? iv. destination master layer in the dms field where destination resides. ? v. incrementing/decrementing or fixed address for source in sinc field. ? vi. incrementing/decrementing or fixed address for destination dinc field. 3. write the channel configuration information into the cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination periph- eral. this requires programming the src_per and dest_per bits, respectively. 4. make sure that the lli.ctlx register locations of all lli entries in memory (except the last) are set as shown in row 10 of table 17-1 on page 181 . the lli.ctlx register of the last linked list item must be set as described in row 1 or row 5 of table 17-1 . fig- ure 17-7 on page 188 shows a linked list example with two list items. 5. make sure that the lli.llpx register locations of all lli entries in memory (except the last) are non-zero and point to the base address of the next linked list item. 6. make sure that the lli.sarx/lli.darx register locations of all lli entries in memory point to the start source/destination block address preceding that lli fetch. 7. make sure that the lli.ctlx.done field of the lli.ctlx register locations of all lli entries in memory are cleared. 8. if source status fetching is enabled (cfgx.ss_upd_en is enabled), program the sstatarx register so that the source status information can be fetched from the loca- tion pointed to by the sstatarx. for conditions under which the source status information is fetched from system memory, refer to the ?writeback? column of table 17- 1 on page 181 . 9. if destination status fetching is enabled (cfgx.ds_upd_en is enabled), program the dstatarx register so that the destination status information can be fetched from the location pointed to by the dstatarx register. for conditions under which the destina- tion status information is fetched from system memory, refer to the ?writeback? column of table 17-1 on page 181 . 10. if gather is enabled (ctlx.s_gath_en is enabled), program the sgrx register for channel x.
186 32003e?avr32?05/06 at32ap7000 11. if scatter is enabled (ctlx.d_scat_en is enabled), program the dsrx register for channel x. 12. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 13. program the ctlx, cfgx registers according to row 10 as shown in table 17-1 on page 181 . 14. program the llpx register with llpx(0), the pointer to the first linked list item. 15. finally, enable the channel by writing a ?1? to the chenreg.ch_en bit. the transfer is performed. 16. the dmac fetches the first lli from the location pointed to by llpx(0). note: the lli.sarx, lli. darx, lli.llpx and lli.ct lx registers are fetched. the dmac automatically reprograms the sarx, darx, llpx and ctlx channel registers from the llpx(0). 17. source and destination request single and burst dma transactions to transfer the block of data (assuming non-memory peripheral). the dmac acknowledges at the comple- tion of every transaction (burst and single) in the block and carry out the block transfer. 18. once the block of data is transferred, the source status information is fetched from the location pointed to by the sstatarx register and stored in the sstatx register if cfgx.ss_upd_en is enabled. for conditions under which the source status informa- tion is fetched from system memory, re fer to the ?writeback? column of table 17-1 on page 181 . the destination status information is fetched from the location pointed to by the dsta- tarx register and stored in the dstatx register if cfgx.ds_upd_en is enabled. for conditions under which the destination status information is fetched from system mem- ory, refer to ?writeback? column of table 17-1 on page 181 . 19. the ctlxh register is written out to system memory. for conditions under which the ctlxh register is written out to system memory, refer to ?writeback? column of table 17-1 on page 181 . the ctlxh register is written out to the same location on the same layer (llpx.lms) where it was originally fetc hed; that is, the location of the ctlx regis- ter of the linked list item fetched prior to the start of the block transfer. only the second word of the ctlx register is written out, ctlxh, because only the ctlx.block_ts and ctlx.done fields have been updated by dmac hardware. additionally, the ctlx.done bit is asserted to indicate block completion. therefore, software can poll the lli.ctlx.done bit of the ctlx register in the lli to ascertain when a block trans- fer has completed. note: do not poll the ctlx.done bit in the dmac memo ry map. instead, poll the lli.ctlx.done bit in the lli for that block. if the polled lli.ctlx.done bit is asserted, then this block transfer has completed. this lli.ctlx.done bit was cleared at the start of the transfer (step 7). 20. the sstatx register is now written out to system memory if cfgx.ss_upd_en is enabled. it is written to the sstatx register location of the lli pointed to by the previ- ously saved llpx.loc register. the dstatx register is now written out to system memory if cfgx.ds_upd_en is enabled. it is written to the dstatx register location of the lli pointed to by the previ- ously saved llpx.loc register. the end of block interrupt, int_block, is generated after the write back of the control and status registers has completed. note: the writeback location for the control and status registers is the lli pointed to by the previous value of the llpx.loc register, not the lli poi nted to by the current value of the llpx.loc register. 21. the dmac does not wait for the block interrupt to be cleared, but continues fetching the next lli from the memory location pointed to by current llpx register and automatically
187 32003e?avr32?05/06 at32ap7000 reprograms the sarx, darx, llpx and ctlx channel registers. the dma transfer con- tinues until the dmac determines that the ctlx and llpx registers at the end of a block transfer match that described in row 1 or row 5 of table 17-1 on page 181 . the dmac then knows that the previous block transferred was the last block in the dma transfer. the dma transfer might look like that shown in figure 17-6 on page 187 . figure 17-6. multi-block with linked list address for source and destination if the user needs to execute a dma transfer wh ere the source and destination address are con- tiguous but the amount of data to be transferred is greater than the maximum block size ctlx.block_ts, then this can be achieved usin g the type of multi-block transfer as shown in figure 17-7 on page 188 . sar(2) sar(1) sar(0) dar(2) dar(1) dar(0) block 2 block 1 block 0 block 0 block 1 block 2 address of source layer address of destination layer source blocks destination blocks
188 32003e?avr32?05/06 at32ap7000 figure 17-7. multi-block with linked address for source and destination blocks are contiguous the dma transfer flow is shown in figure 17-8 on page 189 . sar(2) sar(1) sar(0) dar(2) dar(1) dar(0) block 2 block 1 block 0 block 0 block 1 block 2 address of source layer address of destination layer source blocks destination blocks sar(3) block 2 dar(3) block 2
189 32003e?avr32?05/06 at32ap7000 figure 17-8. dma transfer flow for source and destination linked list address channel enabled by software lli fetch hardware reprograms sarx, darx, ctlx, llpx dmac block transfer source/destination status fetch writeback of control and source/destination status of lli is dmac in row1 or row5 of dmac state machine table? channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no
190 32003e?avr32?05/06 at32ap7000 17.8.1.3 dma transfer flow for source and destination linked list address multi-block transfer with source address auto-reloaded and destination address auto-reloaded (row 4) 1. read the channel enable register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 3. program the following channel registers: a. write the starting source address in the sarx register for channel x. b. write the starting destination address in the darx register for channel x. c. program ctlx and cfgx according to row 4 as shown in table 17-1 on page 181 . program the llpx register with ?0?. d. write the control information for the dma transfer in the ctlx register for channel x. for example, in the register, you can program the following: ? i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the tt_fc of the ctlx register. ? ii. set up the transfer characteristics, such as: ? transfer width for the source in the src_tr_width field. ? transfer width for the destination in the dst_tr_width field. ? source master layer in the sms field where source resides. ? destination master layer in the dms field where destination resides. ? incrementing/decrementing or fixed address for source in sinc field. ? incrementing/decrementing or fixed address for destination in dinc field. e. if gather is enabled (ctlx.s_gath_en is enabled), program the sgrx register for channel x. f. if scatter is enabled (ctlx.d_scat_en), program the dsrx register for channel x. g. write the channel configuration information into the cfgx register for channel x. ensure that the reload bits, cfgx. reload_sr and cfgx.reload_ds are enabled. ? i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. ? ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. 4. after the dmac selected channel has been programmed, enable the channel by writing a ?1? to the chenreg.ch_en bit. make sure that bit 0 of the dmacfgreg register is enabled. 5. source and destination request single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges on com- pletion of each burst/single transaction and carry out the block transfer.
191 32003e?avr32?05/06 at32ap7000 6. when the block transfer has completed, the dmac reloads the sarx, darx and ctlx registers. hardware sets the block comple te interrupt. the dmac then samples the row number as shown in table 17-1 on page 181 . if the dmac is in row 1, then the dma transfer has completed. hardware sets the transfer complete interrupt and dis- ables the channel. so you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (chenreg.ch_en) bit until it is dis- abled, to detect when the transfer is complete. if the dmac is not in row 1, the next step is performed. 7. the dma transfer proceeds as follows: a. if interrupts are enabled (ctlx.int_en = 1) and the block complete interrupt is un- masked (maskblock[x] = 1?b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. it then stalls until the block complete interrupt is cleared by software. if the next block is to be the last block in the dma transfer, then the block complete isr (interrupt service routine) should clear the reload bits in the cfgx.reload_sr and cfgx.reload_ds registers. this put the dmac into row 1 as shown in table 17-1 on page 181 . if the next block is not the last block in the dma transfer, then the reload bits should remain enabled to keep the dmac in row 4. b. if interrupts are disabled (ctlx.int_en = 0) or the block complete interrupt is masked (maskblock[x] = 1?b0, where x is the channel number), then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. in this case software must clear the reload bits in the cfgx.reload_sr and cfgx.reload_ds registers to put the dmac into row 1 of table 17-1 on page 181 before the last block of the dma transfer has completed. the transfer is similar to that shown in figure 17-9 on page 191 . the dma transfer flow is shown in figure 17-10 on page 192 . figure 17-9. multi-block dma transfer with source and destination address auto-reloaded address of source layer address of destination layer source blocks destination blocks blockn block2 block1 block0 sar dar
192 32003e?avr32?05/06 at32ap7000 figure 17-10. dma transfer flow for source and destination address auto-reloaded 17.8.1.4 multi-block transfer with source address auto-reloaded and linked list destination address (row7) 1. read the channel enable register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as block descriptors) in memory. write the control information in the lli.ctlx register location of the block descriptor for each lli in memory for channel x. for example, in the register you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control peripheral by programming the tt_fc of the ctlx register. b. set up the transfer characteristics, such as: ? i. transfer width for the source in the src_tr_width field. ? ii. transfer width for the destination in the dst_tr_width field. ? iii. source master layer in th e sms field where source resides. ? iv. destination master layer in the dms field where destination resides. ? v. incrementing/decrementing or fixed address for source in sinc field. ? vi. incrementing/decrementing or fixed address for destination dinc field. channel enabled by software block transfer reload sarx, darx, ctlx channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no yes stall until block complete interrupt cleared by software ctlx.int_en=1 && maskblock[x]=1? no is dmac in row1 of dmac state machine table?
193 32003e?avr32?05/06 at32ap7000 3. write the starting source address in the sarx register for channel x. note: the values in the lli.sarx register locations of each of the linked list items (llis) setup up in memory, although fetched during a lli fetch, are not used. 4. write the channel configuration information into the cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. 5. make sure that the lli.ctlx register locations of all llis in memory (except the last) are set as shown in row 7 of table 17-1 on page 181 while the lli.ctlx register of the last linked list item must be set as described in row 1 or row 5 of table 17-1 . figure 17-5 on page 180 shows a linked list example with two list items. 6. make sure that the lli.llpx register locations of all llis in memory (except the last) are non-zero and point to the next linked list item. 7. make sure that the lli.darx register location of all llis in memory point to the start destination block address proceeding that lli fetch. 8. make sure that the lli.ctlx.done field of the lli.ctlx register locations of all llis in memory is cleared. 9. if source status fetching is enabled (cfgx.ss_upd_en is enabled), program the sstatarx register so that the source status information can be fetched from the loca- tion pointed to by the sstatarx. for conditions under which the source status information is fetched from system memory, refer to the ?writeback? column of table 17- 1 on page 181 . 10. if destination status fetching is enabled (cfgx.ds_upd_en is enabled), program the dstatarx register so that the destination status information can be fetched from the location pointed to by the dstatarx register. for conditions under which the destina- tion status information is fetched from system memory, refer to the ?writeback? column of table 17-1 on page 181 . 11. if gather is enabled (ctlx.s_gath_en is enabled), program the sgrx register for channel x. 12. if scatter is enabled (ctlx.d_scat_en is enabled), program the dsrx register for channel x. 13. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 14. program the ctlx, cfgx registers according to row 7 as shown in table 17-1 on page 181 . 15. program the llpx register with llpx(0), the pointer to the first linked list item. 16. finally, enable the channel by writing a ?1? to the chenreg.ch_en bit. the transfer is performed. make sure that bit 0 of the dmacfgreg register is enabled. 17. the dmac fetches the first lli from the location pointed to by llpx(0). note: the lli.sarx, lli.darx, lli. llpx and lli.ct lx registers are fetched. the lli.sarx register although fetched is not used.
194 32003e?avr32?05/06 at32ap7000 18. source and destination request single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). dmac acknowledges at the com- pletion of every transaction (burst and single) in the block and carry out the block transfer. 19. once the block of data is transferred, the source status information is fetched from the location pointed to by the sstatarx register and stored in the sstatx register cfgx.ss_upd_en is enabled. for conditions under which the source status informa- tion is fetched from system memory, re fer to the ?writeback? column of table 17-1 on page 181 . the destination status information is fetched from the location pointed to by the dsta- tarx register and stored in the dstatx register if cfgx.ds_upd_en is enabled. for conditions under which the destination status information is fetched from system mem- ory, refer to ?writeback? column of table 17-1 on page 181 . 20. the ctlxh register is written out to system memory. for conditions under which the ctlxh register is written out to system memory, refer to ?writeback? column of table 17-1 on page 181 . the ctlxh register is written out to the same location on the same layer (llpx.lms) where it was originally fetched, that is the location of the ctlx regis- ter of the linked list item fetched prior to the start of the block transfer. only the second word of the ctlx register is written out, ctlxh, because only the ctlx.block_ts and ctlx.done fields have been updated by hardware within the dmac. the lli.ctlx.done bit is asserted to indicate block completion. therefore, software can poll the lli.ctlx.done bit field of the ctlx register in the lli to ascertain when a block transfer has completed. note: do not poll the ctlx.done bit in the dmac me mory map. instead poll the lli.ctlx.done bit in the lli for that block. if the polled lli.ctlx.done bit is asserted, then this block transfer has completed. this lli.ctlx.done bit was cleared at the start of the transfer (step 8). 21. the sstatx register is now written out to system memory if cfgx.ss_upd_en is enabled. it is written to the sstatx register location of the lli pointed to by the previ- ously saved llpx.loc register. the dstatx register is now written out to system memory if cfgx.ds_upd_en is enabled. it is written to the dstatx register location of the lli pointed to by the previ- ously saved llpx.loc register. the end of block interrupt, int_block, is generated after the writeback of the control and status registers has completed. note: the writeback location for the control and status registers is the lli pointed to by the previous value of the llpx.loc register, not the lli poi nted to by the current value of the llpx.loc register. 22. the dmac reloads the sarx register from the initial value. hardware sets the block complete interrupt. the dmac samples the row number as shown in table 17-1 on page 181 . if the dmac is in row 1 or 5, then the dma transfer has completed. hard- ware sets the transfer complete interrupt and disables the channel. you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (chenreg.ch_en) bit until it is cleared by hardware, to detect when the trans- fer is complete. if the dmac is not in row 1 or 5 as shown in table 17-1 on page 181 the following steps are performed. 23. the dma transfer proceeds as follows: a. if interrupts are enabled (ctlx.int_en = 1) and the block complete interrupt is un- masked (maskblock[x] = 1?b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. it then stalls until the block complete interrupt is cleared by software. if the next block is to be the last block in the dma transfer, then the block complete isr (interrupt service routine) should clear the cfgx.reload_sr source reload bit. this puts the dmac into
195 32003e?avr32?05/06 at32ap7000 row1 as shown in table 17-1 on page 181 . if the next block is not the last block in the dma transfer, then the source reload bit should remain enabled to keep the dmac in row 7 as shown in table 17-1 on page 181 . b. if interrupts are disabled (ctlx.int_en = 0) or the block complete interrupt is masked (maskblock[x] = 1?b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. in this case, software must clear the source reload bit, cfgx.reload_sr, to put the device into row 1 of table 17-1 on page 181 before the last block of the dma transfer has completed. 24. the dmac fetches the next lli from memory location pointed to by the current llpx register, and automatically reprograms the darx, ctlx and llpx channel registers. note that the sarx is not re-programmed as the reloaded value is used for the next dma block transfer. if the next block is the last block of the dma transfer then the ctlx and llpx registers just fetched from the lli should match row 1 or row 5 of table 17- 1 on page 181 . the dma transfer might look like that shown in figure 17-11 on page 195 . figure 17-11. multi-block dma transfer with source address auto-reloaded and linked list destination address the dma transfer flow is shown in figure 17-12 on page 196 address of source layer address of destination layer source blocks destination blocks sar block0 block1 block2 blockn dar(n) dar(1) dar(0) dar(2)
196 32003e?avr32?05/06 at32ap7000 figure 17-12. dma transfer flow for source address auto-reloaded and linked list destina- tion address channel enabled by software lli fetch yes no no yes hardware reprograms darx, ctlx, llpx dmac block transfer source/destination status fetch writeback of control and source/destination status of lli reload sarx block complete interrupt generated here dmac transfer complete interrupt generated here channel disabled by hardware ctlx.int_en=1 && maskblock[x]=1 ? stall until block interrupt cleared by hardware is dmac in row1 or row5 of dmac state machine table?
197 32003e?avr32?05/06 at32ap7000 17.8.1.5 multi-block transfer with source address auto-reloaded and contiguous destination address (row 3) 1. read the channel enable register to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 3. program the following channel registers: a. write the starting source address in the sarx register for channel x. b. write the starting destination address in the darx register for channel x. c. program ctlx and cfgx according to row 3 as shown in table 17-1 on page 181 . program the llpx register with ?0?. d. write the control information for the dma transfer in the ctlx register for channel x. for example, in this register, you can program the following: ? i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the tt_fc of the ctlx register. ? ii. set up the transfer characteristics, such as: ? transfer width for the source in the src_tr_width field. ? transfer width for the destination in the dst_tr_width field. ? source master layer in the sms field where source resides. ? destination master layer in the dms field where destination resides. ? incrementing/decrementing or fixed address for source in sinc field. ? incrementing/decrementing or fixed address for destination in dinc field. e. if gather is enabled (ctlx.s_gath_en is enabled), program the sgrx register for channel x. f. if scatter is enabled (ctlx.d_scat_en), program the dsrx register for channel x. g. write the channel configuration information into the cfgx register for channel x. ? i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. ? ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dest_per bits, respectively. 4. after the dmac channel has been programmed, enable the channel by writing a ?1? to the chenreg.ch_en bit. make sure that bit 0 of the dmacfgreg register is enabled. 5. source and destination request single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (burst and single) in the block and carries out the block transfer. 6. when the block transfer has completed, the dmac reloads the sarx register. the darx register remains unchanged. hardware sets the block complete interrupt. the dmac then samples the row number as shown in table 17-1 on page 181 . if the dmac is in row 1, then the dma transfer has completed. hardware sets the transfer complete
198 32003e?avr32?05/06 at32ap7000 interrupt and disables the channel. so you can either respond to the block complete or transfer complete interrupts, or poll for the channel enable (chenreg.ch_en) bit until it is cleared by hardware, to detect when the transfer is complete. if the dmac is not in row 1, the next step is performed. 7. the dma transfer proceeds as follows: a. if interrupts are enabled (ctlx.int_en = 1) and the block complete interrupt is un- masked (maskblock[x] = 1?b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. it then stalls until the block complete interrupt is cleared by software. if the next block is to be the last block in the dma transfer, then the block complete isr (interrupt service routine) should clear the source reload bit, cfgx.reload_sr. this puts the dmac into row1 as shown in table 17-1 on page 181 . if the next block is not the last block in the dma transfer then the source reload bit should remain enabled to keep the dmac in row3 as shown in table 17-1 on page 181 . b. if interrupts are disabled (ctlx.int_en = 0) or the block complete interrupt is masked (maskblock[x] = 1?b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. in this case software must clear the source reload bit, cfgx.reload_sr, to put the device into row 1 of table 17-1 on page 181 before the last block of the dma transfer has completed. the transfer is similar to that shown in figure 17-13 on page 198 . the dma transfer flow is shown in figure 17-14 on page 199 . figure 17-13. multi-block transfer with source address auto-reloaded and contiguous desti- nation address address of source layer address of destination layer source blocks destination blocks sar block0 block1 block2 dar(1) dar(0) dar(2)
199 32003e?avr32?05/06 at32ap7000 figure 17-14. dma transfer for source address auto-reloaded and contiguous destination address 17.8.1.6 multi-block dma transfer with linked list for source and contiguous destination address (row 8) 1. read the channel enable register to choose a free (disabled) channel. 2. set up the linked list in memory. write the control information in the lli. ctlx register location of the block descriptor for each lli in memory for channel x. for example, in the register, you can program the following: a. set up the transfer type (memory or non-memory peripheral for source and desti- nation) and flow control device by programming the tt_fc of the ctlx register. b. set up the transfer characteristics, such as: ? i. transfer width for the source in the src_tr_width field. ? ii. transfer width for the destination in the dst_tr_width field. ? iii. source master layer in th e sms field where source resides. ? iv. destination master layer in the dms field where destination resides. channel enabled by software block transfer reload sarx, ctlx channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no no yes stall until block complete interrupt cleared by software ctlx.int_en=1 && maskblock[x]=1? is dmac in row1 of dmac state machine table?
200 32003e?avr32?05/06 at32ap7000 ? v. incrementing/decrementing or fixed address for source in sinc field. ? vi. incrementing/decrementing or fixed address for destination dinc field. 3. write the starting destination address in the darx register for channel x. note: the values in the lli.darx register location of each linked list item (lli) in memory, although fetched during an lli fetch, are not used. 4. write the channel configuration information into the cfgx register for channel x. a. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires pro- gramming the hs_sel_src/hs_sel_dst bits, respectively. writing a ?0? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?1? activates the software handshaking interface to handle source/destination requests. b. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripherals. this requires programming the src_per and dest_per bits, respectively. 5. make sure that all lli.ctlx register locations of the lli (except the last) are set as shown in row 8 of table 17-1 on page 181 , while the lli.ctlx register of the last linked list item must be set as described in row 1 or row 5 of table 17-1 . figure 17-5 on page 180 shows a linked list example with two list items. 6. make sure that the lli.llpx register locations of all llis in memory (except the last) are non-zero and point to the next linked list item. 7. make sure that the lli.sarx register location of all llis in memory point to the start source block address proceeding that lli fetch. 8. make sure that the lli.ctlx.done field of the lli.ctlx register locations of all llis in memory is cleared. 9. if source status fetching is enabled (cfgx.ss_upd_en is enabled), program the sstatarx register so that the source status information can be fetched from the loca- tion pointed to by sstatarx. for conditions under which the source status information is fetched from system memory, refer to the ?writeback? column of table 17-1 on page 181 . 10. if destination status fetching is enabled (cfgx.ds_upd_en is enabled), program the dstatarx register so that the destination status information can be fetched from the location pointed to by the dstatarx register. for conditions under which the destina- tion status information is fetched from system memory, refer to the ?writeback? column of table 17-1 on page 181 . 11. if gather is enabled (ctlx.s_gath_en is enabled), program the sgrx register for channel x. 12. if scatter is enabled (ctlx.d_scat_en is enabled), program the dsrx register for channel x. 13. clear any pending interrupts on the channel from the previous dma transfer by writing to the interrupt clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. reading the interrupt raw status and interrupt status registers confirms that all interrupts have been cleared. 14. program the ctlx, cfgx registers according to row 8 as shown in table 17-1 on page 181 15. program the llpx register with llpx(0), the pointer to the first linked list item. 16. finally, enable the channel by writing a ?1? to the chenreg.ch_en bit. the transfer is performed. make sure that bit 0 of the dmacfgreg register is enabled.
201 32003e?avr32?05/06 at32ap7000 17. the dmac fetches the first lli from the location pointed to by llpx(0). note: the lli.sarx, lli.darx, lli.llpx and lli.ct lx registers are fetched . the lli.darx register location of the lli although fetched is not us ed. the darx register in the dmac remains unchanged. 18. source and destination requests single and burst dmac transactions to transfer the block of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. 19. once the block of data is transferred, the source status information is fetched from the location pointed to by the sstatarx register and stored in the sstatx register if cfgx.ss_upd_en is enabled. for conditions under which the source status informa- tion is fetched from system memory, re fer to the ?writeback? column of table 17-1 on page 181 . the destination status information is fetched from the location pointed to by the dstatarx register and stored in the dstatx register if cfgx.ds_upd_en is enabled. for conditions under which the destination status information is fetched from system memory, refer to ?writeback? column of table 17-1 on page 181 . 20. the ctlxh register is written out to system memory. for conditions under which the ctlxh register is written out to system memory, refer to ?writeback? column of table 17-1 on page 181 . the ctlxh register is written out to the same location on the same layer (llpx.lms) where it was originally fetched, that is the location of the ctlx regis- ter of the linked list item fetched prior to the start of the block transfer. only the second word of the ctlx register is written out, ctlxh, because only the ctlx.block_ts and ctlx.done fields have been updated by hardware within the dmac. additionally, the ctlx.done bit is asserted to indicate block completion. therefore, software can poll the lli.ctlx.done bit field of the ctlx register in the lli to ascertain when a block transfer has completed. note: do not poll the ctlx.done bit in the dmac me mory map. instead poll the lli.ctlx.done bit in the lli for that block. if the polled lli.ctlx.done bit is asserted, then this block transfer has completed. this lli.ctlx.done bit was cleared at the start of the transfer (step 8). 21. the sstatx register is now written out to system memory if cfgx.ss_upd_en is enabled. it is written to the sstatx register location of the lli pointed to by the previ- ously saved llpx.loc register. the dstatx register is now written out to system memory if cfgx.ds_upd_en is enabled. it is written to the dstatx register location of the lli pointed to by the previ- ously saved llpx.loc register. the end of block interrupt, int_block, is generated after the write back of the control and status registers has completed. note: the writeback location for the control and status registers is the lli pointed to by the previous value of the llpx.loc register, not the lli poi nted to by the current value of the llpx.loc register. 22. the dmac does not wait for the block interrupt to be cleared, but continues and fetches the next lli from the memory location pointed to by current llpx register and automat- ically reprograms the sarx, ctlx and llpx channel registers. the darx register is left unchanged. the dma transfer continues until the dmac samples the ctlx and llpx registers at the end of a block transfer match that described in row 1 or row 5 of table 17-1 on page 181 . the dmac then knows that the previous block transferred was the last block in the dma transfer. the dmac transfer might look like that shown in figure 17-15 on page 202 note that the desti- nation address is decrementing.
202 32003e?avr32?05/06 at32ap7000 figure 17-15. dma transfer with linked list source address and contiguous destination address the dma transfer flow is shown in figure 17-16 on page 203 . sar(2) sar(1) sar(0) dar(2) dar(1) dar(0) block 2 block 1 block 0 block 0 block 1 block 2 address of source layer address of destination layer source blocks destination blocks
203 32003e?avr32?05/06 at32ap7000 figure 17-16. dma transfer flow for source address auto-reloaded and contiguous destina- tion address channel enabled by software lli fetch hardware reprograms sarx, ctlx, llpx dmac block transfer source/destination status fetch writeback of control and source/destination status of lli is dmac in row 1 or row 5 of table 4 ? channel disabled by hardware block complete interrupt generated here dmac transfer complete interrupt generated here yes no
204 32003e?avr32?05/06 at32ap7000 17.9 disabling a channel prio r to transfer completion under normal operation, software enables a channel by writing a ?1? to the channel enable reg- ister, chenreg.ch_en, and hardware disables a ch annel on transfer completion by clearing the chenreg.ch_en register bit. the recommended way for software to disable a channel without losing data is to use the ch_susp bit in conjunction with the fifo_empty bit in the channel configuration register (cfgx) register. 1. if software wishes to disable a channel prior to the dma transfer completion, then it can set the cfgx.ch_susp bit to tell the dmac to halt all transfers from the source peripheral. therefore, the channel fifo receives no new data. 2. software can now poll the cfgx.fifo_empty bit until it indicates that the channel fifo is empty. 3. the chenreg.ch_en bit can then be cleared by software once the channel fifo is empty. when ctlx.src_tr_width is less than ct lx.dst_tr_width and the cfgx.ch_susp bit is high, the cfgx.fifo_empty is asserted once the contents of the fifo do not permit a single word of ctlx.dst_tr_width to be formed. however, there may still be data in the channel fifo but not enough to form a single transfer of ctlx.dst_tr_width width. in this configura- tion, once the channel is disabled, the remaining data in the channel fifo are not transferred to the destination peripheral. it is permitted to remove the channel from the suspension state by writing a ?0? to the cfgx.ch_su sp register. the dma transfer completes in the normal manner. note: if a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement. 17.9.1 abnormal transfer termination a dmac dma transfer may be terminated abruptly by software by clearing the channel enable bit, chenreg.ch_en. this does not mean that th e channel is disabled immediately after the chenreg.ch_en bit is cleared over the ahb slave interface. consider this as a request to dis- able the channel. the chenreg.ch_en must be polled and then it must be confirmed that the channel is disabled by reading back 0. a case where the channel is not be disabled after a chan- nel disable request is where either the source or destination has received a split or retry response. the dmac must keep re -attempting the transfer to th e system haddr that originally received the split or re try response until an okay response is returned. to do otherwise is an system bus protocol violation. software may terminate all channels abruptly by clearing the global enable bit in the dmac con- figuration register (dmacfgreg[0]). again, this does not mean that all channels are disabled immediately after the dmacfgreg[0] is cleared over the ahb slave interface. consider this as a request to disable all channels. the chenreg must be polled and then it must be confirmed that all channels are disabled by reading back ?0?. note: if the channel enable bit is cleared while there is data in the channel fifo, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. for read sensitive source peripherals such as a sour ce fifo this data is therefor e lost. when the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel fifo to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. note: if a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement.
205 32003e?avr32?05/06 at32ap7000 17.10 dma controller (d mac) user interface table 17-2. dma controller (dmac) user interface offset register register name access reset value 0x0 channel 0 source address register sar0 read/write 0x0 0x4 reserved - 0x8 channel 0 destination address register dar0 read/write 0x0 0xc reserved - 0x10 channel 0 linked list pointer register llp0 read/write 0x0 0x14 reserved - 0x18 channel 0 control register low ctl0l read/write 0x1c channel 0 control register high ctl0h read/write 0x20 channel 0 source status register sstat0 read/write 0x0 0x24 reserved 0x28 channel 0 destination status register dstat0 read/write 0x0 0x2c reserved 0x30 channel 0 source status address register sstatar0 read/write 0x0 0x34 reserved 0x38 channel 0 destination status address register dstatar0 read/write 0x0 0x3c reserved 0x40 channel 0 configuration register low cfg0l read/write 0x00000c00 0x44 channel 0 configuration register high cfg0h read/write 0x00000004 0x48 channel 0 source gather register sgr0 read/write 0x0 0x4c reserved 0x50 channel 0 destination scatter register dsr0 read/write 0x0 0x54 reserved 0x58 channel 1 source address register sar1 read/write 0x0 0x5c reserved 0x60 channel 1 destination address register dar1 read/write 0x0 0x64 reserved 0x68 channel 1 linked list pointer register llp1 read/write 0x0 0x7c reserved 0x70 channel 1 control register low ctl1l read/write 0x74 channel 1 control register high ctl1h read/write 0x78 channel 1 source status register sstat1 read/write 0x0 0x7c reserved 0x80 channel 1 destination status register dstat1 read/write 0x0 0x84 reserved 0x88 channel 1 source status address register sstatar1 read/write 0x0
206 32003e?avr32?05/06 at32ap7000 0x8c reserved 0x90 channel 1 destination status address register dstatar1 read/write 0x0 0x94 reserved 0x98 channel 1 configuration register low cfg1l read/write 0x00000c20 0x9c channel 1 configuration register high cfg1h read/write 0x00000004 0xa0 channel 1 source gather register sgr1 read/write 0x0 0xa4 reserved 0xa8 channel 1 destination scatter register dsr1 read/write 0x0 0xac channel 0 source address register sar0 read/write 0x0 0xb0 reserved - 0xb4 channel 0 destination address register dar0 read/write 0x0 0xb8 reserved - 0xbc channel 0 linked list pointer register llp0 read/write 0x0 0xc0 reserved - 0xc4 channel 0 control register low ctl0l read/write 0xc8 channel 0 control register high ctl0h read/write 0xcc channel 0 source status register sstat0 read/write 0x0 0xd0 reserved 0xd4 channel 0 destination status register dstat0 read/write 0x0 0xd8 reserved 0xdc channel 0 source status address register sstatar0 read/write 0x0 0xe0 reserved 0xe4 channel 0 destination status address register dstatar0 read/write 0x0 0xe8 reserved 0xec channel 0 configuration register low cfg0l read/write 0x00000c00 0xf0 channel 0 configuration register high cfg0h read/write 0x00000004 0xf4 channel 0 source gather register sgr0 read/write 0x0 0xf8 reserved 0xfc channel 0 destination scatter register dsr0 read/write 0x0 0x100..0x2b c reserved 0x2c0 raw status for inttfr interrupt rawtfr read 0x0 0x2c4 reserved 0x2c8 raw status for intblock interrupt rawblock read 0x0 0x2cc reserved 0x2d0 raw status for intsrctran interrupt rawsrctran read 0x0 table 17-2. dma controller (dmac) user interface (continued) offset register register name access reset value
207 32003e?avr32?05/06 at32ap7000 0x2d4 reserved 0x2d8 raw status for intdsttran interrupt rawdsttran read 0x0 0x2dc reserved 0x2e0 raw status for interr interrupt rawerr read 0x0 0x2e4 reserved 0x2e8 status for inttfr interrupt statustfr read 0x0 0x2ec reserved 0x2f0 status for intblock interrupt statusblock read 0x0 0x2f4 reserved 0x2f8 status for intsrctran interrupt statussrctran read 0x0 0x2fc reserved 0x300 status for intdsttran interrupt statusdsttran read 0x0 0x304 reserved 0x308 status for interr interrupt statuserr read 0x0 0x30c reserved 0x310 mask for inttfr interrupt masktfr read/write 0x0 0x314 reserved 0x318 mask for intblock interrupt maskblock read/write 0x0 0x31c reserved 0x320 mask for intsrctran interrupt masksrctran read/write 0x0 0x324 reserved 0x328 mask for intdsttran interrupt maskdsttran read/write 0x0 0x32c reserved 0x330 mask for interr interrupt maskerr read/write 0x0 0x334 reserved 0x338 clear for inttfr interrupt cleartfr write 0x0 0x33c reserved 0x340 clear for intblock interrupt clearblock write 0x0 0x344 reserved 0x348 clear for intsrctran interrupt clearsrctran write 0x0 0x34c reserved 0x350 clear for intdsttran interrupt cleardsttran write 0x0 0x354 reserved 0x358 clear for interr interrupt clearerr write 0x0 0x35c reserved 0x360 status for each interr upt type statusint read 0x0 table 17-2. dma controller (dmac) user interface (continued) offset register register name access reset value
208 32003e?avr32?05/06 at32ap7000 0x364 reserved 0x368 source software transaction re quest register reqsrcreg read/write 0x0 0x36c reserved 0x370 destination software transaction request register reqdstreg read/write 0x0 0x374 reserved 0x378 single source transaction request register sglreqsrcreg read/write 0x0 0x37c reserved 0x380 single destination transaction req uest register sglreqdstreg read/write 0x0 0x384 reserved 0x388 last source transaction req uest register lstsrcreg read/write 0x0 0x38c reserved 0x390 last destination transaction r equest register lstdstreg read/write 0x0 0x394 reserved 0x398 dma configuration register dmacfgreg read/write 0x0 0x39c reserved 0x3a0 channel enable register chenreg read/write 0x0 0x3a4 reserved 0x3a8 dma id register idreg read dma_id_num 0x3ac reserved 0x3b0 dma test register dmatestreg read/write 0x3b4 reserved 0x3b8 reserved 0x3b8 reserved table 17-2. dma controller (dmac) user interface (continued) offset register register name access reset value
209 32003e?avr32?05/06 at32ap7000 17.10.1 channel x source address register name: sarx access: read/write reset: 0x0 the address offset for each channel is: [x *0x58] for example, sar0: 0x000, sar1: 0x058, etc. ? sadd: source address of dma transfer the starting system bus source address is programmed by software before the dma channel is enabled or by a lli update before the start of the dma transfer. as the dma transfer is in progress, this register is updated to reflect the source address of the current system bus transfer. updated after each source system bus transfer. the sinc field in the ctlx register determines whether the address incre- ments, decrements, or is left unchanged on every source system bus transfer throughout the block transfer. 31 30 29 28 27 26 25 24 sadd 23 22 21 20 19 18 17 16 sadd 15 14 13 12 11 10 9 8 sadd 76543210 sadd
210 32003e?avr32?05/06 at32ap7000 17.10.2 channel x destination address register name: darx access: read/write reset: 0x0 the address offset for each channel is: 0x08+[x * 0x58] for example, dar0: 0x008, dar1: 0x060, etc. ? dadd: destination addr ess of dma transfer the starting system bus destination address is programmed by software before the dma channel is enabled or by a lli update before the start of the dma transfer. as the dma transfer is in progress, this register is updated to reflect the desti- nation address of the current system bus transfer. updated after each destination system bus transfer. the dinc fi eld in the ctlx register determines whether the address increments, decrements or is left unchanged on every destination system bus transfer throughout the block transfer. 31 30 29 28 27 26 25 24 dadd 23 22 21 20 19 18 17 16 dadd 15 14 13 12 11 10 9 8 dadd 76543210 dadd
211 32003e?avr32?05/06 at32ap7000 17.10.3 linked list pointer register for channel x name: llpx access: read/write reset: 0x0 the address offset for each channel is: 0x10+[x * 0x58] for example, llp0: 0x010, llp1: 0x068, etc. ? loc: address of the next lli starting address in memory of next lli if block chaining is enabled. note that the two lsbs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary. the user need to program this register to point to the first linked list item (lli) in memory prior to enabling the channel if block chaining is enabled. the llp register has two functions: 1. the logical result of the equation llp.loc != 0 is used to set up the type of dma transfer (single or multi-block). if llp.loc is set to 0x0, then transfers using linked lists are not enabled. this register must be programmed prior to enabling the channel in order to set up the transfer type. it (llp.loc != 0) contains the pointer to the next linked listed item for block chaining using linked lists. 2. the llpx register is also used to point to the address where write back of the control and source/destination sta- tus information occurs after block completion. 31 30 29 28 27 26 25 24 loc 23 22 21 20 19 18 17 16 loc 15 14 13 12 11 10 9 8 loc 76543210 loc 0 0
212 32003e?avr32?05/06 at32ap7000 17.10.4 control register for channel x low name: ctlxl access: read/write reset: 0x0 the address offset for each channel is: 0x18+[x * 0x58] for example, ctl0: 0x018, ctl1: 0x070, etc. this register contains fields that control the dma transfer. t he ctlxl register is part of the block descriptor (linked list it em) when block chaining is enabled. it can be varied on a block-by-block basis within a dma transfer when block chaining is enabled. ? int_en: interrupt enable bit if set, then all five interrupt generating sources are enabled. ? dst_tr_width: destination transfer width ? src_tr_width: source transfer width ? dinc: destination address increment indicates whether to increment or decrement the destination address on every destination system bus transfer. if your device is writing data to a destination peripheral fifo with a fixed address, then set this field to ?no change?. 00 = increment 01 = decrement 1x = no change ?sinc : source address increment indicates whether to increment or decrement the source addres s on every source system bus transfer. if your device is fetching data from a source peripheral fifo with a fixed address, then set this field to ?no change?. 00 = increment 01 = decrement 31 30 29 28 27 26 25 24 ? ? ? llp_s_en llp_d_en sms dms 23 22 21 20 19 18 17 16 dms tt_fc - d_scat_en s_gath_en src_msize 15 14 13 12 11 10 9 8 src_msize dest_msize sinc dinc 76543210 dinc src_tr_width dst_tr_width int_en src_tr_width/dst_tr_width size (bits) 000 8 001 16 010 32 other reserved
213 32003e?avr32?05/06 at32ap7000 1x = no change ? dest_msize: destination burst transaction length number of data items, each of width ctlx.dst_tr_width , to be written to the destination every time a destination burst transaction request is made from either the corres ponding hardware or software handshaking interface. ?src_msize: source burst transaction length number of data items, each of width ctlx.src_tr_width , to be read from the source every time a source burst transac- tion request is made from either the correspondi ng hardware or software handshaking interface. ?s_gath_en : source gather enable bit 0 = gather is disabled. 1 = gather is enabled. gather on the source side is only applicable when the ct lx.sinc bit indicates an incrementing or decrementing address control. ?d_scat_en : destination scatter enable bit 0 = scatter is disabled. 1 = scatter is enabled. scatter on the destination side is only applicable when the ctlx.dinc bit indicates an incrementing or decrementing address control. ? tt_fc: transfer type and flow control the following transfer types are supported. ? memory to memory ? memory to peripheral ? peripheral to memory flow control can be assigned to the dmac, the so urce peripheral, or the destination peripheral. ?dms: destination master select identifies the master interface layer where the destination device (peripheral or memory) resides. 00 = ahb master 1 01 = reserved tt_fc transfer type flow controller 000 memory to memory dmac 001 memory to peripheral dmac 010 peripheral to memory dmac 011 peripheral to peripheral dmac 100 peripheral to memory peripheral 101 peripheral to peripheral source peripheral 110 memory to peripheral peripheral 111 peripheral to peripheral destination peripheral
214 32003e?avr32?05/06 at32ap7000 10 = reserved 11 = reserved ?sms: source master select identifies the master interface layer where the source device (peripheral or memory) is accessed from. 00 = ahb master 1 01 = reserved 10 = reserved 11 = reserved ?llp_d_en block chaining is only enabled on the destination side if the llp_d_en field is high and llpx.loc is non-zero. ?llp_s_en block chaining is only enabled on the source side if the llp_s_en field is high and llpx.loc is non-zero.
215 32003e?avr32?05/06 at32ap7000 17.10.5 control register for channel x high name: ctlxh access: read/write reset: 0x0 ? block_ts: block transfer size when the dmac is flow controller, this fi eld is written by the user before the chan nel is enabled to indicate the block size. the number programmed into block_ts indicates the total number of single transactions to perform for every block transfer. the width of the single transaction is determined by ctlx.src_tr_width. ?done: done bit if status writeback is enabled, the control register ctlxh, is written to the control register location of the linked list item in system memory at the end of the block transfer with the done bit set. software can poll the lli ctlx.done bit to see when a bl ock transfer is complete. the lli ctlx.done bit should be cleared when the linked lists are setup in memory prior to enabling the channel. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ? ? ? done ? block_ts 76543210 block_ts
216 32003e?avr32?05/06 at32ap7000 17.10.6 source status register for channel x name: sstatx access: read/write reset: 0x0 the address offset for each channel is: 0x20+[x * 0x58] for example, sstat0: 0x020, sstat1: 0x078, etc. ? sstat: source status information after the completion of each block transfer, hardware can retrieve the source status information from the address pointed to by the contents of the sstatrx register. this status informat ion is then stored in the sstatx register and written out to the sstatarx register location of the lli before the start of the next block.this register is a temporary placeholder for the source status information on its way to the sstatx register location of the lli. the source status information should be retrieved by software from the sstatx register location of th e lli and not by a read of this register over the dmac slave interface. 31 30 29 28 27 26 25 24 sstat 23 22 21 20 19 18 17 16 sstat 15 14 13 12 11 10 9 8 sstat 76543210 sstat
217 32003e?avr32?05/06 at32ap7000 17.10.7 destination status register for channel x name: dstatx access: read/write reset: 0x0 the address offset for each channel is: 0x28+[x * 0x58] for example, dstat0: 0x028, dstat1: 0x080, etc. ? dstat: destination status information after the completion of each block transfer, hardware can retrieve the destination status information from the address pointed to by the contents of the dstatarx register. this st atus information is then stored in the dstatx register and written out to the dstatx register location of the lli before the start of the next block. this register is a temporary placeholder for the destination stat us information on its way to the dstatx register location of the lli. the destination status information should be retrieved by software from the dstatx register location of the lli and not by a read of this register over the dmac slave interface. 31 30 29 28 27 26 25 24 dstat 23 22 21 20 19 18 17 16 dstat 15 14 13 12 11 10 9 8 dstat 76543210 dstat
218 32003e?avr32?05/06 at32ap7000 17.10.8 source status address register for channel x name: sstatarx access: read/write reset: 0x0 the address offset for each channel is: 0x30+[x * 0x58] for example, sstatar0: 0x030, sstatar1: 0x088, etc. ? sstatar: source status information address pointer from where hardware can fetch the source status information.this status information is registered in the sstatx register and written out to the sstatx register location of the lli before the start of the next block. 31 30 29 28 27 26 25 24 sstatar 23 22 21 20 19 18 17 16 sstatar 15 14 13 12 11 10 9 8 sstatar 76543210 sstatar
219 32003e?avr32?05/06 at32ap7000 17.10.9 destination status address register for channel x name: dstatarx access: read/write reset: 0x0 the address offset for each channel is: 0x38+[x * 0x58] for example, dstatar0: 0x0 38, dstatar1: 0x090, etc. ? dstatar: destination status information address pointer from where hardware can fetch the destination status information. this status information is registered in the dstatx register and written out to the dstatx register location of the lli before the start of the next block. 31 30 29 28 27 26 25 24 dstatar 23 22 21 20 19 18 17 16 dstatar 15 14 13 12 11 10 9 8 dstatar 76543210 dstatar
220 32003e?avr32?05/06 at32ap7000 17.10.10 configuration register for channel x low name: cfgxl access: read/write reset: 0x0 the address offset for each channel is: 0x40+[x * 0x58] for example, cfg0: 0x040, cfg1: 0x098, etc. ? ch_prior: channel priority a priority of 7 is the highest priority, and 0 is the lowest. this field must be programmed within the following range [0, x ? 1] a programmed value outside this range causes erroneous behavior. ? ch_susp: channel suspend suspends all dma data transfers from the source until this bit is cleared. there is no guarantee that the current transaction will complete. can also be used in conjunction with cf gx.fifo_empty to cleanly disable a channel without losing any data. 0 = not suspended. 1 = suspend. suspend dma transfer from the source. ? fifo_empty indicates if there is data left in the channel's fifo. can be used in conjunction with cfgx .ch_susp to cleanly disable a channel. 1 = channel's fifo empty 0 = channel's fifo not empty ? hs_sel_dst: destination software or hardware handshaking select this register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this channel. 0 = hardware handshaking interface. software-initiated transaction requests are ignored. 1 = software handshaking interface. hardware initiated transaction requests are ignored. if the destination peripheral is memory, then this bit is ignored. ? hs_sel_src: source software or hardware handshaking select this register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel. 0 = hardware handshaking interface. software-initiated transaction requests are ignored. 31 30 29 28 27 26 25 24 reload_ds reload_sr max_abrst 23 22 21 20 19 18 17 16 max_abrst sr_hs_pol ds_hs_pol lock_b lock_ch 15 14 13 12 11 10 9 8 lock_b_l lock_ch_l hs_sel_sr hs_sel_ds fifo_empt ch_susp 76543210 ch_prior ?????
221 32003e?avr32?05/06 at32ap7000 1 = software handshaking interface. hardware-initiated transaction requests are ignored. if the source peripheral is memory, then this bit is ignored. ?lock_ch_l : channel lock level indicates the duration over which cfgx.lock_ch bit applies. 00 = over complete dma transfer 01 = over complete dma block transfer 1x = over complete dma transaction ?lock_b_l: bus lock level indicates the duration over which cfgx.lock_b bit applies. 00 = over complete dma transfer 01 = over complete dma block transfer 1x = over complete dma transaction ?lock_ch: channel lock bit when the channel is granted control of the master bus interf ace and if the cfgx.lock_ch bit is asserted, then no other channels are granted control of the master bus interface for th e duration specified in cfgx.lock_ch_l. indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the duration specified in cfgx.lock_ch_l. ?lock_b: bus lock bit when active, the system bus master signal hlock is asserted for the duration specified in cfgx.lock_b_l. ?ds_hs_pol: destination handshaking interface polarity 0 = active high 1 = active low ? sr_hs_pol: source handshaking interface polarity 0 = active high 1 = active low ? max_abrst: maximum system bus burst length maximum system bus burst length that is used for dma transfer s on this channel. a value of ?0? indicates that software is not limiting the maximum burst length for dma transfers on this channel. ? reload_sr: automatic source reload the sarx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. a new block transfer is then initiated. ? reload_ds: automatic destination reload the darx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. a new block transfer is then initiated.
222 32003e?avr32?05/06 at32ap7000 17.10.11 configuration register for channel x high name: cfgxh access: read/write reset: 0x0 ?fcmode: flow control mode determines when source transaction requests are serviced when the destination peripheral is the flow controller. 0 = source transaction requests are serviced when they occur. data pre-fetching is enabled. 1 = source transaction requests are not serviced until a destinat ion transaction request occurs. in this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block term i- nation by the destination. data pre-fetching is disabled. ? fifo_mode: r/w 0x0 fifo mode select determines how much space or data needs to be available in the fifo before a burst transaction request is serviced. 0 = space/data available for single system bus transfer of the specified transfer width. 1 = space/data available is greater than or equal to half the fi fo depth for destination transfers and less than half the fifo depth for source transfers. the exceptions are at the end of a burst transaction request or at the end of a block transfer. ? protctl: protection control bits used to drive the system bus hprot[3:1] bus. the system bus specification recommends that the default value of hprot indicates a non-cached, nonbuffered, privileged data access. the reset value is used to indicate such an access. hprot[0] is tied high as all transfers are data accesses as there are no opcode fetches. there is a one-to-one mapping of these register bits to the hprot[3:1] master interface signals. ? ds_upd_en: destination status update enable destination status information is only fetched from the location pointed to by the dstatarx register, stored in the dstatx register and written out to the dstatx location of the lli if ds_upd_en is high. ? ss_upd_en: source status update enable source status information is only fetched from the location pointed to by the sstatarx register, stored in the sstatx reg- ister and written out to the sstatx location of the lli if ss_upd_en is high. ? src_per: source hardware handshaking interface assigns a hardware handshaking interface (0 - dmah_num_hs_int-1) to the source of channel x if the cfgx.hs_sel_src field is 0. otherwise, this field is ignored. the channel can then communicate with the source periph- eral connected to that interface via th e assigned hardware handshaking interface. for correct dmac operation, only one peripheral (source or destination) should be assi gned to the same handshaking interface. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? dest_per src_per 76543210 src_per ss_upd_en ds_upd_en protctl fifo_mode fcmode
223 32003e?avr32?05/06 at32ap7000 ? dest_per: destination hardware handshaking interface assigns a hardware handshaking interface (0 - dm ah_num_hs_int-1) to th e destination of channel x if the cfgx.hs_sel_dst field is 0. otherwise, this field is ignored. the channel can then communicate with the destination peripheral connected to that interface via the assigned hardware handshaking interface. for correct dma operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
224 32003e?avr32?05/06 at32ap7000 17.10.12 source gather register for channel x name: sgrx access: read/write reset: 0x0 the address offset for each channel is: 0x48+[x * 0x58] for example, sgr0: 0x048, sgr1: 0x0a0, etc. the ctlx.sinc field controls whether the address increments or decrements. when the ctlx.sinc field indicates a fixed- address control, then the address remains constant throughout the transfer and the sgrx register is ignored. ? sgi: source gather interval source gather count field specifies the number of contiguo us source transfers of ctlx .src_tr_width between succes- sive gather intervals. this is defined as a gather boundary. ? sgc: source gather count source gather interval field (sgrx.sgi) ? specifies the source address increment/decrement in multiples of ctlx.src_tr_width on a gather boundary when gather mode is enabled for the source transfer. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 sgc sgi 15 14 13 12 11 10 9 8 sgi 76543210 sgi
225 32003e?avr32?05/06 at32ap7000 17.10.13 destination scatter register for channel x name: dsrx access: read/write reset: 0x0 the address offset for each channel is: 0x50+[x * 0x58] for example, dsr0: 0x050, dsr1: 0x0a8, etc. the ctlx.dinc field controls whether the address increments or decrements. when the ctlx.dinc field indicates a fixed address control then the address remains constant throughout the transfer and the dsrx register is ignored. ? dsi: destination scatter interval destination scatter interval field (dsrx.dsi) ? specifies the destination address increment/decrement in multiples of ctlx.dst_tr_width on a scatter boundary when scatter mode is enabled for the destination transfer. ? dsc: destination scatter count destination scatter count field (dsrx.dsc) ? specif ies the number of contiguous destination transfers of ctlx.dst_tr_width between successive scatter boundaries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 dsc dsi 15 14 13 12 11 10 9 8 dsi 76543210 dsi
226 32003e?avr32?05/06 at32ap7000 17.10.14 interrupt registers the following sections describe the registers pertaining to interrupts, their status, and how to clear them. for each channel, there are five types of interrupt sources: ? inttfr: dma transfer complete interrupt this interrupt is generated on dma transfer completion to the destination peripheral. ? intblock: block transfer complete interrupt this interrupt is generated on dma block transfer completion to the destination peripheral. ? intsrctran: source transaction complete interrupt this interrupt is generated after completion of the last sy stem bus transfer of the requested single/burst transaction from the handshaking interface on the source side. if the source for a channel is memory, then that channel never generates a intsrctran interrupt and hence the correspond- ing bit in this field is not set. ? intdsttran: destination transaction complete interrupt this interrupt is generated after completion of the last sy stem bus transfer of the requested single/burst transaction from the handshaking interface on the destination side. if the destination for a channel is memory, then that channel never generates the intdsttran interrupt and hence the corre- sponding bit in this field is not set. ? interr: error interrupt this interrupt is generated when an error response is received from an ahb slave on the hresp bus during a dma transfer. in addition, the dma transfer is cancelled and the channel is disabled.
227 32003e?avr32?05/06 at32ap7000 17.10.15 interrupt raw status registers name: rawtfr, rawblock, rawsrc tran, rawdsttran, rawerr access: read reset: 0x0 the address offset are rawtfr ? 0x2c0 rawblock ? 0x2c8 rawsrctran ? 0x2d0 rawdsttran ? 0x2d8 rawerr ? 0x2e0 ? raw[2:0]: raw interrupt for each channel interrupt events are stored in these raw interrupt status registers before masking: rawtfr, rawblock, rawsrctran, rawdsttran, rawerr. each raw interrupt status register has a bit allocated per channel, for example, rawtfr[2] is chan- nel 2?s raw transfer complete interrupt. each bit in these regi sters is cleared by writing a 1 to the corresponding location in the cleartfr, clear block, clearsrctran, cleards ttran, clearerr registers. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????raw2raw1raw0
228 32003e?avr32?05/06 at32ap7000 17.10.16 interrupt status registers name: statustfr, statusblock, statussrctran, statusdsttran, statuserr access: read reset: 0x0 the address offset are statustfr: 0x2e8 statusblock: 0x2f0 statussrctran: 0x2f8 statusdsttran: 0x300 statuserr: 0x308 ? status[2:0] all interrupt events from all channels are stored in these interr upt status registers after masking: statustfr, statusblock, statussrctran, statusdsttran, statuserr. each interrupt status register has a bit allocated per channel, for example, sta- tustfr[2] is channel 2?s status transfer complete interrupt.the contents of these registers are used to generate the interrupt signals leaving the dmac. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????status2status1status0
229 32003e?avr32?05/06 at32ap7000 17.10.17 interrupt status registers name: masktfr, maskblock, masksrctran, maskdsttran, maskerr access: read/write reset: 0x0 the address offset are masktfr: 0x310 maskblock: 0x318 masksrctran: 0x320 maskdsttran: 0x328 maskerr: 0x330 the contents of the raw status registers are masked with the contents of the mask registers: masktfr, maskblock, masksrctran, maskdsttran, maskerr. each interrupt mask register has a bit allocated per channel, for example, mask- tfr[2] is the mask bit for channel 2?s transfer complete interrupt. a channel?s int_mask bit is only writt en if the corresponding mask write enable bit in the in t_mask_we field is asserted on the same system bus write transfer. this allows software to set a mask bit without performing a read-modified write operation. for example, writing hex 01x1 to the masktfr register writes a 1 into masktfr[0], while masktfr[7:1] remains unchanged. writing hex 00 xx leaves masktfr[7:0] unchanged. writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the dmac to set the appropriate bit in the status registers. ? int_mask[2:0]: interrupt mask 0 = masked 1 = unmasked ? int_m_we[10:8]: interrupt mask write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????int_m_we2int_m_we1int_m_we0 76543210 ?????int_m ask2 int_mask1 int_mask0
230 32003e?avr32?05/06 at32ap7000 17.10.18 interrupt clear registers name: cleartfr, clearblock, clearsrctran, cleardsttran,clearerr access: write reset: 0x0 the address offset are cleartfr: 0x338 clearblock: 0x340 clearsrctran: 0x348 cleardsttran: 0x350 clearerr: 0x358 ? clear[2:0]: interrupt clear 0 = no effect 1 = clear interrupt each bit in the raw status and status registers is cleared on the same cycle by writing a 1 to the corresponding location in the clear registers: cleartfr, clearblock, clearsrctran, cleardsttran, clearerr. each interrupt clear register has a bit allo- cated per channel, for example, cleartfr[2] is the clear bit fo r channel 2?s transfer complete interrupt. writing a 0 has no effect. these registers are not readable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????clear2clear1clear0
231 32003e?avr32?05/06 at32ap7000 17.10.19 combined interrupt status registers name: statusint access: read reset: 0x0 the contents of each of the five status registers (statustfr , statusblock, statussrctran, statusdsttran, statuserr) is or?d to produce a single bit per interrupt type in the combined status register (statusint). ?tfr or of the contents of statustfr register. ?block or of the contents of statusblock register. ?srct or of the contents of statussrctran register. ?dstt or of the contents of statusdsttran register. ?err or of the contents of statuserr register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? err dstt srct block tfr
232 32003e?avr32?05/06 at32ap7000 17.10.20 source software transaction request register name: reqsrcreg access: read/write reset: 0x0 a bit is assigned for each channel in this register. reqsrcreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel src_req bit is written only if the corresponding ch annel write enable bit in the req_we field is asserted on the same system bus write transfer. for example, writing 0x101 writes a 1 into reqsrcreg[0] , while reqsrcreg[3:1] remains unchanged. writing hex 0x0 yy leaves reqsrcreg[3:0] unchanged. this allows software to set a bit in the reqsrcreg register without performing a read- modified write ? src_req[2:0]: source request ? req_we[10:8]: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????req_we2req_we1req_we0 76543210 ?????src_req2src_req1src_req0
233 32003e?avr32?05/06 at32ap7000 17.10.21 destination software transaction request register name: reqdstreg access: read/write reset: 0x0 a bit is assigned for each channel in this register. reqdstreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel dst_req bit is written only if the corresponding channel write enable bit in the req_we field is asserted on the same system bus write transfer. ? dst_req[ 2:0]: destination request ? req_we[10:8]: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????req_we2req_we1req_we0 76543210 ?????dst_req2dst_req1dst_req0
234 32003e?avr32?05/06 at32ap7000 17.10.22 single source transaction request register name: sglreqsrcreg access: read/write reset: 0x0 a bit is assigned for each channel in this register. sglreqsrcreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel s_sg_req bit is written only if the corresponding channel write enable bit in th e req_we field is asserted on the same system bus write transfer. ? s_sg_req[2:0]: source single request ? req_we[10:8]: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????req_we2req_we1req_we0 76543210 ?????s_sg_req2s_sg_req1s_sg_req0
235 32003e?avr32?05/06 at32ap7000 17.10.23 single destination transaction request register name: sglreqdstreg access: read/write reset: 0x0 a bit is assigned for each channel in this register. sglreqdstreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel d_sg_req bit is written only if the corresponding channel write enable bit in the req_we field is asserted on the same system bus write transfer. ? d_sg_req[2:0]: destination single request ? req_we[10:8]: request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????req_we2req_we1req_we0 76543210 ?????d_sg_req2d_sg_req1d_sg_req0
236 32003e?avr32?05/06 at32ap7000 17.10.24 last source transaction request register name: lstsrcreqreg access: read/write reset: 0x0 a bit is assigned for each channel in this register. lstsrcreqreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel lstsrc bit is written only if the corresponding c hannel write enable bit in the lstsr_we field is asserted on the same system bus write transfer. ? lstsrc[2:0]: source last transaction request ? lstsr_we[10 : 8]: source last transaction request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????lstsr_we2lstsr_we1lstsr_we0 76543210 ?????lstsrc2lstsrc1lstsrc0
237 32003e?avr32?05/06 at32ap7000 17.10.25 last destination transaction request register name: lstdstreqreg access: read/write reset: 0x0 a bit is assigned for each channel in this register. lstdstreqreg[ n ] is ignored when software handshaking is not enabled for the source of channel n . a channel lstdst bit is written only if the corresponding ch annel write enable bit in the lstds_we field is asserted on the same system bus write transfer. ? lstdst[2:0]: destination last transaction request ? lstds_we[10:8]: destination last transaction request write enable 0 = write disabled 1 = write enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????lstds_we2lstds_we1lstds_we0 76543210 ?????lstdst2lstdst1lstdst0
238 32003e?avr32?05/06 at32ap7000 17.10.26 dmac configuration register name: dmacfgreg access: read/write reset: 0x0 ?dma_en: dma controller enable 0 = dmac disabled 1 = dmac enabled. this register is used to enable the dmac, which must be done before any channel activity can begin. if the global channel enable bit is clear ed while any channel is still active, then dm acfgreg.dma_en still returns ?1? to indi- cate that there are channels still active until hardware has terminated all activity on all channels, at which point the dmacfgreg.dma_en bit returns ?0?. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????dma_en
239 32003e?avr32?05/06 at32ap7000 17.10.27 dmac channel enable register name: chenreg access: read/write reset: 0x0 ? ch_en[2:0] 0 = disable the channel 1 = enable the channel enables/disables the channel. setting this bit enables a channel, clearing this bit disables the channel. the chenreg.ch_en bit is automatically cleared by hardware to disable the channel after the last system bus transfer of the dma transfer to the destination has completed.software ca n therefore poll this bit to determine when a dma transfer has completed. ? ch_en_we[10:8] the channel enable bit, ch_en, is only written if the corresponding channel writ e enable bit, ch_en_we, is asserted on the same system bus write transfer. for example, writing 0x101 writes a 1 into chenreg[0], while chenreg[7:1] remains unchanged. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????ch_en_we2ch_en_we1ch_en_we0 76543210 ?????ch_en2ch_en1ch_en0
240 32003e?avr32?05/06 at32ap7000 18. peripheral dma controller (pdc) rev: 6047c 18.1 features ? generates transfers to/from peripherals such as usart, ssc and spi ? supports up to 20 chan nels (product dependent) ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory 18.2 description the peripheral dma controller (pdc) transfers data between on-chip serial peripherals such as the uart, usart, ssc, spi, and the on- and off-chip memories. using the peripheral dma controller avoids processor intervention and removes the processor interrupt-handling over- head. this significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient. the pdc channels are implemented in pairs, each pair being dedicated to a particular periph- eral. one channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each uart, usart, ssc and spi. the user interface of a pdc channel is integrated in the memory space of each peripheral. it contains: ? a 32-bit memory pointer register ? a 16-bit transfer count register ? a 32-bit register for next memory pointer ? a 16-bit register for next transfer count the peripheral triggers pdc transfers usin g transmit and receive signals. when the pro- grammed data is transferred, an end of trans fer interrupt is generated by the corresponding peripheral.
241 32003e?avr32?05/06 at32ap7000 18.3 block diagram figure 18-1. block diagram control pdc channel 0 pdc channel 1 thr rhr control status & control peripheral peripheral dma controller memory controller
242 32003e?avr32?05/06 at32ap7000 18.4 functional description 18.4.1 configuration the pdc channels user interface enables the user to configure and control the data transfers for each channel. the user interface of a pdc channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. per peripheral, it contains four 32-bit pointer registers (rpr, rnpr, tpr, and tnpr) and four 16-bit counter re gisters (rcr, rncr, tcr, and tncr). the size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. the memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. it is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. the pdc has dedicated sta- tus registers which indicate if the transfer is enabl ed or disabled for each channel. the status for each channel is located in the peripheral status register. transfers can be enabled and/or dis- abled by setting txten/txtdis and rxten/rxtd is in pdc transfer co ntrol register. these control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. the pdc sends status flags to the peripheral visible in its status-register (endrx, endtx, rxbuff, and txbufe). endrx flag is set when the periph_rcr register reaches zero. rxbuff flag is set when both pe riph_rcr and periph_rncr reach zero. endtx flag is set when the per iph_tcr register reaches zero. txbufe flag is set when both pe riph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register. 18.4.2 memory pointers each peripheral is connected to the pdc by a receiver data channel and a transmitter data channel. each channel has an internal 32-bit memory pointer. each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers. if a memory pointer is reprogrammed while the pdc is in operation, the transfer address is changed, and the pdc performs transfers using the new address. 18.4.3 transfer counters there is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. these counters are decremented after each data transfer. when the counter reaches zero, the transfer is complete and the pdc stops transfer- ring data. if the next counter register is equal to zero, the pdc disables the trigger while activating the related peripheral end flag.
243 32003e?avr32?05/06 at32ap7000 if the counter is reprogrammed while the pdc is operating, the number of transfers is updated and the pdc counts transfers from the new value. programming the next counter/pointer register s chains the buffers. the counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the next counter/pointer are loaded into the counter/pointer registers in order to re-enable the triggers. for each channel, two status bits indicate the end of the current buffer (endrx, entx) and the end of both current and next buffer (rxbuff, txbufe). these bits are directly mapped to the peripheral status register and can trigger an interrupt request to the interrupt controller. the peripheral end flag is automatically cleared when one of the counter-registers (counter or next counter regi ster) is written. note: when the next counter register is loaded into the counter register, it is set to zero. 18.4.4 data transfers the peripheral triggers pdc transfers using transmit (txrdy) and receive (rxrdy) signals. when the peripheral receives an external characte r, it sends a receive ready signal to the pdc which then requests access to the system bus. when access is granted, the pdc starts a read of the peripheral receive holding register (rhr) and then triggers a write in the memory. after each transfer, the relevant pdc memory pointer is incremented and the number of trans- fers left is decremented. when the memory bl ock size is reached, a signal is sent to the peripheral and the transfer stops. the same procedure is followed, in reverse, for transmit transfers. 18.4.5 priority of pdc transfer requests the peripheral dma controller handles transfer requests from the channel according to priori- ties fixed for each product.these prioriti es are defined in the product datasheet. if simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. if transfer requests are not simultaneous, they are treated in the order they occurred. requests from the receivers are handled first and then followed by transmitter requests.
244 32003e?avr32?05/06 at32ap7000 18.5 peripheral dma controll er (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the per ipheral desired (usart, ssc, spi, etc). table 18-1. register mapping offset register register name read/write reset 0x100 receive pointer register periph (1) _rpr read/write 0x0 0x104 receive counter register periph_rcr read/write 0x0 0x108 transmit pointer register periph_tpr read/write 0x0 0x10c transmit counter register periph_tcr read/write 0x0 0x110 receive next pointer register periph_rnpr read/write 0x0 0x114 receive next counter register periph_rncr read/write 0x0 0x118 transmit next pointer register periph_tnpr read/write 0x0 0x11c transmit next counter register periph_tncr read/write 0x0 0x120 pdc transfer control register periph_ptcr write-only - 0x124 pdc transfer status r egister periph_ptsr read-only 0x0
245 32003e?avr32?05/06 at32ap7000 18.5.1 pdc receive pointer register register name: periph _ rpr access type: read/write ? rxptr: receive pointer address address of the next receive transfer. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr
246 32003e?avr32?05/06 at32ap7000 18.5.2 pdc receive counter register register name: periph _ rcr access type: read/write ? rxctr: receive counter value number of receive transfers to be performed. 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr
247 32003e?avr32?05/06 at32ap7000 18.5.3 pdc transmit pointer register register name: periph _ tpr access type: read/write ? txptr: transmit pointer address address of the transmit buffer. 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr
248 32003e?avr32?05/06 at32ap7000 18.5.4 pdc transmit counter register register name: periph _ tcr access type: read/write ? txctr: transmit counter value txctr is the size of the transmit transfer to be performed. at zero, the peripheral data transfer is stopped. 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txctr 76543210 txctr
249 32003e?avr32?05/06 at32ap7000 18.5.5 pdc receive next pointer register register name: periph _ rnpr access type: read/write ? rxnptr: receive next pointer address rxnptr is the address of the next buffer to fill with received data when th e current buffer is full. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr
250 32003e?avr32?05/06 at32ap7000 18.5.6 pdc receive next counter register register name: periph _ rncr access type: read/write ? rxncr: receive next counter value rxncr is the size of the next buffer to receive. 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxncr 76543210 rxncr
251 32003e?avr32?05/06 at32ap7000 18.5.7 pdc transmit next pointer register register name: periph _ tnpr access type: read/write ? txnptr: transmit next pointer address txnptr is the address of the next buffer to transmit when the current buffer is empty. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr
252 32003e?avr32?05/06 at32ap7000 18.5.8 pdc transmit next counter register register name: periph _ tncr access type: read/write ? txncr: transmit next counter value txncr is the size of the next buffer to transmit. 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txncr 76543210 txncr
253 32003e?avr32?05/06 at32ap7000 18.5.9 pdc transfer control register register name: periph_ptcr access type: write - only ? rxten: receiver transfer enable 0 = no effect. 1 = enables the receiver pdc transfer requests if rxtdis is not set. ? rxtdis: receiver transfer disable 0 = no effect. 1 = disables the receiver pdc transfer requests. ? txten: transmitter transfer enable 0 = no effect. 1 = enables the transmitter pdc transfer requests. ? txtdis: transmitter transfer disable 0 = no effect. 1 = disables the transmitter pdc transfer requests 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten
254 32003e?avr32?05/06 at32ap7000 18.5.10 pdc transfer status register register name: periph _ ptsr access type: read-only ? rxten: receiver transfer enable 0 = receiver pdc transfer requests are disabled. 1 = receiver pdc transfer requests are enabled. ? txten: transmitter transfer enable 0 = transmitter pdc transfer requests are disabled. 1 = transmitter pdc transfer requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
255 32003e?avr32?05/06 at32ap7000 19. parallel input/outp ut controller (pio) rev: 6057b 19.1 features ? up to 32 programmable i/o lines ? fully programmable through set/clear registers ? multiplexing of two peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change interrupt ? glitch filter ? programmable pull up on each i/o line ? pin data status register, supplies visibility of the le vel on the pin at any time ? synchronous output, provides set and clear of several i/o lines in a single write 19.2 description the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: ? an input change interrupt enabling level change detection on any i/o line. ? a glitch filter providing rejection of pulses lower than one-half of clock cycle. ? control of the the pull-up of the i/o line. ? input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
256 32003e?avr32?05/06 at32ap7000 19.3 block diagram figure 19-1. block diagram figure 19-2. application block diagram embedded peripheral embedded peripheral pio interrupt pio controller up to 32 pins power manager up to 32 peripheral ios up to 32 peripheral ios pio clock apb interrupt controller data, enable pin 31 pin 1 pin 0 data, enable on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
257 32003e?avr32?05/06 at32ap7000 19.4 product dependencies 19.4.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio con- troller can control how the pin is driven by the product. 19.4.2 external interrupt lines the external interrupt request signals are most generally multiplexed through the pio control- lers. however, it is not necessary to assign t he i/o line to the interrupt function as the pio controller has no effect on inputs and the external interrupt lines are used only as inputs. 19.4.3 power management the pio clock is generated by the power manager. before accessing the pio, the programmer must ensure that the pio clock is enabled in the power manager. note that the pio clock must be enabled when using the input change interrupt. in the pio descript ion, master clock (mck) is the apb-bus clock, to wh ich the pio is connected. 19.4.4 interrupt generation the pio interrupt line is connected to the interr upt controller. using th e pio interrupt requires the interrupt controller to be programmed first.
258 32003e?avr32?05/06 at32ap7000 19.5 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic asso- ciated to each i/o is represented in figure 19-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 19-3. i/o line control logic 1 0 1 0 glitch filter peripheral b input peripheral a input 1 0 pio_ifdr[0] pio_ifsr[0] pio_ifer[0] edge detector pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad pio_pudr[0] pio_pusr[0] pio_puer[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] 1 0 1 0 pio_bsr[0] pio_absr[0] pio_asr[0] peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr[0] pio_osr[0] pio_oer[0]
259 32003e?avr32?05/06 at32ap7000 19.5.1 pull-up resistor control each i/o line is designed with an embedded pull-up resistor. the value of this resistor is library- specific, refer to the electrical characteristi cs section for details. the pull-up resistor can be enabled or disabled by writing respectively pu er (pull-up enable register) and pudr (pull-up disable resistor). writing in these registers results in setting or clearing the corresponding bit in pusr (pull-up status register). reading a 1 in pusr means the pull-up is disabled and read- ing a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pusr resets at the value 0x0. 19.5.2 i/o line or peripheral function selection when a pin is multiplexed with one or two periph eral functions, the selection is controlled with the registers per (pio enable register) and pdr (pio disable register). the register psr (pio status register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the absr (ab select status register). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), per and pdr have no effect and psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. psr resets at 1. however, in some events, it is important that pio lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of psr is defined at the product level, depending on the multiplexing of the device. 19.5.3 peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writ ing asr (a select register) and bsr (select b register). absr (ab select status register) indicates which peri pheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corresponding bit at level 1 indicates that pe ripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, absr is 0, thus indicating that all the pio lines are configured on peripheral a. how- ever, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in asr and bsr manages absr regardless of the configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (asr or bsr) in addition to a write in pdr. 19.5.4 output control when the i/0 line is assigned to a peripheral function, i.e. the corresponding bit in psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in absr, determines whether the pin is driven or not. when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing oer (output enable regist er) and pdr (output disable register). the results of these write operations are detected in osr (output status register). when a bit in this
260 32003e?avr32?05/06 at32ap7000 register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the cor- responding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in sodr (set output data register) and codr (clear output data register). these write operations respectively set and clear odsr (output data status register), which represents the data driven on the i/o lines. writing in oer and odr manages osr whether the pin is configured to be controlled by the pio con- troller or assigned to a peripheral function. this enables configuration of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in sodr and co dr effects odsr. this is importan t as it defines the first level driven on the i/o line. 19.5.5 synchronous data output controlling all paralle l busses using several pios requires two successive write operations in the sodr and codr registers. this may lead to unexpected transient values. the pio controller offers a direct control of pio outputs by single write access to odsr (output data status regis- ter). only bits unmasked by oswsr (output write status register) are written. the mask bits in the owsr are set by writing to ower (output write enable register) and cleared by writing to owdr (output write disable register). after reset, the synchronous data output is disabled on all the i/o lines as owsr resets at 0x0. 19.5.6 output line timings figure 19-4 shows how the outputs are driven either by writing sodr or codr, or by directly writing odsr. this last case is valid only if the corresponding bit in owsr is set. figure 19-4 also shows when the feedback in pdsr is available. figure 19-4. output line timings 19.5.7 inputs the level on each i/o line can be read through pdsr (pin data status register). this register indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pdsr reads the levels present on the i/o line at the time the clock was disabled. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
261 32003e?avr32?05/06 at32ap7000 19.5.8 input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch fil- ter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automatically rejected, while a pulse with a duration of 1 mast er clock cycle or more is accepted. for pulse durations between 1/2 master clock cycle and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level change occurs before a rising edge. however, this latency does not appear if the pin level chan ge occurs before a falling ed ge. this is illustrated in figure 19-5 . the glitch filters are controlled by the register set; ifer (input filter enable register), ifdr (input filter disable register) and ifsr (input filter status register). writing ifer and ifdr respectively sets and clears bits in ifsr. this last register enables the glitch filter on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pdsr and on the input change interrupt detection. the glitch fil- ters require that the pio controller clock is enabled. figure 19-5. input glitch filter timing 19.5.9 input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is controlled by writing ier (interrupt enable register) and idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in imr (interrupt mask register). as input change detection is possible only by comparing two successive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regard- less of the configuration of the i/o line, i.e. configured as an input only, controlled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in isr (interrupt status register) is set. if the corresponding bit in imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the interrupt controller. when the software reads isr, all the interrupts are automatically cleared. th is signifies that all the interrupts that are pending when isr is read must be handled. mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle
262 32003e?avr32?05/06 at32ap7000 figure 19-6. input change interrupt timings 19.6 i/o lines programming example the programing example as shown in table 19-1 below is used to define the following configuration. ? 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation) ? four output signals on i/o lines 4 to 7 (to drive leds for example) ? four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts ? four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter ? i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor ? i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor ? i/o line 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor mck pin level read pio_isr apb access pio_isr apb access
263 32003e?avr32?05/06 at32ap7000 table 19-1. programming example register value to be written per 0x0000 ffff pdr 0x0fff 0000 oer 0x0000 00ff odr 0x0fff ff00 ifer 0x0000 0f00 ifdr 0x0fff f0ff sodr 0x0000 0000 codr 0x0fff ffff ier 0x0f00 0f00 idr 0x00ff f0ff pudr 0x00f0 00f0 puer 0x0f0f ff0f asr 0x0f0f 0000 bsr 0x00f0 0000 ower 0x0000 000f owdr 0x0fff fff0
264 32003e?avr32?05/06 at32ap7000 19.7 user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio control- ler user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not mul- tiplexed with any peripheral, the i/o line is controlled by the pio controller and psr returns 1 systematically. table 19-2. register mapping offset register name access reset value 0x0000 pio enable register per write-only ? 0x0004 pio disable register pdr write-only ? 0x0008 pio status register (1) psr read-only 0x0000 0000 0x000c reserved 0x0010 output enable register oer write-only ? 0x0014 output disable register odr write-only ? 0x0018 output status regi ster osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter en able register ifer write-only ? 0x0024 glitch input filter dis able register ifdr write-only ? 0x0028 glitch input filter status register ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data register sodr write-only ? 0x0034 clear output data register codr write-only ? 0x0038 output data status register (2) odsr read-only 0x0000 0000 0x003c pin data status register (3) pdsr read-only 0x0040 interrupt enable register ier write-only ? 0x0044 interrupt disable register idr write-only ? 0x0048 interrupt mask register imr read-only 0x0000 0000 0x004c interrupt status register (4) isr read-only 0x0000 0000 0x0050 reserved 0x0054 reserved 0x0058 reserved 0x005c reserved 0x0060 pull-up disable register pudr write-only ? 0x0064 pull-up enable register puer write-only ? 0x0068 pad pull-up status r egister pusr read-only 0x0000 0000 0x006c reserved
265 32003e?avr32?05/06 at32ap7000 notes: 1. reset value of psr depends on the product implementation. 2. odsr is read-only or read/write depending on owsr i/o lines. 3. reset value of pdsr depends on the level of the i/o lines. 4. isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. 5. only this set of registers clears the status by writing 1 in the first register and sets the st atus by writing 1 in the secon d register. 0x0070 peripheral a select register (5) asr write-only ? 0x0074 peripheral b select register (5) bsr write-only ? 0x0078 ab status register (5) absr read-only 0x0000 0000 0x007c to 0x009c reserved 0x00a0 output write enable ower write-only ? 0x00a4 output write disable owdr write-only ? 0x00a8 output write status re gister owsr read-only 0x0000 0000 0x00ac reserved table 19-2. register mapping (continued) offset register name access reset value
266 32003e?avr32?05/06 at32ap7000 19.7.1 pio controller pio enable register name: per access type: write-only ? p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
267 32003e?avr32?05/06 at32ap7000 19.7.2 pio controller pio disable register name: pdr access type: write-only ? p0-p31: pio disable 0 = no effect. 1 = disables the pio from controllin g the corresponding pin (enables peripheral contro l of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
268 32003e?avr32?05/06 at32ap7000 19.7.3 pio controller pio status register name: psr access type: read-only ? p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
269 32003e?avr32?05/06 at32ap7000 19.7.4 pio controller output enable register name: oer access type: write-only ? p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
270 32003e?avr32?05/06 at32ap7000 19.7.5 pio controller output disable register name: odr access type: write-only ? p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
271 32003e?avr32?05/06 at32ap7000 19.7.6 pio controller output status register name: osr access type: read-only ? p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
272 32003e?avr32?05/06 at32ap7000 19.7.7 pio controller input filter enable register name: ifer access type: write-only ? p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. 19.7.8 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
273 32003e?avr32?05/06 at32ap7000 pio controller input filter disable register name: ifdr access type: write-only ? p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
274 32003e?avr32?05/06 at32ap7000 19.7.9 pio controller input filter status register name: ifsr access type: read-only ? p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
275 32003e?avr32?05/06 at32ap7000 19.7.10 pio controller set output data register name: sodr access type: write-only ? p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
276 32003e?avr32?05/06 at32ap7000 19.7.11 pio controller clear output data register name: codr access type: write-only ? p0-p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
277 32003e?avr32?05/06 at32ap7000 19.7.12 pio controller output data status register name: odsr access type: read-only or read/write ? p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
278 32003e?avr32?05/06 at32ap7000 19.7.13 pio controller pin data status register name: pdsr access type: read-only ? p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
279 32003e?avr32?05/06 at32ap7000 19.7.14 pio controller interrupt enable register name: ier access type: write-only ? p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
280 32003e?avr32?05/06 at32ap7000 19.7.15 pio controller interrupt disable register name: idr access type: write-only ? p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
281 32003e?avr32?05/06 at32ap7000 19.7.16 pio controller interrupt mask register name: imr access type: read-only ? p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
282 32003e?avr32?05/06 at32ap7000 19.7.17 pio controller interrupt status register name: isr access type: read-only ? p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since isr was last read or since reset. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
283 32003e?avr32?05/06 at32ap7000 19.7.18 pio pull up disable register name: pudr access type: write-only ? p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
284 32003e?avr32?05/06 at32ap7000 19.7.19 pio pull up enable register name: puer access type: write-only ? p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
285 32003e?avr32?05/06 at32ap7000 19.7.20 pio pull up status register name: pusr access type: read-only ? p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
286 32003e?avr32?05/06 at32ap7000 19.7.21 pio peripheral a select register name: asr access type: write-only ? p0-p31: peripheral a select. 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
287 32003e?avr32?05/06 at32ap7000 19.7.22 pio peripheral b select register name: bsr access type: write-only ? p0-p31: peripheral b select. 0 = no effect. 1 = assigns the i/o line to the peripheral b function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
288 32003e?avr32?05/06 at32ap7000 19.7.23 pio peripheral a b status register name: absr access type: read-only ? p0-p31: peripheral a b status. 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
289 32003e?avr32?05/06 at32ap7000 19.7.24 pio output write enable register name: ower access type: write-only ? p0-p31: output write enable. 0 = no effect. 1 = enables writing od sr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
290 32003e?avr32?05/06 at32ap7000 19.7.25 pio output write disable register name: owdr access type: write-only ? p0-p31: output write disable. 0 = no effect. 1 = disables writing odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
291 32003e?avr32?05/06 at32ap7000 19.7.26 pio output write status register name: owsr access type: read-only ? p0-p31: output write status. 0 = writing odsr does not affect the i/o line. 1 = writing odsr affects the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
292 32003e?avr32?05/06 at32ap7000 20. serial peripheral interface (spi) rev: 6088d 20.1 features ? supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consec utive transfers and be tween clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? connection to pdc channel capabi lities optimizes data transfers ? one channel for the receiver, on e channel for the transmitter ? next buffer support 20.2 description the serial peripheral interface (spi) circuit is a synchronous serial data link that provides com- munication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi syste m acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' whic h have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. howeve r, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: ? master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). ? master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. ? serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. ? slave select (nss): this control line allows slaves to be turned on and off by hardware.
293 32003e?avr32?05/06 at32ap7000 20.3 block diagram figure 20-1. block diagram note: 1. n = 32 spi interface interrupt control pio pdc power manager mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 div npcs3 apb mck n (1)
294 32003e?avr32?05/06 at32ap7000 20.4 application block diagram figure 20-2. application block diagram: single master/multiple slave implementation spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
295 32003e?avr32?05/06 at32ap7000 20.5 signal description table 20-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
296 32003e?avr32?05/06 at32ap7000 20.6 product dependencies 20.6.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 20.6.2 power management the spi clock is generated by the power manager. before using the spi, the programmer must ensure that the spi clock is enabled in the power manager. in the spi descripti on, master clock (mck) is the apb-bus clock, to wh ich the spi is connected. 20.6.3 interrupt the spi interface has an interrupt line connected to the interrupt controller. handling the spi interrupt requires programming the interrupt controller before configuring the spi.
297 32003e?avr32?05/06 at32ap7000 20.7 functional description 20.7.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the re ceiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 20.7.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine th e edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possi- ble combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a dif- ferent slave. table 20-2 shows the four modes and corresponding parameter settings. figure 20-3 and figure 20-4 show examples of data transfers. table 20-2. spi bus protocol mode spi mode cpol ncpha 001 100 211 310
298 32003e?avr32?05/06 at32ap7000 figure 20-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 20-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
299 32003e?avr32?05/06 at32ap7000 20.7.3 master mode operations when configured in master mode, the spi uses the internal programmable baud rate generator as clock source. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data regis- ter, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the tdr (transmit data register). the written data is immediately transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. no transfer is started when writing into the tdr if the pcs field does not select a slave. the pcs field is set by writing the tdr in variable mode, or the mr in fixed mode, depending on the value of pcs field. if new data is written in tdr during the transfer, it stays in it until the current transfer is com- pleted. then, the received data is transferred from the shift register to rdr, the data in tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in tdr in the shift register is indicated by the tdre bit (transmit data register empty) in the status register (s r). when new data is written in tdr, this bit is cleared. the tdre bit is used to trigger the tran smit pdc channel. the end of transfer is indicated by the txempty fl ag in the sr register. if a transfer delay (dly- bct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift re gister in rdr is indicated by the rdrf bit (receive data register full) in the status r egister (sr). when the received data is read, the rdrf bit is cleared. if the rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in sr is set. as long as this flag is set, no data is loaded in rdr. the user has to read the status register to clear the ovres bit. figure 20-5 on page 300 shows a block diagram of the spi when operating in master mode. fig- ure 20-6 on page 301 shows a flow chart describing how transfers are handled.
300 32003e?avr32?05/06 at32ap7000 20.7.3.1 master mode block diagram figure 20-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits 0 1 fdiv mck mck/n baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
301 32003e?avr32?05/06 at32ap7000 20.7.3.2 master mode flow diagram figure 20-6. master mode flow diagram s spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
302 32003e?avr32?05/06 at32ap7000 20.7.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck) or the master clock divided by 32, by a value between 2 and 255. the selection between master clock or master clock divided by n is done by the fdiv value set in the mode register this allows a maximum operating baud rate at up to master clock/2 and a minimum operating baud rate of mck divided by 255*32. programming the scbr field at 0 is forbidden. tr iggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 20.7.3.4 transfer delays figure 20-7 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: ? the delay between chip selects, programmable only once for all the chip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. ? the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. ? the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 20-7. programmable delays dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
303 32003e?avr32?05/06 at32ap7000 20.7.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: ? fixed peripheral select: spi exchanges data with only one peripheral ? variable peripheral select: data can be exchanged with more than one peripheral fixed peripheral select is activated by writing t he ps bit to zero in mr (mode register). in this case, the current peripheral is defined by the pcs field in mr and the pcs fields of the chip select registers have no effect. variable peripheral select is activated by setting ps bit to one. the pcs field in tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without repro- gramming the mode register. data written in tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. using the pdc in this mo de requires 32-bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, however the spi still controls the number of bi ts (8 to16) to be tr ansferred through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 20.7.3.6 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external l ogic. this can be enabled by writing the pcs- dec bit at 1 in the mode register (mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
304 32003e?avr32?05/06 at32ap7000 20.7.3.7 peripheral deselection when operating normally, as soon as the transfer of the last data written in tdr is completed, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select li ne to remain active during a full set of transfers. to facilitate interfacing with such devices, the chip select regist er can be prog rammed with the csaat bit (chip select active afte r transfer) at 1. this allows th e chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. figure 20-8 shows different peripheral deselection cases and the effect of the csaat bit. figure 20-8. peripheral deselection a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 dlybct aa csaat = 1 a
305 32003e?avr32?05/06 at32ap7000 20.7.3.8 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss signal. as this pin is generally configured in open- drain, it is important that a pull up resistor is connected on the npcs0 line, so that a high level is guaranteed and no spurious mode fault is detected. when a mode fault is detected, the modf bit in the sr is set until the sr is read and the spi is automatically disabled until re-enabled by writing the spien bit in the cr (control register) at 1. by default, the mode fault detection circuitr y is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (mr). 20.7.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (csr0). these bits are processed follow- ing a phase and a polarity defined respectively by the ncpha and cpol bits of the csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if rdrf is already high wh en the data is transf erred, the overrun bit rises and the data transfer to rdr is aborted. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (t dr), the last data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift register resets at 0. when a first data is written in tdr, it is trans ferred immediately in the shift register and the tdre bit rises. if new data is wr itten, it remains in tdr until a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. when the transfer occurs, the last data written in tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no c haracter has been written in tdr since the last load from tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 20-9 shows a block diagram of the spi when operating in slave mode.
306 32003e?avr32?05/06 at32ap7000 figure 20-9. slave mode functional block diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits fload spien spidis miso
307 32003e?avr32?05/06 at32ap7000 20.8 user interface table 20-3. spi register mapping offset register register name access reset 0x00 control register cr write-only --- 0x04 mode register mr read/write 0x0 0x08 receive data register rdr read-only 0x0 0x0c transmit data register tdr write-only --- 0x10 status register sr read-only 0x000000f0 0x14 interrupt enable register ier write-only --- 0x18 interrupt disable register idr write-only --- 0x1c interrupt mask register imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 csr0 read/write 0x0 0x34 chip select register 1 csr1 read/write 0x0 0x38 chip select register 2 csr2 read/write 0x0 0x3c chip select register 3 csr3 read/write 0x0 0x100 - 0x124 reserved for the pdc
308 32003e?avr32?05/06 at32ap7000 20.8.1 spi control register name: cr access type: write-only ? spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. ? spidis: spi disable 0 = no effect. 1 = disables the spi. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. ? swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst?????spidisspien
309 32003e?avr32?05/06 at32ap7000 20.8.2 spi mode register name: mr access type: read/write ? mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ? ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. ? pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 16 chip selects according to the following rules: csr0 defines peripheral chip select signals 0 to 3. csr1 defines peripheral chip select signals 4 to 7. csr2 defines peripheral chip select signals 8 to 11. csr3 defines peripheral chip select signals 12 to 15. ? fdiv: clock selection 0 = the spi operates at mck. 1 = the spi operates at mck/n. ? modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. ? llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled. llb controls the local loopback on the data serializer for testing in master mode only. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? ? modfdis fdiv pcsdec ps mstr
310 32003e?avr32?05/06 at32ap7000 ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six mck periods (or 6*n mck period s if fdiv is set) will be inserted by default. otherwise, the following equat ion determines the delay: if fdiv is 0: if fdiv is 1: delay between chip selects dlybcs mck ---------------------- - = delay between chip selects dlybcs n mck --------------------------------- =
311 32003e?avr32?05/06 at32ap7000 20.8.3 spi receive data register name: rdr access type: read-only ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
312 32003e?avr32?05/06 at32ap7000 20.8.4 spi transmit data register name: tdr access type: write-only ? td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peri pheral by raising the correspo nding npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
313 32003e?avr32?05/06 at32ap7000 20.8.5 spi status register name: sr access type: read-only ? rdrf: receive data register full 0 = no data has been received since the last read of rdr 1 = data has been received and the receiv ed data has been transferred from the serializer to rdr since the last read of rdr. ? tdre: transmit data register empty 0 = data has been written to tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. ? modf: mode fault error 0 = no mode fault has been detected since the last read of sr. 1 = a mode fault occurred since the last read of the sr. ? ovres: overrun error status 0 = no overrun has been detected since the last read of sr. 1 = an overrun has occurred since the last read of sr. an overrun occurs when rdr is loaded at least twice from the seri alizer since the last read of the rdr. ? endrx: end of rx buffer 0 = the receive counter register has not reach ed 0 since the last write in rcr or rncr. 1 = the receive counter register has reached 0 since the last write in rcr or rncr. ? endtx: end of tx buffer 0 = the transmit counter register has not reache d 0 since the last write in tcr or tncr. 1 = the transmit counter register has reached 0 since the last write in tcr or tncr. ? rxbuff: rx buffer full 0 = rcr or rncr has a value other than 0. 1 = both rcr and rncr has a value of 0. ? txbufe: tx buffer empty 0 = tcr or tncr has a value other than 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
314 32003e?avr32?05/06 at32ap7000 1 = both tcr and tncr has a value of 0. ? nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. ? txempty: transmission registers empty 0 = as soon as data is written in tdr. 1 = tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. ? spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled.
315 32003e?avr32?05/06 at32ap7000 20.8.6 spi interrupt enable register name: ier access type: write-only ? rdrf: receive data register full interrupt enable ? tdre: spi transmit data regi ster empty interrupt enable ? modf: mode fault error interrupt enable ? ovres: overrun error interrupt enable ? endrx: end of receive bu ffer interrupt enable ? endtx: end of transmit buffer interrupt enable ? rxbuff: receive buffer full interrupt enable ? txbufe: transmit buffer empty interrupt enable ? txempty: transmission registers empty enable ? nssr: nss rising interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
316 32003e?avr32?05/06 at32ap7000 20.8.7 spi interrupt disable register name: idr access type: write-only ? rdrf: receive data register full interrupt disable ? tdre: spi transmit data register empty interrupt disable ? modf: mode fault error interrupt disable ? ovres: overrun error interrupt disable ? endrx: end of receive bu ffer interrupt disable ? endtx: end of transmit buffer interrupt disable ? rxbuff: receive buffer full interrupt disable ? txbufe: transmit buffer empty interrupt disable ? txempty: transmission registers empty disable ? nssr: nss rising interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
317 32003e?avr32?05/06 at32ap7000 20.8.8 spi interrupt mask register name: imr access type: read-only ? rdrf: receive data register full interrupt mask ? tdre: spi transmit data register empty interrupt mask ? modf: mode fault error interrupt mask ? ovres: overrun error interrupt mask ? endrx: end of receive buffer interrupt mask ? endtx: end of transmit buffer interrupt mask ? rxbuff: receive buffer full interrupt mask ? txbufe: transmit buffer empty interrupt mask ? txempty: transmission registers empty mask ? nssr: nss rising interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
318 32003e?avr32?05/06 at32ap7000 20.8.9 spi chip select register name: csr0... csr3 access type: read/write ? cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ? ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. ? csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. ? bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used, see table 20-4 on page 319 . 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat ? ncpha cpol
319 32003e?avr32?05/06 at32ap7000 . ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: if fdiv is 0: if fdiv is 1: note: n = 32 programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. table 20-4. bits, bits per transfer bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved spck baudrate mck scbr -------------- - = spck baudrate mck nscbr () ------------------------------ =
320 32003e?avr32?05/06 at32ap7000 otherwise, the following equations determine the delay: if fdiv is 0: if fdiv is 1: note: n = 32 ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: if fdiv is 0: if fdiv is 1: n = 32 delay before spck dlybs mck ------------------ - = delay before spck ndlybs mck ---------------------------- - = delay between consecutive transfers 32 dlybct mck ------------------------------------ scbr 2 mck ---------------- - + = delay between consecutive transfers 32 n dlybct mck ---------------------------------------------- - nscbr 2 mck ------------------------- + =
321 32003e?avr32?05/06 at32ap7000 21. two-wire interface (twi) rev: 6061b 21.1 features ? compatible with philips? i2c? protocol ? one, two or three bytes for slave address ? sequential read/write operations 21.2 description the two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-ori- ented transfer format. it can be used with any atme l two-wire bus serial eeprom. the twi is programmable as a master with sequential or single-byte access. a configurable baud rate gen- erator permits the output data rate to be adapted to a wide range of core clock frequencies. 21.3 block diagram figure 21-1. block diagram 21.4 application block diagram figure 21-2. application block diagram apb bridge power manager mck two-wire interface pio interrupt controller twi interrupt twck twd host with twi interface twd twck at24lc16 u1 at24lc16 u2 lcd controller u3 slave 1 slave 2 slave 3 rr vdd
322 32003e?avr32?05/06 at32ap7000 21.4.1 i/o lines description 21.5 product dependencies 21.5.1 i/o lines both twd and twck are bi-directional lines, connected to a positive supply voltage via a cur- rent source or pull-up resistor (see figure 21-2 on page 321 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open- collector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must program the pio controller to dedicate twd and twck as peripheral lines. 21.5.2 power management the twi clock is generated by the power manager. before using the twi, the programmer must ensure that the twi clock is enabled in the power manager. in the twi description, master clock (mck) is the apb-bus clock, to which the twi is connected. 21.5.3 interrupt the twi interface has an interrupt line connected to the interrupt controller. in order to handle interrupts, the interrupt controller must be programmed before configuring the twi. table 21-1. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
323 32003e?avr32?05/06 at32ap7000 21.6 functional description 21.6.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 21-4 on page 323 ). each transfer begins with a start condition and terminates with a stop condition (see figure 21-3 on page 323 ). ? a high-to-low transition on the twd line while twck is high defines the start condition. ? a low-to-high transition on the twd line while twck is high defines a stop condition. figure 21-3. start and stop conditions figure 21-4. transfer format 21.6.2 modes of operation the twi has two modes of operation: ? master transmitter mode ? master receiver mode the twi control register (cr) allows configurat ion of the interface in master mode. in this mode, it generates the clock according to the value programmed in the clock waveform gener- ator register (cwgr). this register defines the twck signal completely, enabling the interface to be adapted to a wide range of clocks. 21.6.3 transmitting data after the master initiates a start condition, it sends a 7-bit slave address, configured in the mas- ter mode register (dadr in mmr), to notify th e slave device. the bit following the slave address indicates the transfer direction (write or read). if this bit is 0, it indicates a write operation (trans- mit operation). if the bit is 1, it indicate s a request for data read (receive operation). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse, the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line during this clock pulse and sets the nak bit in the status register if the slave does not acknowledge the byte. as with the twd twck start stop twd twck start address r/w ack data ack data ack stop
324 32003e?avr32?05/06 at32ap7000 other status bits, an interrupt can be generated if enabled in the interrupt enable register (ier). after writing in the transmit-holding register (thr ), setting the start bit in the control register starts the transmission. the data is shifted in the internal shifter and when an acknowledge is detected, the txrdy bit is set un til a new write in the thr (see figure 21-6 below). the master generates a stop condition to end the transfer. the read sequence begins by setting the start bit. when the rxrdy bit is set in the status register, a character has been received in the receive-holding register (rhr). the rxrdy bit is reset when reading the rhr. the twi interface performs various transfer formats (7-bit slave address, 10-bit slave address). the three internal address bytes are configurable through the master mode register (mmr). if the slave device supports only a 7-bit address, iadrsz must be set to 0. for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (iadr). figure 21-5. master write with one, two or three bytes internal address and one data byte figure 21-6. master write with one byte internal address and multiple data bytes figure 21-7. master read with one, two or three bytes internal address and one data byte s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd a iadr(7:0) a data a s dadr w data a p data a txcomp txrdy write thr write thr write thr write thr twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p s dadr r a s dadr r a data n p s dadr r a data n p twd twd twd three bytes internal address two bytes internal address one byte internal address
325 32003e?avr32?05/06 at32ap7000 figure 21-8. master read with one byte internal address and multiple data bytes ?s = start ?p = stop ?w = write ? r = read ? a = acknowledge ? n = not acknowledge ? dadr= device address ? iadr = internal address figure 21-9 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 21-9. internal address usage a iadr(7:0) a s dadr w s dadr r a data a data n p txcomp write start bit rxrdy write stop bit read rhr read rhr twd s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
326 32003e?avr32?05/06 at32ap7000 21.6.4 read/write flowcharts the following flowcharts shown in figure 21-10 on page 326 and in figure 21-11 on page 327 give examples for read and write operations in master mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (ier) be configured first. figure 21-10. twi write in master mode set twi clock: twi_cwgr = clock set the control register: - master enable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send start the transfer twi_cr = start stop the transfer twi_cr = stop read status register txrdy = 0? data to send? read status register txcomp = 0? end start set theinternal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s
327 32003e?avr32?05/06 at32ap7000 figure 21-11. twi read in master mode set twi clock: twi_cwgr = clock set the control register: - master enable - slave disable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit read ==> bit mread = 0 internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 0? data to read? read status register txcomp = 0? end start set the internal address twi_iadr = address ye s ye s ye s ye s
328 32003e?avr32?05/06 at32ap7000 21.7 twi user interface 21.7.1 register mapping table 21-2. two-wire interface (twi) user interface offset register name access reset value 0x0000 control register cr write-only n/a 0x0004 master mode register mmr read/write 0x0000 0x0008 reserved - - - 0x000c internal address register iadr read/write 0x0000 0x0010 clock waveform generator register cwgr read/write 0x0000 0x0020 status register sr read-only 0x0008 0x0024 interrupt enable register ier write-only n/a 0x0028 interrupt disable register idr write-only n/a 0x002c interrupt mask register imr read-only 0x0000 0x0030 receive holding register rhr read-only 0x0000 0x0034 transmit holding register thr read/write 0x0000
329 32003e?avr32?05/06 at32ap7000 21.7.2 twi control register register name :cr access type: write-only ? start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the settings in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. ? stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read or write mode. in single data byte master read or write, the start and stop must both be set. in multiple data bytes master read or write, the stop must be set before ack/nack bit transmission. in master read mode, if a nack bit is received, the stop is automatically performed. in multiple data write operation, when both thr and shift register are empty, a stop condition is automatically sent. ? msen: twi master transfer enabled 0 = no effect. 1 = if msdis = 0, the master data transfer is enabled. ? msdis: twi master transfer disabled 0 = no effect. 1 = the master data transfer is disabled, all pending data is tr ansmitted. the shifter and holding characters (if they contain data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. ? swrst: software reset 0 = no effect. 1 = equivalent to a system reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? msdis msen stop start
330 32003e?avr32?05/06 at32ap7000 21.7.3 twi master mode register register name :mmr address type : read/write ? iadrsz: internal device address size ? mread: master read direction 0 = master write direction. 1 = master read direction. ? dadr: device address the device address is used in master mode to access slave devices in read or write mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? iadrsz[9:8] 0 0 no internal device address (byte command protocol) 0 1 one-byte internal device address 1 0 two-byte internal device address 1 1 three-byte internal device address
331 32003e?avr32?05/06 at32ap7000 21.7.4 twi internal address register register name :iadr access type : read/write ? iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. ? low significant byte address in 10-bit mode addresses. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr
332 32003e?avr32?05/06 at32ap7000 21.7.5 twi clock waveform generator register register name :cwgr access type : read/write ? cldiv: clock low divider the scl low period is defined as follows: ? chdiv: clock high divider the scl high period is defined as follows: ? ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 3 ) + t mck = t high chdiv ( 2 ckdiv () 3 ) + t mck =
333 32003e?avr32?05/06 at32ap7000 21.7.6 twi status register register name :sr access type : read-only ? txcomp: transmission completed 0 = in master, during the length of the current frame. in slave, from start received to stop received. 1 = when both holding and shift registers are empty and stop condition has been sent (in master), or when msen is set (enable twi). ? rxrdy: receive hold ing register ready 0 = no character has been received since the last rhr read operation. 1 = a byte has been received in therhr since the last read. ? txrdy: transmit holding register ready 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into thr register. 1 = as soon as data byte is transferred from thr to internal shifter or if a nack error is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). ? ovre: overrun error 0 = rhr has not been loaded while rxrdy was set 1 = rhr has been loaded while rxrdy was set. reset by read in sr when txcomp is set. ? unre: underrun error 0 = no underrun error 1 = no valid data in thr (txrdy set) while trying to load the data shifter. this action automatically generated a stop bit in master mode. reset by read in sr when txcomp is set. ? nack: not acknowledged 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the slave compo nent. set at the same time as txcomp. reset after read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
334 32003e?avr32?05/06 at32ap7000 21.7.7 twi interrupt enable register register name :ier access type: write-only ? txcomp: transmission completed ? rxrdy: receive hold ing register ready ? txrdy: transmit holding register ready ? ovre: overrun error ? unre: underrun error ? nack: not acknowledge 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
335 32003e?avr32?05/06 at32ap7000 21.7.8 twi interrupt disable register register name :idr access type: write-only ? txcomp: transmission completed ? rxrdy: receive hold ing register ready ? txrdy: transmit holding register ready ? ovre: overrun error ? unre: underrun error ? nack: not acknowledge 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
336 32003e?avr32?05/06 at32ap7000 21.7.9 twi interrupt mask register register name :imr access type : read-only ? txcomp: transmission completed ? rxrdy: receive hold ing register ready ? txrdy: transmit holding register ready ? ovre: overrun error ? unre: underrun error ? nack: not acknowledge 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
337 32003e?avr32?05/06 at32ap7000 21.7.10 twi receive holding register register name : rhr access type : read-only ? rxdata: master or slave receive holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata
338 32003e?avr32?05/06 at32ap7000 21.7.11 twi transmit holding register register name :thr access type: read/write ? txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
339 32003e?avr32?05/06 at32ap7000 22. ps/2 module (psif) rev: 1.0.0 22.1 features ? system bus apb slave ? ps/2 host ? receive and transmit capability ? parity generation and error detection ? overrun error detection 22.2 description the ps/2 module provides host functionality allowing the mcu to interface ps/2 devices such as keyboard and mice. the module is capable of both host-to-device and device-to-host communication. 22.3 product dependencies 22.3.1 i/o lines the ps/2 may be multiplexed with pio lines. the programmer must first program the pio con- troller to give control of the pins to the ps/2 module. 22.3.2 power management the clock for the ps/2 module is generated by the power manager. the programmer must ensure that the ps/2 clock is enabled in the power manager before using the ps/2 module. 22.3.3 interrupt the ps/2 module has an interrupt line connected to the interrupt controller. handling the ps/2 interrupt requires programming the interrupt controller before configuring the ps/2 module. 22.4 the ps/2 protocol the ps/2 protocol is a bidirectional synchronous serial communication protocol. it connects a single master - referred to as the ?host? - to a single slave - referred to as the ?device?. communi- cation is done through two lines called ?data? and ?clock?. both of these must be open-drain or open-collector with a pullup resistor to perform a wired-and function. when the bus is idle, both lines are high. the device always generates the clock signal, but the host may pull the clock low to inhibit trans- fers. the clock frequency is in the range 10-16.7 khz. both the host and the slave may initiate a transfer, but the host has ultimate control of the bus. data are transmitted one byte at a time in a frame consisting of 11-12 bits. the transfer format is described in detail below. 22.4.1 device to host communication the device can only initiate a transfer when the bus is idle. if the host at any time pulls the clock low, the device must stop transferring data and prepare to receive data from the host. the device transmits data using a 11-bit frame. t he device writes a bit on the data line when the clock is high, and the host reads the bit when the clock is low.
340 32003e?avr32?05/06 at32ap7000 the format of the frame is: ? 1 start bit - always 0. ? 8 data bits, least significant bit first. ? 1 parity bit - odd parity. ? 1 stop bit - always 1. figure 22-1. device to host transfer 22.4.2 host to device communication because the device always generates the clock, host to device communication is done differ- ently than device to host communication. ? the host starts by inhibiting communicati on by pulling clock low for a minimum of 100 microseconds. ? then applies a ?request-to-send? by releasing clock and pulling data low. the device must check for this state at least ev ery 10 milliseconds. once it detects a request-to- send, it must start generating the clock and receive one frame of data. the host writes a data bit when the clock is low, and the device reads the bit when the clock is high. the format of the frame is: ? 1 start bit - always 0. ? 8 data bits - least significant bit first. ? 1 parity bit - odd parity ? 1 stop bit - always one. ? 1 acknowledge bit - the device acknowledges by pulling data low. clock data start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 7 stop bit 6
341 32003e?avr32?05/06 at32ap7000 figure 22-2. host to device transfer 22.5 functional description 22.5.1 prescaler for all data transfers on the ps/2 bus, the dev ice is responsible for generating the clock and thus controlling the timing of th e communications. when a host wa nts to initiate a transfer how- ever, it needs to pull the clock line low for a given time (minimum 100s). a clock prescaler controls the timing of the transfer request pulse. before initiating host to device transfers, the programmer must write psr (prescale register). this value determines the length of the ?transfer request? pulse and is found by: prscv = pulse length * ps/2 module frequency according to the ps/2 specifications, the pulse length should be at least 100s. the ps/2 mod- ule frequency is the frequ ency of the apb bus to which the module is connected. 22.5.2 receiving data the receiver is enabled by writing the rxen bi t in cr (control register) to ?1?. when enabled, the receiver will continuously receiv e data transmitted by the device . the data is stored in rhr (receive holding register). when a byte has been received, the rxrdy bit in sr (status reg- ister) is set. for each received byte, the parity is calculated. if it doesn?t match the parity bit received from the device, the parity bit in sr is set. the received byte should then be discarded. if a received byte in rhr is not read before a new byte has been received, the overrun bit - ovrun in sr is set. the new data is stored in rhr overwriting the previously received byte. 22.5.3 transmitting data the transmitter is enabled by writing the txen bit in cr to ?1?. when enabled, a data transfer to the device will be started by wr iting the transmit data to thr (transmit holding register). any ongoing transfer from the device will be aborted. clock data host clock host data device clock device data start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 7 stop bit 6 inhibit ack
342 32003e?avr32?05/06 at32ap7000 when the data written to thr has been transmitted to the device, the txrdy bit in sr will be set and a new value can be loaded into thr. at the end of the transfer, the device should acknowledge the transfer by pulling the data line low for one cycle. if an acknowledge is not detected, the nack bit in sr will be set. if the device fails to a cknowledge the frame, th e nack bit in sr will be set. the software is responsible for any retries. all transfers from host to device are started by the host pulling the clock line low for at least 100s. the programmer must ensure that the prescaler is programmed to generate correct pulse length. 22.5.4 interrupts the ps/2 module can be configured to signal an interrupt when one of the bits in sr is set. the interrupt is enabled by writing to ier (interrupt enable register) and disabled by writing to idr (interrupt disable register). the current setting of an interrupt line can be seen by reading imr (interrupt mask register).
343 32003e?avr32?05/06 at32ap7000 22.6 user interface offset register register name access reset 0x00 ps/2 control register cr write-only - 0x04 ps/2 receive holding register rhr read-only 0x0 0x08 ps/2 transmit holding register thr write-only - 0x0c reserved - - - 0x10 ps/2 status register sr read-only 0x0 0x14 ps/2 interrupt enable register ier write-only - 0x18 ps/2 interrupt disable register idr write-only - 0x1c ps/2 interrupt mask register imr read-only 0x0 0x20 ps/2 prescale register psr write-only 0x0
344 32003e?avr32?05/06 at32ap7000 22.6.1 ps/2 control register name: cr access type: write-only ? swrst: software reset writing this strobe causes a reset of the ps/2 interface module. data shift registers are cleared and configuration registers a re reset to default values. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis=0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? rxen: receiver enable 0: no effect. 1: enables the receiver if rxdis=0. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 swrst - - - - - txdis txen 76543210 ------rxdisrxen
345 32003e?avr32?05/06 at32ap7000 22.6.2 ps/2 receive holding register name: rhr access type: read-only ? rxdata: receive data data received from the device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 rxdata
346 32003e?avr32?05/06 at32ap7000 22.6.3 ps/2 transmit holding register name: thr access type: write-only ? txdata: transmit data ? data to be transmitted to the device. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 txdata
347 32003e?avr32?05/06 at32ap7000 22.6.4 ps/2 status register name: sr access type: read-only ? parity: 0: no parity errors detected on incoming data since last read of sr. 1: at least one parity error detected on incoming data since last read of sr. ? nack: not acknowledge 0: all transmissions has been properly acknowle dged by the device since last read of sr. 1: at least one transmission was not properly acknowledged by the device since last read of sr. ? ovrun: overrun 0: no receive overrun has occured since the last read of sr. 1: at least one receive overrun condition has occured since the last read of sr. ? rxrdy: receiver ready 0: rhr is empty. 1: rhr contains valid data received from the device. ? txempty: transmitter empty 0: data remains in thr or is currently being transmitted from the shift register. 1: both thr and the sh ift register are empty. ? txrdy: transmitter ready 0: data has been loaded in thr and is waiting to be loaded into the shift register. 1: thr is empty. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------paritynack 76543210 - - ovrun rxrdy - - txempty txrdy
348 32003e?avr32?05/06 at32ap7000 22.6.5 ps/2 interrupt enable register name: ier access type: write-only ? parity: parity interrupt enable ? nack: not acknowledge interrupt enable ? ovrun: overrun interrupt enable ? rxrdy: overrun interrupt enable ? txempty: overrun interrupt enable ? txrdy: overrun interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------paritynack 76543210 - - ovrun rxrdy - - txempty txrdy
349 32003e?avr32?05/06 at32ap7000 ? 22.6.6 ps/2 interrupt disable register name: idr access type: write-only ? parity: parity interrupt disable ? nack: not acknowledge interrupt disable ? ovrun: overrun interrupt disable ? rxrdy: overrun interrupt disable ? txempty: overrun interrupt disable ? txrdy: overrun interrupt disable 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------paritynack 76543210 - - ovrun rxrdy - - txempty txrdy
350 32003e?avr32?05/06 at32ap7000 22.6.7 ps/2 interrupt mask register name: imr access type: read-only ? parity: parity interrupt mask ? nack: not acknowledge interrupt mask ? ovrun: overrun interrupt mask ? rxrdy: overrun interrupt mask ? txempty: overrun interrupt mask ? txrdy: overrun interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ------paritynack 76543210 - - ovrun rxrdy - - txempty txrdy
351 32003e?avr32?05/06 at32ap7000 22.6.8 ps/2 prescale register name: psr access type: read/write ? prscle: prescale value 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - prscv 76543210 prscv
352 32003e?avr32?05/06 at32ap7000 23. synchronous serial controller (ssc) rev: 6078b 23.1 features ? provides serial synchronous communication links used in audio and telecom applications ? contains an independent receiver and transmitter an d a common clock divider ? interfaced with two pdc channels (dma access) to reduce processor overhead ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to st art automatically or on detection of different events on the frame sync signal ? receiver and transmitter includ e a data signal, a cl ock signal and a frame synchronization signal 23.2 description the atmel synchronous serial controller (ssc ) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be pro- grammed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of programmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: ? codec?s in master or slave mode ? dac through dedicated serial interface, particularly i2s ? magnetic card reader
353 32003e?avr32?05/06 at32ap7000 23.3 block diagram figure 23-1. block diagram 23.4 application block diagram figure 23-2. application block diagram ssc interface pio pdc apb bridge mck ahb apb tf tk td rf rk rd interrupt control ssc interrupt power manager interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
354 32003e?avr32?05/06 at32ap7000 23.5 pin name list 23.6 product dependencies 23.6.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio contro ller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 23.6.2 power management the ssc clock is generated by the power manager. before using the ssc, the programmer must ensure that the ssc clock is enabled in the power manager. in the sscdescription, master clock (mck) is the apb-bus clock, to which the ssc is connected. 23.6.3 interrupt the ssc interface has an interrupt line connected to the interrupt controller. handling interrupts requires programming the interrupt controller before configuring the ssc. all ssc interrupts can be enabled/disabled configur ing the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. 23.7 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by pro- gramming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be pro- grammed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfer s. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. table 23-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output
355 32003e?avr32?05/06 at32ap7000 figure 23-3. ssc functional block diagram 23.7.1 clock management the transmitter clock can be generated by: ? an external clock received on the tk i/o pad ? the receiver clock ? the internal clock divider the receiver clock can be generated by: ? an external clock received on the rk i/o pad ? the transmitter clock ? the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. interrupt control interrupt controller user interface apb mck receive clock controller start selector tx clock rk input rf tf clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register load shift td tf tk rx clock rx pdc receiver pdc transmitter clock divider
356 32003e?avr32?05/06 at32ap7000 23.7.1.1 clock divider figure 23-4. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode regist er cmr, allowing a master clock division by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of mas- ter clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50 % duty cycle for the divided clock regardless of whether the div value is even or odd. figure 23-5. divided clock generation 23.7.1.2 transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transmitter clock is selected by the cks field in tcmr (transmit clock mode register). transmit cl ock can be inverted independently by the cki bits in tcmr. table 23-2. maximum minimum mck / 2 mck / 8190 mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
357 32003e?avr32?05/06 at32ap7000 the transmitter can also drive the tk i/o pad cont inuously or be limited to the actual data trans- fer. the clock output is configured by the tcmr register. the transmit clock inversion (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks field) and at the same time continuous transmit clock (cko field) might lead to unpredictable results. figure 23-6. transmitter clock management 23.7.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in rcmr. the receiver can also drive the rk i/o pad continuo usly or be limited to the actual data transfer. the clock output is configured by the rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) can lead to unpredictable results. tk (pin) receiver clock divider clock cks cko data transfer cki ckg transmitter clock clock output mux tri_state controller tri-state controller inv mux
358 32003e?avr32?05/06 at32ap7000 figure 23-7. receiver clock management 23.7.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: ? master clock divided by 2 if receiver frame synchro is input ? master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock speed allowed on the tk pin is: ? master clock divided by 6 if transmit frame synchro is input ? master clock divided by 2 if transmit frame synchro is output 23.7.2 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (tcmr). see section ?23.7.4? on page 360. the frame synchronization is configured setting the transmit frame mode register (tfmr). see section ?23.7.5? on page 362. to transmit data, the transmitter uses a shift re gister clocked by the transmitter clock signal and the start mode selected in the tcmr. data is written by the application to the thr register then transferred to the shift register according to the data format selected. when both the thr and the transmit shift register are empty, the status flag txempty is set in sr. when the transmit holding register is transferred in the transmit shift register, the status flag txrdy is set in sr and additional data can be loaded in the holding register. rk (pin) transmitter clock divider clock cks cko data transfer cki ckg receiver clock clock output mux tri-state controller tri-state controller inv mux
359 32003e?avr32?05/06 at32ap7000 figure 23-8. transmitter block diagram 23.7.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (rcmr). see section ?23.7.4? on page 360. the frame synchronization is configured setting the receive frame mode register (rfmr). see section ?23.7.5? on page 362. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the rcmr. the data is transferred from the shift register depending on the data for- mat selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the sta- tus flag rxrdy is set in sr and the data can be read in the receiver holding register. if another transfer occurs before read of the rhr register, the status flag overun is set in sr and the receiver shift register is tr ansferred in the rhr register. transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden 0 1 1 0 rf tf
360 32003e?avr32?05/06 at32ap7000 figure 23-9. receiver block diagram 23.7.4 start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start selection (start) field of tcmr and in the receive start selection (start) field of rcmr. under the following conditions the start event is independently programmable: ? continuous. in this case, the transmission starts as soon as a word is written in thr and the reception starts as soon as the receiver is enabled. ? synchronously with the transmitter/receiver ? on detection of a falling/rising edge on tf/rf ? on detection of a low level/high level on tf/rf ? on detection of a level change or an edge on tf/rf a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start coul d be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fsos of the transmit/receive frame mode register (tfmr/rfmr). receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf
361 32003e?avr32?05/06 at32ap7000 figure 23-10. transmit start mode figure 23-11. receive pulse/ed ge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
362 32003e?avr32?05/06 at32ap7000 23.7.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchron ization signals. the frame sync output selection (fsos) field in the receive frame mode regi ster (rfmr) and in the transmit frame mode register (tfmr) are used to select the required waveform. ? programmable low or high levels during data transfer are supported. ? programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in rfmr and tfmr pro- grams the length of the pulse, from 1 bit time up to 16 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection (period) field in rcmr and tcmr. 23.7.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding register in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in rfmr/tfmr. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the re ceive sync holding register thr ough the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in tfmr is set. if the fr ame sync length is equal to or lower than the delay between the start event and the actual dat a transmission, the normal transmission has pri- ority and the data contained in the transmit sync holding register is transferred in the transmit register, then shifted out. 23.7.5.2 frame sync edge detection the frame sync edge detection is programmed by the fsedge field in rfmr/tfmr. this sets the corresponding flags rxsyn/txsyn in the ssc status register (sr) on frame synchro edge detection (signals rf/tf).
363 32003e?avr32?05/06 at32ap7000 23.7.6 receive compare modes figure 23-12. receive compare modes 23.7.6.1 compare functions compare 0 can be one start event of the receiver. in this case, the receiver compares at each new sample the last fslen bits received at the fslen lower bit of the data contained in the compare 0 register (rc0r). when this start ev ent is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continu- ously until compare 1 occurs. this selecti on is done with the bit (stop) in rcmr. 23.7.7 data format the data framing format of both the transmitter and the receiver are programmable through the transmitter frame mode register (tfmr) and the receiver frame mode register (rfmr). in either case, the user can independently select: ? the event that starts the data transfer (start) ? the delay in number of bit periods between the start event and the first data bit ( sttdly ) ? the length of the data (datlen) ? the number of data to be transferred for each start event (datnb). ? the length of synchronization transferred for each start event (fslen) ? the bit sense: most or lowest significant bit first (msbf). additionally, the transmitter can be used to tr ansfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in tfmr. cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen
364 32003e?avr32?05/06 at32ap7000 figure 23-13. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. table 23-3. data frame registers transmitter receiver field length comment tfmr rfmr datlen up to 32 size of word tfmr rfmr datnb up to 16 number of words transmitted in frame tfmr rfmr msbf most significant bit first tfmr rfmr fslen up to 16 size of synchro data register tfmr datdef 0 or 1 data default value ended tfmr fsden enable send tshr tcmr rcmr period up to 512 frame size tcmr rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef
365 32003e?avr32?05/06 at32ap7000 figure 23-14. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 23-15. receive frame format in continuous mode note: 1. sttdly is set to 0. 23.7.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in rfmr. in this case, rd is connected to td, rf is con- nected to tf and rk is connected to tk. 23.7.9 interrupt most bits in sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ier (interr upt enable register) and idr (int errupt disable register) these registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in imr (interrupt mask register), which controls the generation of inter- rupts by asserting the ssc interrupt line connected to the interrupt controller. datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
366 32003e?avr32?05/06 at32ap7000 figure 23-16. interrupt block diagram 23.8 ssc application examples the ssc can support several serial communica tion modes used in audio or high speed serial links. some standard applications are shown in t he following figures. all se rial link applications supported by the ssc are not listed here. figure 23-17. audio application block diagram ssc_imr pdc interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync txbufe endtx rxbuff endrx clear ssc_ier ssc_idr ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb
32003e?avr32?05/06 codec application block diagram time slot application block diagram ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
32003e?avr32?05/06 register mapping 0x0 control register cr write ? 0x4 clock mode register cmr read/write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register rcmr read/write 0x0 0x14 receive frame mode register rfmr read/write 0x0 0x18 transmit clock mode register tcmr read/write 0x0 0x1c transmit frame mode register tfmr read/write 0x0 0x20 receive holding register rhr read 0x0 0x24 transmit holding register thr write ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register rshr read 0x0 0x34 transmit sync. holding register tshr read/write 0x0 0x38 receive compare 0 register rc0r read/write 0x0 0x3c receive compare 1 register rc1r read/write 0x0 0x40 status register sr read 0x000000cc 0x44 interrupt enable register ier write ? 0x48 interrupt disable register idr write ? 0x4c interrupt mask register imr read 0x0 0x50-0xfc reserved ? ? ? 0x100- 0x124 reserved for peripheral data controller (pdc) ? ? ?
32003e?avr32?05/06 cr write-only 0: no effect. 1: enables receive if rxdis is not set. 0: no effect. 1: disables receive. if a character is currently being re ceived, disables at end of current character reception. 0: no effect. 1: enables transmit if txdis is not set. 0: no effect. 1: disables transmit. if a character is currently being transmitted, disables at end of current character transmission. 0: no effect. 1: performs a software reset. has priority on any other bit in cr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst?????txdistxen 76543210 ??????rxdisrxen
32003e?avr32?05/06 cmr read/write 0: the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div
32003e?avr32?05/06 rcmr read/write 0: the data inputs (data and frame sync signals) are sample d on receive clock falling edge . the frame sync signal out- put is shifted out on receive clock rising edge. 1: the data inputs (data and frame sync signals) are sample d on receive clock rising edge. the frame sync signal out- put is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 stddly 15 14 13 12 11 10 9 8 ? ? ? stop start 76543210 ckg cki cko cks 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved 0x0 none input-only 0x1 continuous receive clock output 0x2 receive clock only during data transfers output 0x3-0x7 reserved
32003e?avr32?05/06 0: after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period sig nal is generated each 2 x (period+1) receive clock. 0x0 none, continuous clock 0x1 receive clock enabled only if rf low 0x2 receive clock enabled only if rf high 0x3 reserved 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 transmit start 0x2 detection of a low level on rf signal 0x3 detection of a high level on rf signal 0x4 detection of a falling edge on rf signal 0x5 detection of a rising edge on rf signal 0x6 detection of any level change on rf signal 0x7 detection of any edge on rf signal 0x8 compare 0 0x9-0xf reserved
32003e?avr32?05/06 rfmr read/write 0: forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the receiver. if datlen is lower or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. 0: normal operating mode. 1: rd is driven by td, rf is driven by tf and tk drives rk. 0: the lowest significant bit of the data register is sampled first in the bit stream. 1: the most significant bit of the data register is sampled first in the bit stream. this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). this field defines the length of the receive frame sync signal and the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also deter- mines the length of the sampled data to be compared to the compare 0 or compare 1 register. pulse length is equal to (fslen + 1) receive clock periods. th us, if fslen is 0, the receive frame sync signal is gener- ated during one receive clock period. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 msbf ? loop datlen
32003e?avr32?05/06 determines which edge on frame sy nc will generate the in terrupt rxsyn in the ssc status register. 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined 0x0 positive edge detection 0x1 negative edge detection
32003e?avr32?05/06 tcmr read/write 0: the data outpu ts (data and frame sync signals) are shifted out on tr ansmit clock falling edge . the frame sync signal input is sampled on transmit clock rising edge. 1: the data outputs (data and frame sync signals) are shifted out on transmit clock rising edge. the frame sync signal input is sampled on tran smit clock falling edge. cki affects only the transmit clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ckg cki cko cks 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved 0x0 none input-only 0x1 continuous transmit clock output 0x2 transmit clock only during data transfers output 0x3-0x7 reserved
32003e?avr32?05/06 if sttdly is not 0, a delay of sttdly clock cycles is inse rted between the start event and the actual start of transmission of data. when the transmitter is programmed to start sync hronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emit- ted instead of the end of tag. this field selects the divider to apply to the selected transmi t clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. 0x0 none, continuous clock 0x1 transmit clock enabled only if tf low 0x2 transmit clock enabled only if tf high 0x3 reserved 0x0 continuous, as soon as a word is written in the thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8 - 0xf reserved
32003e?avr32?05/06 tfmr read/write 0: forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the transmit. if datlen is lower or equal to 7, data transfers are bytes, if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. this bit defines the level driven on the td pin while out of tran smission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. 0: the lowest significant bit of the data register is shifted out first in the bit stream. 1: the most significant bit of the data register is shifted out first in the bit stream. this field defines the number of data words to be transferred after each transfer start, which is equal to (datnb +1). this field defines the length of the transmit frame sync sig nal and the number of bits shifted out from the transmit sync data register if fsden is 1. pulse length is equal to (fslen + 1) transmit clock periods, i.e., the pulse length can range from 1 to 16 transmit clock periods. if fslen is 0, the transmit frame sync signal is generated during one transmit clock period. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 m s b f ? dat d e f dat l e n
32003e?avr32?05/06 0: the td line is driven with the default va lue during the transmi t frame sync signal. 1: tshr value is shifted out during the tran smission of the transmi t frame sync signal. determines which edge on frame sync will gene rate the interrupt tx syn (status register). 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined 0x0 positive edge detection 0x1 negative edge detection
32003e?avr32?05/06 rhr read-only right aligned regardless of the number of data bits defined by datlen in rfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat
32003e?avr32?05/06 thr write-only right aligned regardless of the number of data bits defined by datlen in tfmr. 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
32003e?avr32?05/06 rshr read-only 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat
32003e?avr32?05/06 tshr read/write 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
32003e?avr32?05/06 rc0r read/write 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp0 76543210 cp0
32003e?avr32?05/06 rc1r read/write 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp1 76543210 cp1
32003e?avr32?05/06 sr read-only 0: data has been loaded in thr and is waiting to be loaded in the transmit shift register (tsr). 1: thr is empty. 0: data remains in thr or is currently transmitted from tsr. 1: last data written in thr has been loaded in tsr and last data loaded in tsr has been transmitted. 0: the register tcr has not reached 0 since the last write in tcr or tncr. 1: the register tcr has reached 0 since the last write in tcr or tncr. 0: tcr or tncr have a value other than 0. 1: both tcr and tncr have a value of 0. 0: rhr is empty. 1: data has been received and loaded in rhr. 0: no data has been loaded in rhr while previous data has not been read since the last read of the status register. 1: data has been loaded in rhr while previous data has not yet been read since the last read of the status register. 0: data is written on the receive counter register or receive ne xt counter register. 1: end of pdc transfer when receive counter register has arrived at zero. 0: rcr or rncr have a value other than 0. 1: both rcr and rncr have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????rxentxen 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
32003e?avr32?05/06 0: a compare 0 has not occurred since the last read of the status register. 1: a compare 0 has occurred since the last read of the status register. 0: a compare 1 has not occurred since the last read of the status register. 1: a compare 1 has occurred since the last read of the status register. 0: a tx sync has not occurred since the last read of the status register. 1: a tx sync has occurred since the last read of the status register. 0: an rx sync has not occurred since the last read of the status register. 1: an rx sync has occurred since the last read of the status register. 0: transmit is disabled. 1: transmit is enabled. 0: receive is disabled. 1: receive is enabled.
32003e?avr32?05/06 ier write-only 0: no effect. 1: enables the transmit ready interrupt. 0: no effect. 1: enables the transmit empty interrupt. 0: no effect. 1: enables the end of transmission interrupt. 0: no effect. 1: enables the transmit buffer empty interrupt 0: no effect. 1: enables the receive ready interrupt. 0: no effect. 1: enables the receive overrun interrupt. 0: no effect. 1: enables the end of reception interrupt. 0: no effect. 1: enables the receive buffer full interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
32003e?avr32?05/06 0: no effect. 1: enables the compare 0 interrupt. 0: no effect. 1: enables the compare 1 interrupt. 0: no effect. 1: enables the tx sync interrupt. 0: no effect. 1: enables the rx sync interrupt.
32003e?avr32?05/06 idr write-only 0: no effect. 1: disables the transmit ready interrupt. 0: no effect. 1: disables the transmit empty interrupt. 0: no effect. 1: disables the end of transmission interrupt. 0: no effect. 1: disables the transmit buffer empty interrupt. 0: no effect. 1: disables the rece ive ready interrupt. 0: no effect. 1: disables the receive overrun interrupt. 0: no effect. 1: disables the end of reception interrupt. 0: no effect. 1: disables the receiv e buffer full interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
32003e?avr32?05/06 0: no effect. 1: disables the compare 0 interrupt. 0: no effect. 1: disables the compare 1 interrupt. 0: no effect. 1: disables the tx sync interrupt. 0: no effect. 1: disables the rx sync interrupt.
32003e?avr32?05/06 imr read-only 0: the transmit ready interrupt is disabled. 1: the transmit ready interrupt is enabled. 0: the transmit empty interrupt is disabled. 1: the transmit empty interrupt is enabled. 0: the end of transmission interrupt is disabled. 1: the end of transmission interrupt is enabled. 0: the transmit buffer empty interrupt is disabled. 1: the transmit buffer empty interrupt is enabled. 0: the receive ready interrupt is disabled. 1: the receive ready interrupt is enabled. 0: the receive overrun interrupt is disabled. 1: the receive overrun interrupt is enabled. 0: the end of reception interrupt is disabled. 1: the end of reception interrupt is enabled. 0: the receive buffer full interrupt is disabled. 1: the receive buffer full interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuf endrx ovrun rxrdy txbufe endtx txempty txrdy
32003e?avr32?05/06 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled. 0: the compare 1 interrupt is disabled. 1: the compare 1 interrupt is enabled. 0: the tx sync interrupt is disabled. 1: the tx sync interrupt is enabled. 0: the rx sync interrupt is disabled. 1: the rx sync interrupt is enabled.
393 32003e?avr32?05/06 at32ap7000 24. universal synchronous/asynchro nous receiver/transmitter (usart) rev: 6089h 24.1 features ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multidrop mode with address generation and detection ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo ? supports connection of two peripheral dma controller channels (pdc) ? offers buffer transfer without processor intervention 24.2 description the universal synchronous asynchronous rece iver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programma- ble (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time-out enables handling variable-length frames and the transmitt er timeguard facilitates communications with slow remote devices. multidrop communications are also supported through address bit han- dling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshaking feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor.
394 32003e?avr32?05/06 at32ap7000 24.3 block diagram figure 24-1. usart block diagram peripheral dma controller channel channel interrupt controller receiver usart interrupt rxd txd sck usart pio controller cts rts transmitter baud rate generator user interface power manager mck slck div mck/div apb
395 32003e?avr32?05/06 at32ap7000 24.4 application block diagram figure 24-2. application block diagram 24.5 i/o lines description table 24-1. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input cts clear to send input low rts request to send output low smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp
396 32003e?avr32?05/06 at32ap7000 24.6 product dependencies 24.6.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. 24.6.2 power management the usart is not continuously clocked. the programmer must ensure that the usart clock is enabled in the power manager (pm) before using the usart. however, if the application does not require usart operations, the usart clock can be stopped when not needed and be restarted late r. in this case, the usart will resume its operations where it left off. master clock (mck) in the usart description is the clock fo r the apb-bus to which th e usart is connected. 24.6.3 interrupt the usart interrupt line is connected on one of the internal sources of the interrupt controller. using the usart interrupt requires the interrupt controller to be programmed first.
397 32003e?avr32?05/06 at32ap7000 24.7 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: ? 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication ? rs485 with driver control signal ? iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? infrared irda modulation and demodulation ? test modes ? remote loopback, local loopback, automatic echo 24.7.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (mr) between: ? the master clock mck ? a division of the master clock, the divider being product dependent, but generally set to 8 ? the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (brgr). if cd is programmed at 0, the baud rate gener- ator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive.
398 32003e?avr32?05/06 at32ap7000 if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck. figure 24-3. baud rate generator if the usart is programmed to operate in as ynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest possi- ble clock and that over is programmed at 1. table 24-2 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- = table 24-2. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70%
399 32003e?avr32?05/06 at32ap7000 the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. the baud rate generator previously defined is su bject to the following limitation: the output fre- quency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate c hanges by a fraction of the reference source clock. this fractional part is programmed with the fp field in the baud rate generator register (brgr). if fp is not 0, the fractional part is acti vated. the resolution is one eighth of the clock divider. this feature is only available when usi ng usart functional mode. the fractional baud rate is calculated using the following formula: 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% 70 000 000 38 400 113.93 114 38 377.19 0.06% table 24-2. baud rate example (over = 0) (continued) source clock expected baud rate calculation result cd actual baud rate error baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? = baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - =
400 32003e?avr32?05/06 at32ap7000 the modified architecture is presented below: figure 24-4. fractional baud rate generator if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. the iso7816 specification defines the bit rate with the following formula: where: ? b is the bit rate ? di is the bit-rate adjustment factor mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - = b di fi ----- - f =
401 32003e?avr32?05/06 at32ap7000 ? fi is the clock frequency division factor ? f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 24-3 . fi is a binary value encoded on a 4-bi t field, named fi, as represented in table 24-4 . table 24-5 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, th e clock selected by the usclks field in the mode register (mr) is first divided by the valu e programmed in the field cd in the baud rate generator register (brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in mr. this clock is then divided by the value progra mmed in the fi_di_ratio field in the fi_di_ratio register (fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 24-5 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. table 24-3. binary and decimal values for d di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal)1 2 4 8 163212 20 table 24-4. binary and decimal values for f fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 24-5. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
402 32003e?avr32?05/06 at32ap7000 figure 24-5. elementary time unit (etu) 24.7.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx re spectively, in the control register (cr). the reset commands have the same effect as a hardware reset on the corresponding logic. regardless of what the receiver or the transmi tter is performing, the communication is immedi- ately stopped. the user can also independently disable the receiv er or the transmitter by setting rxdis and txdis respectively in cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (thr). if a time- guard is programmed, it is handled normally. 24.7.3 synchronous and asynchronous modes the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 da ta bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode9 bit in the mode register (mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in mr configures wh ich data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less signi ficant bit is sent first. the number of stop bits is selected by the nbstop field in mr. the 1.5 stop bit is supported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
403 32003e?avr32?05/06 at32ap7000 figure 24-6. character transmit the characters are sent by writing in the tr ansmit holding register (thr). the transmitter reports two status bits in the channel status register (csr): txrdy (transmitter ready), which indicates that thr is empt y and txempty, which indicates that all the characters written in thr have been processed. when the current character processing is completed, the last character written in thr is transferred into the shift register of the transmitter and thr becomes empty, thus txrdy raises. both txrdy and txempty bits are low since the transmitter is disabled. writing a character in thr while txrdy is active has no effect and the written character is lost. figure 24-7. transmitter status when the manchester encoder is in use, c haracters transmitted through the usart are encoded based on biphase manchester ii format. to enable this mode, set the man field in the mr register to 1. depending on polarity configurat ion, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. thus, a transition always occurs at the midpoint of each bit time. it consumes more bandwidth than the original nrz signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. an example of manchester encoded sequence is: th e byte 0xb1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. figure 24-8 illustrates this coding scheme. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
404 32003e?avr32?05/06 at32ap7000 figure 24-8. nrz to manchester encoding the manchester encoded character can also be enc apsulated by adding both a configurable preamble and a start frame delimiter pattern. depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. if the preamble length is set to 0, the preamble waveform is not generated prior to any character. the preamble pattern is chosen among the following sequences: all_one, all_zero, one_zero or zero_one, writing the field tx_pp in the man register, the field tx_pl is used to configure the preamble length. figure 24-9 illustrates and defines the valid patterns. to improve flexibility, the encodi ng scheme can be configured using the tx_mpol field in the man register. if the tx_mpol field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. if the tx_mpol field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. figure 24-9. preamble patterns, default polarity assumed a start frame delimiter is to be configured using the onebit field in the mr register. it consists of a user-defined pattern that indicates the beginning of a valid data. figure 24-10 illustrates these patterns. if the start frame delimiter, also known as start bit, is one bit, (onebit at 1), a logic zero is manchester encoded and indicates that a new character is being sent serially on the line. if the start frame delimiter is a synchronization pattern also referred to as sync (onebit at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. the sync waveform is in itself an invalid manchester waveform as the transition occurs at the nrz encoded data manchester encoded data default polarity 10110001 txd txdn manchester encoded data default polarity d ifferential output txd txdn sfd sfdn data datan 8 bit width "all_one" preamble manchester encoded data default polarity d ifferential output txd txdn sfd sfdn data datan 8 bit width "all_zero" preamble manchester encoded data default polarity d ifferential output txd txdn sfd sfdn data datan 8 bit width "zero_one" preamble
405 32003e?avr32?05/06 at32ap7000 middle of the second bit time. two distinct sync patterns are used: the command sync and the data sync. the command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. if the sync field in the mr register is set to 1, the next character is a command. if it is set to 0, the next character is a data. when direct memory access is used, the sync field can be immediately updated with a modified character located in memory. to enable this mode, var_sync field in mr register must be set to 1. in this case, the sync field in mr is bypassed and the sync configuration is held in the txsynh in the thr register. the usart character format is modified and includes sync information. figure 24-10. start frame delimiter drift compensation is available only in 16x oversampling mode. an ha rdware recovery system allows a larger clock drift. to enable the hardwa re system, the bit in th e man register must be set. if the rxd edge is one 16x clock cycle from the expected edge, this is considered as nor- mal jitter and no corrective actions is taken. if the rxd event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. if the rxd event is between 2 and 3 clock cycles after the expected edge, then the current period is length- ened by one clock cycle. these intervals are considered to be drift and so corrective actions are automatically taken. manchester encoded data default polarity differential output txd txdn sfd sfdn data datan one bit start frame delimiter preamble length is set to 0 manchester encoded data default polarity differential output txd txdn sfd sfdn data datan command sync start frame delimiter sfd
406 32003e?avr32?05/06 at32ap7000 figure 24-11. bit resynchronization if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl, mo de9, msbf and par. the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiv er and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchroni- zation can also be accomplished when the transmitter is operating with one stop bit. figure 24-12 and figure 24-13 illustrate start detection and character reception when usart operates in asynchronous mode. rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error
407 32003e?avr32?05/06 at32ap7000 figure 24-12. asynchronous start detection figure 24-13. asynchronous character reception when the man field in mr register is set to 1, the manchester decoder is enabled. the decoder performs both preamble and start frame delimiter detection. one input line is dedicated to manchester encoded input data. an optional preamble sequence can be defined, it s length is user-defined and totally indepen- dent of the emitter side. use rx_pl in man regi ster to configure the length of the preamble sequence. if the length is set to 0, no preamble is detected and the function is disabled. in addi- tion, the polarity of the input stream is programmable with rx_mpol field in man register. depending on the desired application the preamble pattern matching is to be defined via the rx_pp field in man. see figure 24-9 for available preamble patterns. unlike preamble, the start frame delimiter is shared between manchester encoder and decoder. so, if onebit field is set to 1, only a zero encoded manchester can be detected as a valid start frame delimiter. if onebit is set to 0, only a sync pattern is detected as a valid start frame delimiter. decoder operates by detecting transition on incoming stream. if rxd is sampled dur- ing one quarter of a bit time at zero, a start bit is detected. see figure 24-14 .. the sample pulse rejection mechanism applies. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
408 32003e?avr32?05/06 at32ap7000 figure 24-14. asynchronous star t bit detection the receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. if a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. if the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.the minimum time threshold to estimate the bit value is three quarters of a bit time. if a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into nrz data and passed to usart for processing. figure 24-15 illustrates manchester pattern mismatch. when incoming data stream is passed to the usart, the receiver is also able to detect manchester code vi olation. a code violation is a lack of transition in the middle of a bit cell. in this case, mane flag in csr register is raised. it is cleared by writing the control register (cr) with the rststa bit at 1. see figure 24-16 for an example of manchester error detection during data phase. figure 24-15. preamble pattern mismatch figure 24-16. manchester error flag when the start frame delimiter is a sync pattern (onebit field at 0), both command and data delimiter are supported. if a valid sync is detec ted, the received character is written as rxchr manchester encoded data default polarity differential output txd txdn sampling clock (16 x) start detection edge synchronization manchester encoded data default polarity differential output txd txdn sfd sfdn data datan preamble mismatch invalid pattern preamble mismatch manchester coding error preamble mismatch differential error manchester encoded data default polarity differential output txd txdn sfd sfdn preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully entering usart character area
409 32003e?avr32?05/06 at32ap7000 field in the rhr register and the rxsynh is updated. rxchr is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. this mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. the decoder does not perform pipelining of incoming data stream. thus when unipolar mode is enabled, it is highly recommended to assure consistency between start frame delimiter (or pre- amble) waveform and default active level. example: when the line idles, the logic level is one; to synchronize and avoid confusion, a ze ro-to-one transition is mandatory. radio interface: manchester encoded usart application this section describes low data rate rf transmission systems and their integration with a manchester encoded usart. these systems are based on transmitter and receiver ics that support ask and fsk modulation schemes. the goal is to perform full duplex radio transmissi on of characters using two different frequency carriers. see the configuration in figure 24-17 . figure 24-17. manchester encoded characters rf transmission the usart module is configured as a manches ter encoder/decoder. it is also highly recom- mended to use pio interface to access rf receiv er configuration registers. looking at the downstream communication channel, manchester encoded characters are serially sent to the rf emitter. this may also include a user defined preamble and a start frame delimiter. mostly, preamble is used in the rf receiver to distinguish between a valid data from a transmitter and signals due to noise. the manchester stream is then modulated. see figure 24-18 for an exam- ple of ask modulation scheme. when a logic one is sent to the ask modulator, the power amplifier, referred to as pa, is enabled and transmits an rf signal at downstream frequency. when a logic zero is transmitted, the rf signal is turned off. if the fsk modulator is activated, two different frequencies are used to transmit dat a. when a logic 1 is sent, the modulator out- puts an rf signal at frequency f0 and switches to f1 if the data sent is a 0. see figure 24-19 . lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier
410 32003e?avr32?05/06 at32ap7000 from the receiver side, another carrier frequency is used. the rf receiver performs a bit check operation examining demodulated data stream. if a valid pattern is detected, the receiver switches to receiving mode. the demodulated stream is sent to the manchester decoder. because of bit checking inside rf ic, the data transferred to the microcontroller is reduced by a user-defined number of bits. the manchester preamble length is to be defined in accordance with the rf ic configuration. figure 24-18. ask modulator output figure 24-19. fsk modulator output 24.7.3.7 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a lo w level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 24-20 illustrates a character rec eption in synchronous mode. manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 10 0 1 manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 10 0 1
411 32003e?avr32?05/06 at32ap7000 figure 24-20. synchronous mode character reception 24.7.3.8 receiver operations when a character reception is completed, it is transferred to the receive holding register (rhr) and the rxrdy bit in the st atus register (csr) rises. if a character is completed while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into rhr and overwrites the previous one. the ovre bit is cleared by writing the control register (cr) with the rststa (reset status) bit at 1. figure 24-21. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
412 32003e?avr32?05/06 at32ap7000 24.7.3.9 parity the usart supports five parity modes selected by programming the par field in the mode register (mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 413 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a num- ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sam- pled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0. if the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 24-6 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (csr). the pare bit can be cleared by writing the control register (cr) with the rst- sta bit at 1. figure 24-22 illustrates the parity bit status setting and clearing. table 24-6. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
413 32003e?avr32?05/06 at32ap7000 figure 24-22. parity error 24.7.3.10 multidrop mode if the par field in the mode register (mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentia tes the data characters and the address charac- ters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bit set) when senda is written to cr. in this case, the next byte written to thr is transmitted as an address. any character written in thr without having written the command senda is transmitted normally with the parity at 0. 24.7.3.11 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard regis- ter (ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit peri- ods programmed in tg in addition to the number of stop bits. as illustrated in figure 24-23 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in thr. txempty remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
414 32003e?avr32?05/06 at32ap7000 figure 24-23. timeguard operations table 24-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 24.7.3.12 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeou t bit in csr remains at 0. otherwise, the receiver loads a 16-bit counter with the value programmed in to. this counter is decremented at each bit period and reloaded ea ch time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. the user can either: d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 24-7. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
415 32003e?avr32?05/06 at32ap7000 ? obtain an interrupt when a time-out is detected after having received at least one character. this is performed by writing the control regist er (cr) with the sttto (start time-out) bit at 1. ? obtain a periodic interrupt while no character is received. this is performed by writing cr with the retto (reload and start time-out) bit at 1. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so t hat a user time-out can be handled, for example when no key is pressed on a keyboard. figure 24-24 shows the block diagram of the receiver time-out feature. figure 24-24. receiver time-out block diagram table 24-8 gives the maximum time-out period for some standard baud rates. table 24-8. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
416 32003e?avr32?05/06 at32ap7000 24.7.3.13 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (cr) with the rststa bit at 1. figure 24-25. framing error status 24.7.3.14 transmit break the user can request the transmitter to generate a break condition on the txd line. a break con- dition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift reg- ister or in thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, t he character is first completed be fore the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing cr with the both sttbrk and stpbrk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte writ- ten into the transmit holding re gister while a break is pending, but not started, is ignored. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
417 32003e?avr32?05/06 at32ap7000 after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 24-26 illustrates the effect of both the start break (sttbrk ) and stop break (stpbrk) commands on the txd line. figure 24-26. break transmission 24.7.3.15 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in csr. this bit may be cleared by writing the control register (cr) with the bit rststa at 1. an end of receive break is detected by a high leve l for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 24.7.3.16 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 24-27 . figure 24-27. connection with a remote device for hardware handshaking d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break usart txd cts remote device rxd txd rxd rts rts cts
418 32003e?avr32?05/06 at32ap7000 setting the usart to operate with hardware handshaking is performed by writing the mode field in the mode register (mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires usin g the pdc channel for reception. the transmitter can handle hardware handshaking in any case. figure 24-28 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) com- ing from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled , the rts falls, indicating to the remote device that it can start transmitt ing. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 24-28. receiver behavior when operating with hardware handshaking figure 24-29 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitt er. if a character is being processi ng, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 24-29. transmitter behavior when operating with hardware handshaking 24.7.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the mode field in the mode regis- ter (mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. 24.7.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clo ck provided to the remote device (see ?baud rate generator? on page 397 ). rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd
419 32003e?avr32?05/06 at32ap7000 the usart connects to a smart card as shown in figure 24-30 . the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is direct ed to the input of the receiver. the usart is con- sidered as the master of the communication as it generates the clock. figure 24-30. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, ev en parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to ?usart mode register? on page 430 and ?par: parity type? on page 431 . the usart cannot operate concurrently in both receiver and transmitter modes as the commu- nication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this for- mat and the user has to perform an exclusive or on the data before writing it in the transmit holding register (thr) or after reading it in the receive holding register (rhr). 24.7.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 24-31 . if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 24-32 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (rhr). it appropriately sets the pare bit in the status register (sr) so that the software can handle the error. smart card sck clk txd i/o usart
420 32003e?avr32?05/06 at32ap7000 figure 24-31. t = 0 protocol without parity error figure 24-32. t = 0 protocol with parity error 24.7.4.3 receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (ner) register. the nb_errors field ca n record up to 255 errors. reading ner auto- matically clears the nb_errors field. 24.7.4.4 receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inack bit is set in the status register (sr). the inack bit can be cleared by writing the control re gister (cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous receiv ed character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. 24.7.4.5 transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (mr) at a value higher than 0. each character can be transmitted up to eight times; the firs t transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in csr can be cleared by writing the control register with the rsit bit at 1. 24.7.4.6 disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (mr). the maximum num- ber of nack transmitted is programmed in the max_iteration field. as soon as d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
421 32003e?avr32?05/06 at32ap7000 max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 24.7.4.7 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the par e bit in the channel status register (csr). 24.7.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 24-33 . the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting the mo de field in the mode register (mr) to the value 0x8. the irda filter register (if) allows configuring the demodulator filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are acces- sible. note that the modulator and the demodulator are activated. figure 24-33. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 24.7.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 24-9 . irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter table 24-9. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s
422 32003e?avr32?05/06 at32ap7000 figure 24-34 shows an example of character transmission. figure 24-34. irda modulation 24.7.5.2 irda baud rate table 24-10 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s table 24-9. irda pulse duration baud rate pulse duration (3/16) bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 24-10. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77
423 32003e?avr32?05/06 at32ap7000 24.7.5.3 irda demodulator the demodulator is based on the irda receive filter co mprised of an 8-bit down counter which is loaded with the value pr ogrammed in if. when a falling edge is detected on the rxd pin, the fil- ter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 24-35 illustrates the operations of the irda demodulator. figure 24-35. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 24-10. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 driven low during 16 baud rate clock cycles 65432 0 pulse accepted counter value
424 32003e?avr32?05/06 at32ap7000 24.7.6 rs485 mode the usart features the rs485 mode to enable li ne driver control. while operating in rs485 mode, the usart behaves as though in asynch ronous or synchronous mode and configuration of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 24-36 . figure 24-36. typical connection to a rs485 bus the usart is set in rs485 mode by programming the mode field in the mode register (mr) to the value 0x1. the rts pin is at a level inverse to the txempt y bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character com- pletion. figure 24-37 gives an example of the rts waveform during a character transmission when the timeguard is enabled. figure 24-37. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
425 32003e?avr32?05/06 at32ap7000 24.7.7 test modes the usart can be programmed to operate in three different test modes. the internal loopback capability allows on-boar d diagnostics. in the loopback mode the usart interface pins are dis- connected or not and reconfigured for loopback internally or externally. 24.7.7.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 24-38. normal mode configuration 24.7.7.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 24-39 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 24-39. automatic echo mode configuration 24.7.7.3 local loopback mode local loopback mode c onnects the output of the transmitter directly to the input of the receiver, as shown in figure 24-40 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 24-40. local loopback mode configuration receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
426 32003e?avr32?05/06 at32ap7000 24.7.7.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 24-41 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by-bit retransmission. figure 24-41. remote loopback mode configuration receiver transmitter rxd txd 1
427 32003e?avr32?05/06 at32ap7000 24.8 usart user interface table 24-11. usart memory map offset register name access reset state 0x0000 control register cr write-only ? 0x0004 mode register mr read/write ? 0x0008 interrupt enable register ier write-only ? 0x000c interrupt disable register idr write-only ? 0x0010 interrupt mask register imr read-only 0x0 0x0014 channel status register csr read-only ? 0x0018 receiver holding register rhr read-only 0x0 0x001c transmitter holding register thr write-only ? 0x0020 baud rate generator register brgr read/write 0x0 0x0024 receiver time-out register rtor read/write 0x0 0x0028 transmitter timeguard register ttgr read/write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio register fidi read/write 0x174 0x0044 number of errors register ner read-only ? 0x0048 reserved - ? ? 0x004c irda filter register if read/write 0x0 0x0050 manchester encoder decoder register man read/write 0x0 0x5c - 0xfc reserved ? ? ? 0x100 - 0x128 reserved for pdc registers ? ? ?
428 32003e?avr32?05/06 at32ap7000 24.8.1 usart control register name: cr access type: write-only ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre and rxbrk in the csr. ? sttbrk: start break 0: no effect. 1: starts transmission of a break after t he characters present in thr and the transmit shift register have been transmit- ted. no effect if a break is already being transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsen?? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
429 32003e?avr32?05/06 at32ap7000 ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttto: start time-out 0: no effect 1: starts waiting for a character before clocking the time-out counter. ? senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the thr is sent with the address bit set. ? rstit: reset iterations 0: no effect. 1: resets iteration in csr. no e ffect if the iso7816 is not enabled. ? rstnack: reset non acknowledge 0: no effect 1: resets nack in csr. ? retto: rearm time-out 0: no effect 1: restart time-out ? rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. ? rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1.
430 32003e?avr32?05/06 at32ap7000 24.8.2 usart mode register name: mr access type: read/write ?mode ? usclks: clock selection ? chrl: character length. 31 30 29 28 27 26 25 24 onebit ? man filter ? max_iteration 23 22 21 20 19 18 17 16 ? var_sync dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks mode mode mode of the usart 0000normal 0001rs485 0 0 1 0 hardware handshaking 0011reserved 0 1 0 0 is07816 protocol: t = 0 0101reserved 0 1 1 0 is07816 protocol: t = 1 0111reserved 1000irda 11xxreserved usclks selected clock 00mck 01mck / div 10reserved 11sck chrl character length 0 0 5 bits
431 32003e?avr32?05/06 at32ap7000 ? sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. ? par: parity type ? nbstop: number of stop bits ? chmode: channel mode ? msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. ? cklo: clock output select 0: the usart does not drive the sck pin. 0 1 6 bits 1 0 7 bits 1 1 8 bits par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 1 0 x no parity 1 1 x multidrop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input.. 1 1 remote loopback. rxd pin is internally connected to the txd pin.
432 32003e?avr32?05/06 at32ap7000 1: the usart drives the sck pin if usclks does not select the external clock sck. ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is r eached, no additional nack is sent on the iso line. the flag iteration is asserted. ? var_sync: variable synchronization of command/data sync start frame delimiter 0: user defined configuration of command or data sync field depending on sync value. 1: the sync field is updated when a ch aracter is written into thr register. ? max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). ? man: manchester encoder/decoder enable 0: manchester encoder/decoder are disabled. 1: manchester encoder/decoder are enabled. ? onebit: start frame delimiter selector 0: start frame delimiter is command or data sync. 1: start frame delimiter is one bit.
433 32003e?avr32?05/06 at32ap7000 24.8.3 usart interrupt enable register name: ier access type: write-only ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? rxbrk: receiver break interrupt enable ? endrx: end of receive transfer interrupt enable ? endtx: end of transmit interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? iteration: iteration interrupt enable ? txbufe: buffer empty interrupt enable ? rxbuff: buffer full interrupt enable ? nack: non acknowledge interrupt enable ? ctsic: clear to send input change interrupt enable ? mane: manchester error interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
434 32003e?avr32?05/06 at32ap7000 24.8.4 usart interrupt disable register name: idr access type: write-only ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? rxbrk: receiver bre ak interrupt disable ? endrx: end of receive transfer interrupt disable ? endtx: end of transmit interrupt disable ? ovre: overrun error interrupt disable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? iteration: iteration interrupt disable ? txbufe: buffer empty interrupt disable ? rxbuff: buffer full interrupt disable ? nack: non acknowledge interrupt disable ? ctsic: clear to send input change interrupt disable ? mane: manchester error interrupt disable 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
435 32003e?avr32?05/06 at32ap7000 24.8.5 usart interrupt mask register name: imr access type: read-only ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? rxbrk: receiver break interrupt mask ? endrx: end of receive transfer interrupt mask ? endtx: end of transmit interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? iteration: iteration interrupt mask ? txbufe: buffer empty interrupt mask ? rxbuff: buffer full interrupt mask ? nack: non acknowledge interrupt mask ? ctsic: clear to send input change interrupt mask ? mane: manchester error interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
436 32003e?avr32?05/06 at32ap7000 24.8.6 usart channel status register name: csr access type: read-only ? rxrdy: receiver ready 0: no complete character has been received since the last read of rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1: at least one complete ch aracter has been re ceived and rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no character in the thr. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. ? endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. ? endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. ? pare: parity error 0: no parity error has been detected since the last rststa. 31 30 29 28 27 26 25 24 ???????manerr 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
437 32003e?avr32?05/06 at32ap7000 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since the last start time-out command or the time-out register is 0. 1: there has been a time-out since the last start time-out command. ? txempty: transmitter empty 0: there are characters in either thr or the trans mit shift register, or the transmitter is disabled. 1: there is at least one character in either thr or the transmit shift register. ? iteration: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rsit. 1: maximum number of repetitions has been reached since the last rsit. ? txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. ? rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from th e receive pdc channel is active. ? nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of csr. 1: at least one input change has been detected on the cts pin since the last read of csr. ? cts: image of cts input 0: cts is at 0. 1: cts is at 1. ? manerr: manchester error 0: no manchester error has been detected since the last rststa. 1: at least one manchester error has been detected since the last rststa.
438 32003e?avr32?05/06 at32ap7000 24.8.7 usart receive holding register name: rhr access type: read-only ? rxchr: received character last character received if rxrdy is set. ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????rxchr 76543210 rxchr
439 32003e?avr32?05/06 at32ap7000 24.8.8 usart transmit holding register name: thr access type: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????txchr 76543210 txchr
440 32003e?avr32?05/06 at32ap7000 24.8.9 usart baud rate generator register name: brgr access type: read/write ? cd: clock divider ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baudrate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? fp 15 14 13 12 11 10 9 8 cd 76543210 cd cd mode iso7816 mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
441 32003e?avr32?05/06 at32ap7000 24.8.10 usart receiver time-out register name: rtor access type: read/write ? to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to
442 32003e?avr32?05/06 at32ap7000 24.8.11 usart transmitter timeguard register name: ttgr access type: read/write ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
443 32003e?avr32?05/06 at32ap7000 24.8.12 usart fi di ratio register name: fidi access type: read/write reset value : 0x174 ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
444 32003e?avr32?05/06 at32ap7000 24.8.13 usart number of errors register name: ner access type: read-only ? nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
445 32003e?avr32?05/06 at32ap7000 24.8.14 usart manchester configuration register name: man access type: read/write ? tx_pl: transmitter preamble length 0: the transmitter preamble pattern generation is disabled 1 - 15: the preamble length is tx_pl x bit period ? tx_pp: transmitter preamble pattern ? tx_mpol: transmitter manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? rx_pl: receiver preamble length 0: the receiver preamble pattern detection is disabled 1 - 15: the detected preamble length is rx_pl x bit period ? rx_pp: receiver preamble pattern detected ? rx_mpol: receiver manchester polarity 0: logic zero is coded as a zero-to-one transition , logic one is coded as a one-to-zero transition. 31 30 29 28 27 26 25 24 ? drift ? rx_mpol ? ? rx_pp 23 22 21 20 19 18 17 16 ???? rx_pl 15 14 13 12 11 10 9 8 ? ? ? tx_mpol ? ? tx_pp 76543210 ???? tx_pl tx_pp preamble pattern default polari ty assumed (tx_mpol field not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero rx_pp preamble pattern de fault polarity assumed (rx_mpol fi eld not set) 0 0 all_one 0 1 all_zero 10zero_one 11one_zero
446 32003e?avr32?05/06 at32ap7000 1: logic zero is coded as a one-to-zero transition , logic one is coded as a zero-to-one transition. ? drift: drift compensation 0: the usart can not recover from an important clock drift 1: the usart can recover from clock drift. the 16x clock mode must be enabled.
447 32003e?avr32?05/06 at32ap7000 24.8.15 usart irda filter register name: if access type: read/write ? irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
448 32003e?avr32?05/06 at32ap7000 25. ac97 controller(ac97c) rev: 6144a 25.1 features ? compliant with ac97 2.2 component specification ? 2 independent comm unication channels ? codec channel, dedicated to the ac97 analog front end control and status monitoring ? 2 channels associated with dma controller interface for isochronous audio streaming transfer ? variable sampling rate ac 97 codec interface support ? one primary codec support ? independent input and output slot to channel assignment, several slots can be assigned to the same channel. ? channels support mono/stereo/multichann el samples of 10, 16, 18 and 20 bits. 25.2 description the ac97 controller is the hardware implementation of the ac97 digital controller (dc?97) com- pliant with ac97 component specification 2.2. the ac97 controller communicates with an audio codec (ac97) or a modem codec (mc?97) via the ac-link digital serial interface. all digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the ac-link protocol. the ac97 controller features a dma controller interface for audio streaming transfers. it also supports variable sampling rate and four puls e code modulation (pcm) sample resolutions of 10, 16, 18 and 20 bits.
449 32003e?avr32?05/06 at32ap7000 25.3 block diagram figure 25-1. functional block diagram ac97 channel a ac97c_cathr ac97c_carhr slot #3...12 ac97 codec channel ac97c_cothr ac97c_corhr slot #2 slot #1,2 ac97 channel b ac97c_cbthr ac97c_cbrhr slot #3...12 ac97 tag controller transmit shift register receive shift register receive shift register receive shift register receive shift register transmit shift register transmit shift register transmit shift register slot #0 slot #0,1 ac97 slot controller slot number 16/20 bits slot number sdi sclk sdo sync user interface mck clock domain bit clock domain ac97c interrupt mck apb interface m u x d e m u x
450 32003e?avr32?05/06 at32ap7000 25.4 pin name list the ac97 reset signal provided to the primary codec can be generated by a pio. 25.5 application block diagram figure 25-2. application block diagram table 25-1. i/o lines description pin name pin description type sclk 12.288-mhz bit-rate clock (referred as bitclk in ac-link spec) input sdi receiver data (referred as sdata_in in ac-link spec) input sync 48-khz frame indicator and synchronizer output sdo transmitter data (referred as sdata_out in ac-link spec) output ac 97 controller sdo sdi piox ac'97 primary codec sync sclk ac97_reset ac97_sync ac97_sdata_out ac97_bitclk ac-link ac97_sdata_in
451 32003e?avr32?05/06 at32ap7000 25.6 product dependencies 25.6.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ac97 controller receiver, the pio controller must be configured in order for the ac97c receiver i/o lines to be in ac97 controller peripheral mode. before using the ac97 controller transmitter, the pio controller must be configured in order for the ac97c transmitter i/o lines to be in ac97 controlle r peripheral mode. 25.6.2 power management the ac97 clock is generated by the power manager. before using the ac97, the programmer must ensure that the ac?97 clock is enabled in the power manager. in the ac97 description, master clock (mck) is the apb-bus clock, to which the ac97 is con- nected. it is important that that the mck cl ock frequency is higher than the sclk (bit clock) clock frequancy as signals that cross the two clock domains are re-synchronized. 25.6.3 interrupt the ac97 interface has an interrupt line connected to the interrupt controller. in order to handle interrupts, the interrupt controller must be programmed before configuring the ac97. all ac97 controller interrupts can be enabled/dis abled by writing to the ac97 controller inter- rupt enable/disable registers. each pending and unmasked ac97 controller interrupt will assert the interrupt line. the ac97 controller interrupt service routine can get the interrupt source in two steps: ? reading and anding ac97 controller interrupt mask register (imr) and ac97 controller status register (sr). ? reading ac97 controller channel x status register (cxsr).)
452 32003e?avr32?05/06 at32ap7000 25.7 functional description 25.7.1 protocol overview ac-link protocol is a bidirectional, fixed clock rate, serial digital stream. ac-link handles multiple input and output pulse code modulation pcm audio streams, as well as control register accesses employing a time division multiplexed (tdm) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots. figure 25-3. bidirectional ac-link fr ame with slot assignment slot # ac97fs tag cmd addr cmd data 0 ac97tx (controller output) ac97rx (codec output) pcm l front pcm r front line 1 dac pcm center pcm r surr pcm lfe line 2 dac hset dac io ctrl tag status addr status data pcm left line 1 dac pcm mic rsved rsved rsved line 2 adc hset adc io status 12 3 4 56 7 8 9 1011 12 pcm l surr pcm right table 25-2. ac-link output slots transmitted from the ac97c controller slot # pin description 0tag 1 command address port 2 command data port 3,4 pcm playback left/right channel 5 modem line 1 output channel 6, 7, 8 pcm center/left surround/right surround 9pcm lfe dac 10 modem line 2 output channel 11 modem handset output channel 12 modem gpio control channel table 25-3. ac-link input slots transmitte d from the ac97c controller slot # pin description 0tag 1 status address port 2 status data port 3,4 pcm playback left/right channel 5 modem line 1 adc 6 dedicated microphone adc 7, 8, 9 vendor reserved 10 modem line 2 adc 11 modem handset input adc 12 modem io status
453 32003e?avr32?05/06 at32ap7000 25.7.2 slot description 25.7.2.1 tag slot the tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. within tag slot, the first bit is a global bit that flags the entire frame validity. the next 12 bit positions sampled by the ac97 cont roller indicate which of the corresponding 12 time slots contain valid data. the slot?s last two bits (combined) called codec id, are used to dis- tinguish primary and secondary codec. the 16-bit wide tag slot of the output frame is automatically generated by the ac97 controller according to the transmit request of each channel and to the slotreq from the previous input frame, sent by the ac97 codec, in variable sample rate mode. 25.7.2.2 codec slot 1 the command/status slot is a 20-bit wide slot used to control features, and monitors status for ac97 codec functions. the control interface architecture supports up to sixty-four 16-bit wide read/write registers. only the even registers are currently defined and addressed. slot 1?s bitmap is the following: ? bit 19 is for read/write command, 1= read, 0 = write. ? bits [18:12] are for control register index. ? bits [11:0] are reserved. 25.7.2.3 codec slot 2 slot 2 is a 20-bit wide slot used to carry 16-bit wide ac97 codec control register data. if the cur- rent command port operation is a read, the entire slot time is stuffed with zeros. its bitmap is the following: ? bits [19:4] are the control register data ? bits [3:0] are reserved and stuffed with zeros. 25.7.2.4 data slots [3:12] slots [3:12] are 20-bit wide data slots, they usually carry audio pcm or/and modem i/o data.
454 32003e?avr32?05/06 at32ap7000 25.7.3 ac97 controller channel organization the ac97 controller features a codec channel and 2 logical channels; channel a and channel b. the codec channel controls ac97 codec register s, it enables write and read configuration val- ues in order to bring the ac97 codec to an operating state. the codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. channel a and channel b transfer data to/from ac97 codec. all audio samples and modem data must transit by these two channels. each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by either channel a or channel b. the slot to cha nnel assignment is configured by two registers: ? ac97 controller input channel assignment register (ica) ? ac97 controller output channel assignment register (oca) the ac97 controller input channel assignment register (ica) configures the input slot to chan- nel assignment. the ac97 controller output channel assignment register (oca) configures the output slot to channel assignment. a slot can be left unassigned to a channel by the ac97 controller. slots 0, 1,and 2 cannot be assigned to channel a or to channel b through the oca and ica registers. the width of sample data, that transit via channel a and channel b varies and can take one of these values; 10, 16, 18 or 20 bits. figure 25-4. logical channel assignment slot # ac97fs tag cmd data 0 ac97tx (controller output) ac97rx (codec output) pcm l front pcm r front line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl tag status addr status data pcm left pcm right line 1 dac pcm mic rsved rsved rsved line 2 adc hset adc io status 12 3 4 56 7 8 91011 12 codec channel channel a codec channel channel a ac97c_oca = 0x0000_0209 ac97c_ica = 0x0000_0009 cmd addr
455 32003e?avr32?05/06 at32ap7000 25.7.3.1 ac97 controller setup the following operations must be performed in order to bring the ac97 controller into an operat- ing state: 1. enable the ac97 controller clock in the power manager. 2. turn on ac97 function by enabling the ena bit in ac97 controller mode register (mr). 3. configure the input channe l assignment by controlling the ac97 controller input assignment register (ica). 4. configure the output channel assignment by controlling the ac97 controller input assignment register (oca). 5. configure sample width for channel a and ch annel b by writing the size bit field in ac97c channel a mode register (camr) and ac97c channel b mode register (cbmr). the application can write 10, 16, 18,or 20-bit wide pcm samples through the ac97 interface and they will be trans ferred into 20-bit wide slots. 6. configure data endianness for channel a and channel b by writing cem bit field in camr and cbmr registers. data on the ac-link are shifted msb first. the application can write little- or big-endian data to the ac97 controller interface. 7. configure the pio controller to drive the reset signal of the external codec. the reset signal must fulfill external ac97 codec timing requirements. 8. enable channel a and/or channel b by writing cen bit field in camr and cbmr registers. 25.7.3.2 transmit operation the application must perform the following steps in order to send data via a channel to the ac97 codec: ? check if previous data has been sent by polling txrdy flag in the ac97c channel x status register (cxsr). x being one of the 2 channels. ? write data to the ac97 controller channel x transmit holdin g register (cxthr). once data has been transferred to the channel x shift register, the txrdy flag is automatically set by the ac97 controller which allows the application to start a new write action. the applica- tion can also wait for an interrupt notice associated with txrdy in order to send data. the interrupt remains active until txrdy flag is cleared..
456 32003e?avr32?05/06 at32ap7000 figure 25-5. audio transfer (pcm l front, pcm r front) on channel x the txempty flag in the ac97 controller channel x status register (cxsr) is set when all requested transmissions for a channel have been shifted on the ac-link. the application can either poll txempty flag in cxsr or wait for an interrupt notice associated with the same flag. in most cases, the ac97 controller is embedded in chips that target audio player devices. in such cases, the ac97 controller is exposed to heavy audio transfers. using the polling tech- nique increases processor overhead and may fail to keep the required pace under an operating system. in order to avoid these polling drawbacks, the app lication can perform audio streams by using a dma controller (dmac) connected to both ch annels, which reduces processor overhead and increases performance especially under an operating system. the dmac transmit counter values must be equal to the number of pcm samples to be trans- mitted, each sample goes in one slot. 25.7.3.3 ac97 output frame the ac97 controller outputs a thirteen-slot frame on the ac-link. the first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. slots 1 and 2 are used if the application performs control and status monitoring actions on ac97 codec control/status registers. slots [3:12] are used according to the content of the ac97 controller output channel assignment regi ster (oca). if the application performs many transmit requests on a channel, some of the slots associated to this channel or all of them will carry valid data. slot # ac97fs tag cmd addr cmd data 0 ac97tx (controller output) pcm l front pcm r front line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl 12 3 4 56 7 8 9 1011 12 txrdycx (ac97c_sr) write access to ac97c_thrx pcm l front transfered to the shift register pcm r front transfered to the shift register txempty (ac97c_sr)
457 32003e?avr32?05/06 at32ap7000 25.7.3.4 receive operation the ac97 controller can also receive data from ac97 codec. data is received in the channel?s shift register and then transferred to the ac97 controller channel x read holding register. to read the newly received data, the application must perform the following steps: ? poll rxrdy flag in ac97 controller channel x status register (cxsr). x being one of the 2 channels. ? read data from ac97 controller channel x read holding register. the application can also wait for an interrupt notice in order to read data from cxrhr. the inter- rupt remains active until rxrdy is cleared by reading cxsr. the rxrdy flag in cxsr is set automatically when data is received in the channel x shift regis- ter. data is then shifted to cxrhr. figure 25-6. audio transfer (pcm l front, pcm r front) on channel x if the previously received data has not been read by the application, the new data overwrites the data already waiting in cxrhr, therefore the ovrun flag in cx sr is raised. the application can either poll the ovrun flag in cxsr or wait for an interrupt notice. the interrupt remains active until the ovrun fl ag in cxsr is set. the ac97 controller can also be used in sound recording devices in association with an ac97 codec. the ac97 controller may also be exposed to heavy pcm transfers. the application can use the dmac connected to both channels in order to reduce processor overhead and increase performance especially under an operating system. the dmac receive counter values must be equal to the number of pcm samples to be received. when more than one timeslot is assigned to a channel using dma, the different timeslot sam- ples will be interleaved. 25.7.3.5 ac97 input frame the ac97 controller receives a thirteen slot frame on the ac-link sent by the ac97 codec. the first slot (tag slot or slot 0) fl ags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. slots 1 and 2 are used if the application requires status informations from ac97 codec. slots [3:12] are used according to ac97 controller output channel assignment register (ica) content. the ac97 controller will not receive any data from any slot if ica is not assigned to a channel in input. slot # ac97fs 0123 4 56 7 8 9 1011 12 rxrdycx (ac97c_sr) read access to ac97c_rhrx ac97rx (codec output) tag status addr status data pcm left pcm right line 1 dac pcm mic rsved rsved rsved line 2 adc hset adc io status
458 32003e?avr32?05/06 at32ap7000 25.7.3.6 configuring and using interrupts instead of polling flags in ac97 controller global status register (sr) and in ac97 controller channel x status register (cxsr), the applicatio n can wait for an interr upt notice. the following steps show how to configure and use interrupts correctly: ? set the interruptible flag in ac97 controller channel x mode register (cxmr). ? set the interruptible event and channel event in ac97 controller interrupt enable register (ier). the interrupt handler must read both ac97 controller global status register (sr) and ac97 controller interrupt mask register (imr) and and them to get the real interrupt source. further- more, to get which event was activated, the interrupt handler has to read ac97 controller channel x status register (cxsr), x being the channel whose event triggers the interrupt. the application can disable event interrupts by writing in ac97 controlle r interrupt disable reg- ister (idr). the ac97 controller interrupt mask register (imr) shows which event can trigger an interrupt and which one cannot. 25.7.3.7 endianness endianness can be managed automatically for each channel, except for the codec channel, by writing to channel endianness mode (cem) in cxmr. this enables transferring data on ac-link in little endian format without any additional operation. 25.7.3.8 to transmit a word stored in little endian format on ac-link word to be written in ac97 co ntroller channel x transmit hold ing register (cxthr) (as it is stored in memory or mi croprocessor register). word stored in channel x transmit holding register (ac97c_cxthr) (data to transmit) . data transmitted on appropriate slot: data[19:0] = {byte1[3:0], byte2[7:0], byte3[7:0]}. 25.7.3.9 to transmit a halfword stored in little endian format on ac-link halfword to be written in ac97 controller ch annel x transmit hold ing register (cxthr). halfword stored in ac97 cont roller channel x transmit hold ing register (cxthr) (data to transmit). data emitted on related slot: data[19:0] = {byte1[7:0], byte0[7:0], 0x0}. 31 24 23 16 15 8 7 0 byte3[7:0] byte2[7:0] byte1[7:0] byte0[7:0] 31 24 23 20 19 16 15 8 7 0 ? ? byte1[3:0] byt e2[7:0] byte3[7:0] 31 24 23 16 15 8 7 0 ? ? byte0[7:0] byte1[7:0] 31 24 23 16 15 8 7 0 ? ? byte1[7:0] byte0[7:0]
459 32003e?avr32?05/06 at32ap7000 25.7.3.10 to transmit a10-bit sample stored in little endian format on ac-link halfword to be written in ac97 controller ch annel x transmit hold ing register (cxthr). halfword stored in ac97 cont roller channel x transmit hold ing register (cxthr) (data to transmit). data emitted on related slot: data[19:0] = {byte1[1:0], byte0[7:0], 0x000}. 25.7.3.11 to receive word transfers data received on appropriate slot: data[19:0] = {byte2[3:0], byte1[7:0], byte0[7:0]}. word stored in ac97 co ntroller channel x receiv e holding register (cxrhr) (received data) . data is read from ac97 controller channel x receive holding register (cxrhr) when channel x data size is greater than 16 bits and when little endian mode is enabled (data written to memory). 25.7.3.12 to receive halfword transfers data received on appropriate slot: data[19:0] = {byte1[7:0], byte0[7:0], 0x0 }. halfword stored in ac97 controller channel x receive holding register (cxrhr) (received data). data is read from ac97 controller channel x receive holding register (cxrhr) when data size is equal to 16 bits and when little endian mode is enabled. 25.7.3.13 to receiv e 10-bit samples data received on appropriate slot: data[19:0] = {byte1[1:0], byte0[7:0], 0x000}. halfword stored in ac97 controller channel x receive hold ing register (cxrhr) (received data) 31 24 23 16 15 8 7 0 ? ? byte0[7:0] {0x00, byte1[1:0]} 31 24 23 16 15 10 9 8 7 0 ??? byte1 [1:0] byte0[7:0] 31 24 23 20 19 16 15 8 7 0 ? ? byte2[3:0] byt e1[7:0] byte0[7:0] 31 24 23 16 15 8 7 0 byte0[7:0] byte1[7:0] {0x0, byte2[3:0]} 0x00 31 24 23 16 15 8 7 0 ? ? byte1[7:0] byte0[7:0] 31 24 23 16 15 8 7 0 ? ? byte0[7:0] byte1[7:0] 31 24 23 16 15 10 9 8 7 0 ??? byte1 [1:0] byte0[7:0]
460 32003e?avr32?05/06 at32ap7000 data read from ac97 controller channel x receive holding regist er (cxrhr) when data size is equal to 10 bits and when little endian mode is enabled. 25.7.4 variable sample rate the problem of variable sample rate can be su mmarized by a simple example. when passing a 44.1 khz stream across the ac-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. the new ac97 standard approach calls for the addition of ?on-demand? slot request flags. the ac97 codec examines its sample rate control register, the state of its fifos, and the incoming sdata_out tag bits (slot 0) of each output frame and then determines which slotreq bits to set acti ve (low). these bits are passed from the ac97 codec to the ac97 controller in slot 1/slotreq in every audio input frame. each time the ac97 controller sees one or more of the newly defined slot request flags set active (low) in a given audio input frame, it must pass along the next pcm sample for the corresponding slot(s) in the ac-link output frame that immediately follows. the variable sample rate mode is enabled by performing the following steps: ? setting the vra bit in the ac97 controller mode register (mr). ? enable variable rate mode in the ac97 codec by performing a transfer on the codec channel. slot 1 of the input frame is automatically interpreted as slotreq signaling bits. the ac97 con- troller will automatically fill the ac tive slots according to both sl otreq and oca register in the next transmitted frame. 25.7.5 power management 25.7.5.1 powering down the ac-link the ac97 codecs can be placed in low power mo de. the application can bring ac97 codec to a power down state by performing sequential writes to ac97 codec powerdown register . both the bit clock (clock delivered by ac97 codec, sclk) and the input line (sdi) are held at a logic low voltage level. this puts ac 97 codec in power down state while all its registers are still hold- ing current values. without the bit clock, the ac-link is completely in a power down state. the ac97 controller should not attempt to pl ay or capture audio data until it has awakened ac97 codec. to set the ac97 codec in low power mode, the pr4 bit in the ac97 codec powerdown register (codec address 0x26) must be set to 1. then the primary codec drives both bitclk and sdi to a low logic voltage level. the following operations must be done to put ac97 codec in low power mode: ? disable channel a clearing cen in the camr register. ? disable channel b clearing cen field in the cbmr register. ? write 0x2680 value in the cothr register. ? poll the txempty flag in cxsr registers for the 2 channels. at this point ac97 code c is in low power mode. 31 24 23 16 15 8 7 3 1 0 ? ? byte0[7:0] 0x00 byte1 [1:0]
461 32003e?avr32?05/06 at32ap7000 25.7.5.2 waking up the ac-link there are two methods to bring the ac-link out of low power mode. regardless of the method, it is always the ac97 controller that performs the wake-up. 25.7.5.3 wake-up tiggered by the ac97 controller the ac97 controller can wake up the ac97 codec by issuing either a cold or a warm reset. the ac97 controller can also wake up the ac97 codec by asserting sync signal, however this action should not be performed for a minimum period of four audio frames following the frame in which the powerdown was issued. 25.7.5.4 wake-up triggered by the ac97 codec this feature is implemented in ac97 modem c odecs that need to report events such as caller- id and wake-up on ring. the ac97 codec can drive sdi signal from low to high level and holding it high until the control- ler issues either a cold or a warm reset. the sdi rising edge is asynchronously (regarding sync) detected by the ac97 controller. if wkup bit is enabled in imr register, an interrupt is triggered that wakes up the ac97 controller which should then immediately issue a cold or a warm reset. if the processor needs to be awakened by an exte rnal event, the sdi signal must be externally connected to the wakeup entry of the system controller. figure 25-7. ac97 power-down/up sequence ac97ck ac97fs tag write to 0x26 data pr4 power down frame sleep state tag write to 0x26 data pr4 wake event warm reset new audio frame tag slot1 slot2 ac97tx ac97rx tag slot1 slot2
462 32003e?avr32?05/06 at32ap7000 25.7.5.5 ac97 codec reset there are three ways to reset an ac97 codec. 25.7.5.6 cold ac97 reset a cold reset is generated by asserting the reset signal low for the minimum specified time (depending on the ac97 codec) and then by de-a sserting reset high. bitclk and sync is reactivated and all ac97 codec registers are set to their default power-on values. transfers on ac-link can resume. the reset signal will be controlled via a pio line. th is is how an applicat ion should perform a cold reset: ? clear and set ena flag in the mr register to reset the ac97 controller ? clear pio line output cont rolling the ac97 reset signal ? wait for the minimum specified time ? set pio line output contro lling the ac97 reset signal bitclk, the clock provided by ac97 codec, is detected by the controller. 25.7.5.7 warm ac97 reset a warm reset reactivates the ac-link without alteri ng ac97 codec registers. a warm reset is sig- naled by driving ac97fx signal high for a minimum of 1us in the absence of bitclk. in the absence of bitclk, ac97fx is treated as an a synchronous (regarding ac97fx) input used to signal a warm reset to ac97 codec. this is the right way to perform a warm reset: ? set wrst in the mr register. ? wait for at least 1us ? clear wrst in the mr register. the application can check that operations have resumed by checking sof flag in the sr regis- ter or wait for an interrupt notice if sof is enabled in imr.
463 32003e?avr32?05/06 at32ap7000 25.8 ac97 controller (a c97c) user interface table 25-4. register mapping offset register register name access reset 0x0-0x4 reserved ? ? ? 0x8 mode register mr read/write 0x0 0xc reserved ? ? ? 0x10 input channel assignment register ica read/write 0x0 0x14 output channel assignment register oca read/write 0x0 0x18-0x1c reserved ? ? ? 0x20 channel a receive holding register carhr read 0x0 0x24 channel a transmit holding register cathr write ? 0x28 channel a status register casr read 0x0 0x2c channel a mode register camr read/write 0x0 0x30 channel b receive holding register cbrhr read 0x0 0x34 channel b transmit holding register cbthr write ? 0x38 channel b status register cbsr read 0x0 0x3c channel b mode register cbmr read/write 0x0 0x40 codec receive holding register corhr read 0x0 0x44 codec transmit holding register cothr write ? 0x48 codec status register cosr read 0x0 0x4c codec mode register comr read/write 0x0 0x50 status register sr read 0x0 0x54 interrupt enable register ier write ? 0x58 interrupt disable register idr write ? 0x5c interrupt mask register imr read 0x0 0x60-0xfb reserved ? ? ?
464 32003e?avr32?05/06 at32ap7000 25.8.1 ac97 controller mode register name: mr access type: read-write ? vra: variable rate (for data slots 3-12) 0: variable rate is inactive. (48 khz only) 1: variable rate is active. ? wrst: warm reset 0: warm reset is inactive. 1: warm reset is active. ? ena: ac97 controller global enable 0: no effect. ac97 function as well as access to other ac97 controller registers are disabled. 1: activates the ac97 function. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????vrawrstena
465 32003e?avr32?05/06 at32ap7000 25.8.2 ac97 controller input channel assignment register register name :ica access type : read/write ? chidx: channel id for the input slot x 31 30 29 28 27 26 25 24 ? ? chid12 chid11 23 22 21 20 19 18 17 16 chid10 chid9 chid8 15 14 13 12 11 10 9 8 chid8 chid7 chid6 chid5 76543210 chid5 chid4 chid3 chidx selected receive channel 0x0 none. no data will be received during this slot x 0x1 channel a data will be received during this slot time. 0x2 channel b data will be received during this slot time
466 32003e?avr32?05/06 at32ap7000 25.8.3 ac97 controller output channel assignment register register name :oca access type : read/write ? chidx: channel id for the output slot x 31 30 29 28 27 26 25 24 ? ? chid12 chid11 23 22 21 20 19 18 17 16 chid10 chid9 chid8 15 14 13 12 11 10 9 8 chid8 chid7 chid6 chid5 76543210 chid5 chid4 chid3 chidx selected transmit channel 0x0 none. no data will be transmitted during this slot x 0x1 channel a data will be transferred during this slot time. 0x2 channel b data will be transferred during this slot time
467 32003e?avr32?05/06 at32ap7000 25.8.4 ac97 controller codec channel receive holding register register name : corhr access type : read-only ?sdata: status data data sent by the codec in the third ac97 input frame slot (slot 2). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 sdata 76543210 sdata
468 32003e?avr32?05/06 at32ap7000 25.8.5 ac97 controller codec channel transmit holding register register name :cothr access type : write-only ? read: read/write command 0: write operation to the codec r egister indexed by the caddr address. 1: read operation to the codec register indexed by the caddr address. this flag is sent during the second ac97 frame slot ? caddr: codec control register index data sent to the codec in the second ac97 frame slot. ? cdata: command data data sent to the codec in the third ac97 frame slot (slot 2). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 read caddr 15 14 13 12 11 10 9 8 cdata 76543210 cdata
469 32003e?avr32?05/06 at32ap7000 25.8.6 ac97 controller channel a, channel b receive holding register register name : carhr, cbrhr access type : read-only ? rdata: receive data received data on channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? rdata 15 14 13 12 11 10 9 8 rdata 76543210 rdata
470 32003e?avr32?05/06 at32ap7000 25.8.7 ac97 controller channel a, channel b transmit holding register register name : cathr, cbthr access type : write-only ? tdata: transmit data data to be sent on channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? tdata 15 14 13 12 11 10 9 8 tdata 76543210 tdata
471 32003e?avr32?05/06 at32ap7000 25.8.8 ac97 controller channel a status register register name : casr access type : read-only 25.8.9 ac97 controller channel b status register register name : cbsr access type : read-only 25.8.10 ac97 controller codec channel status register register name : cosr access type : read-only flags in cxsr registers are automatically cleared by a processor read operation. ? txrdy: channel transmit ready 0: data has been loaded in channel transmit register and is waiting to be loaded in the channel transmit shift register. 1: channel transmit register is empty. ? txempty: channel transmit empty 0: data remains in the channel transmit register or is currently transmitted from the channel transmit shift register. 1: data in the channel transmit register have been loaded in the channel transmit shift register and sent to the codec. ? rxrdy: channel receive ready 0: channel receive holding register is empty. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? - txempty txrdy
472 32003e?avr32?05/06 at32ap7000 1: data has been received and loaded in channel receive holding register. ? ovrun: receive overrun 0: no data has been loaded in the channel receive holding re gister while previous data has not been read since the last read of the status register. 1: data has been loaded in the channel receive holding register while previous data has not yet been read since the last read of the status register.
473 32003e?avr32?05/06 at32ap7000 25.8.11 ac97 controller channel a mode register register name :camr access type : read/write ? dmaen: dma enable 0: disable dma transfers for this channel. 1: enable dma transfers for this channel using dmac. ? cem: channel a endian mode 0: transferring data through channel a is straight forward (big endian). 1: transferring data through channel a from/to a memory is performed with from/to little endian format translation. ? size: channel a data size size encoding note: each time slot in the data phase is 20 bit long. for example, if a 16-bit sample stream is being played to an ac 97 dac, t he first 16 bit positions are presented to the dac msb-justified. they ar e followed by the next four bit positions that the ac97 control ler fills with zeroes. this process ensures that the least significant bits do not introduce any dc biasing, regardless of the impl e- mented dac?s resolution (16-, 18-, or 20-bit). ? cen: channel a enable 0: data transfer is disabled on channel a. 1: data transfer is enabled on channel a. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? dmaen cen ? ? cem size 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy size selected channel 0x0 20 bits 0x1 18bits 0x2 16 bits 0x3 10 bits
474 32003e?avr32?05/06 at32ap7000 25.8.12 ac97 controller channel b mode register register name :cbmr access type : read/write ? dmaen: dma enable 0: disable dma transfers for this channel. 1: enable dma transfers for this channel using dmac. ? cem: channel b endian mode 0: transferring data through channel b is straight forward (big endian). 1: transferring data through channel b from/to a memory is performed with from/to little endian format translation. ? size: channel b data size size encoding note: each time slot in the data phase is 20 bit long. for example, if a 16-bit sample stream is being played to an ac 97 dac, t he first 16 bit positions are presented to the dac msb-justified. they ar e followed by the next four bit positions that the ac97 control ler fills with zeroes. this process ensures that the least significant bits do not introduce any dc biasing, regardless of the impl e- mented dac?s resolution (16-, 18-, or 20-bit). ? cen: channel b enable 0: data transfer is disabled on channel b. 1: data transfer is enabled on channel b. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? dmaen cen ? ? cem size 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? unrun txempty txrdy size selected channel 0x0 20 bits 0x1 18bits 0x2 16 bits 0x3 10 bits
475 32003e?avr32?05/06 at32ap7000 25.8.13 ac97 controller codec channel mode register register name : comr access type : read/write ? txrdy: channel transmit ready interrupt enable ? txempty: channel transmit empty interrupt enable ? rxrdy: channel receive ready interrupt enable ? ovrun: receive overrun interrupt enable 0: read: the corresponding interrupt is disabled. write: disables the corresponding interrupt. 1: read: the corresponding interrupt is enabled. write: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ovrun rxrdy ? - txempty txrdy
476 32003e?avr32?05/06 at32ap7000 25.8.14 ac97 controller status register register name :sr access type : read-only wkup and sof flags in sr register are automat ically cleared by a processor read operation. ? sof: start of frame 0: no start of frame has been detected since the last read of the status register. 1: at least one start of frame has been detected since the last read of the status register. ? wkup: wake up detection 0: no wake-up has been detected. 1: at least one rising edge on sdata_in has been asynchr onously detected. that means ac97 codec has notified a wake-up. ? coevt: codec channel event a codec channel event occurs when cosr and comr is not 0. coevt flag is automatically cleared when the channel event condition is cleared. 0: no event on the codec channel has been detected since the last read of the status register. 1: at least one event on th e codec channel is active. ? caevt: channel a event a channel a event occurs when casr and camr is not 0. ca evt flag is automatically cleared when the channel event condition is cleared. 0: no event on the channel a has been detected since the last read of the status register. 1: at least one event on the channel a is active. ? cbevt: channel b event a channel b event occurs when cbsr and cbmr is not 0. cb evt flag is automatically cleared when the channel event condition is cleared. 0: no event on the channel b has been detected since the last read of the status register. 1: at least one event on the channel b is active. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cbevt caevt coevt wkup sof
477 32003e?avr32?05/06 at32ap7000 25.8.15 ac97 controller interrupt enable register register name :ier access type : write-only ? sof: start of frame ?wkup: wake up ? coevt: codec event ? caevt: channel a event ? cbevt: channel b event 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cbevt caevt coevt wkup sof
478 32003e?avr32?05/06 at32ap7000 25.8.16 ac97 controller interrupt disable register register name :idr access type : write-only ? sof: start of frame ?wkup: wake up ? coevt: codec event ? caevt: channel a event ? cbevt: channel b event 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cbevt caevt coevt wkup sof
479 32003e?avr32?05/06 at32ap7000 25.8.17 ac97 controller interrupt mask register register name :imr access type : read-only ? sof: start of frame ?wkup: wake up ? coevt: codec event ? caevt: channel a event ? cbevt: channel b event 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? cbevt caevt coevt wkup sof
480 32003e?avr32?05/06 at32ap7000 26. audio dac - (dac) rev: 1.1.0 26.1 features ? digital stereo dac ? oversampled d/a conversion architecture ? oversampling ratio fixed 128x ? digital interpolation filter: comb4 ? fir equalization filter ? 3rd order sigma-delta d/a converters ? digital bitstream outputs ? parallel interface ? connected to dma controller for backgrou nd transfer without cpu intervention 26.2 description the audio dac converts a 16-bit sample value to a digital bitstream with an average value pro- portional to the sample value. two channels are supported, making the audio dac particularly suitable for stereo audio. each channel has a pair of complementary digital outputs, dacn and dacn_n, which can be directly connected to an external amplifier. the audio dac is compromised of two 3rd order sigma delta d/a converter with an oversam- pling ratio of 128. the samples are upsampled with a 4th order sinc interpolation filter (comb4) before being input to the sigmal delta modulator. in order to compensate for the pass band fre- quency response of the interpolation filter and flatten the overall frequency response, the input to the interpolation filter is first filtered with a simple 3-tap fir filter.the total frequency response of the equalization fir filter and the interpolation filter is given in figure 26-2 on page 491 . the digital output bitstreams from the sigma delta modulators should be low-pass filtered to remove high frequency noise inserted by the modulation process.
481 32003e?avr32?05/06 at32ap7000 26.3 block diagram figure 26-1. functional block diagram 26.4 pin name list 26.5 product dependencies 26.5.1 i/o lines the output pins used for the output bitstream from the audio dac may be multiplexed with pio lines. before using the audio dac, the pio controller must be configured in order for the audio dac i/o lines to be in audio dac peripheral mode. 26.5.2 power management the apb-bus clock to the audio dac is generated by the power manager. before using the audio dac, the programmer must ensure that the audio dac clock is enabled in the power manager. table 26-1. i/o lines description pin name pin description type data0 output from audio dac channel 0 output data1 output from audio dac channel 1 output datan0 inverted output from audio dac channel 0 output datan1 inverted output from audio dac channel 1 output clock generator equalization fir sigma-delta da-mod equalization fir sigma-delta da-mod data0 sample_clk audiodac channel0 channel1 apb interface user interface datan1 power manager clk audio dac data data1 datan0 comb (int=128) comb (int=128)
482 32003e?avr32?05/06 at32ap7000 26.5.3 clock management the audio dac needs a separate clock for the d/a conversion operation. this clock should be set up in the power manager. the frequency of this clock must be 256 times the frequency of the desired samplerate (f s ). for f s =48khz this means that the clock must have a frequency of 12.288mhz. 26.5.4 interrupts the audio dac interface has an interrupt line connected to the interrupt controller. in order to handle interrupts, the interrupt controller must be programmed before configuring the audio dac. all audio dac interrupts can be enabled/disab led by writing to th e audio dac interrupt enable/disable registers. each pending and unm asked audio dac interrupt will assert the interrupt line. the audio dac interrupt service routine can get the interrupt source by reading the interrupt status register. 26.5.5 dma the audio dac is connected to the dma controller. the dma controller can be programmed to automatically transfer samples to the audio da c sample data register (sdr) when the audio dac is ready for new samples. this enables t he audio dac to operate without any cpu inter- vention such as polling the inte rrupt status register (isr) or using inte rrupts. see the dma controller documentation for details on how to setup dma transfers. 26.6 functional description in order to use the audio dac the product dependencies given in section 26.5 on page 481 must be resolved. particular attention should be given to the configuration of clocks and i/o lines in order to ensure correct operation of the audio dac. the audio dac is enabled by writing the en able bit in the audio dac control register (cr).the two 16-bit sample values for channel 0 and 1 can then be written to the least and most significant halfword of the sample data regist er (sdr), respectively. the tx_ready bit in the interrupt status register (isr) will be set whenever the dac is ready to receive a new sample. a new sample value should be written to sdr be fore 256 dac clock cycles, or an underrun will occur, as indicated by the underrun status flags in isr. isr is clear ed when read, or when writing one to the corresponding bits in the interrupt clear register (icr). for interrupt-based operation, the relevant interrupts must be enabled by writing one to the cor- responding bits in the interrupt enable register (ier). interrupts can be disabled by the interrupt disable register (idr), and active interrupts are indicated in the read-only interrupt mask regis- ter (imr). the audio dac can also be configured for peri pheral dma access, in which case only the enable bit in the control register needs to be set in the audio dac module.
483 32003e?avr32?05/06 at32ap7000 26.7 audio dac user interface table 26-2. register mapping offset register register name access reset 0x0 sample data register sdr read/write 0x0 0x4 reserved - - - 0x8 control register cr read/write 0x0 0xc interrupt mask register imr read 0x0 0x10 interrupt enable register ier write - 0x14 interrupt disable register idr write - 0x18 interrupt clear register icr write - 0x1c interrupt status register isr read 0x0
484 32003e?avr32?05/06 at32ap7000 26.7.1 audio dac sample data register name: sdr access type: read-write ? channel0: sample data for channel 0 signed 16-bit sample data for channel 0. when the swap bit in the dac control register (cr) is set writing to the sample data register (sdr) will cause the values writ ten to channel0 and ch annel1 to be swapped. ? channel1: sample data for channel 1 signed 16-bit sample data for channel 1. when the swap bit in the dac control register (cr) is set writing to the sample data register (sdr) will cause the values writ ten to channel0 and ch annel1 to be swapped. 31 30 29 28 27 26 25 24 channel1 23 22 21 20 19 18 17 16 channel1 15 14 13 12 11 10 9 8 channel0 76543210 channel0
485 32003e?avr32?05/06 at32ap7000 26.7.2 audio dac control register name: cr access type: read-write ? swap: swap channels 0: the channel0 and channel1 samples will not be swapped when writing the audio dac sample data register (sdr). 1: the channel0 and channel1 samples will be swapped when writing the audio dac sample data register (sdr). ? en: enable audio dac 0: audio dac is disabled. 1: audio dac is enabled. 31 30 29 28 27 26 25 24 enswap------ 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
486 32003e?avr32?05/06 at32ap7000 26.7.3 audio dac interrupt mask register name: imr access type: read-only ? underrun: underrun interrupt mask 0: the audio dac underrun interrupt is disabled. 1: the audio dac underrun interrupt is enabled. ? tx_ready: tx ready interrupt mask 0: the audio dac tx ready interrupt is disabled. 1: the audio dac tx ready interrupt is enabled. 31 30 29 28 27 26 25 24 --tx_readyunderrun---- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
487 32003e?avr32?05/06 at32ap7000 26.7.4 audio dac interrupt enable register name: ier access type: write-only ? underrun: underrun interrupt enable 0: no effect. 1: enables the audio dac underrun interrupt. ? tx_ready: tx ready interrupt enable 0: no effect. 1: enables the audio dac tx ready interrupt. 31 30 29 28 27 26 25 24 --tx_readyunderrun---- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
488 32003e?avr32?05/06 at32ap7000 26.7.5 audio dac interrupt disable register name: idr access type: write-only ? underrun: underrun interrupt disable 0: no effect. 1: disable the audio da c underrun interrupt. ? tx_ready: tx ready interrupt disable 0: no effect. 1: disable the audio dac tx ready interrupt. 31 30 29 28 27 26 25 24 --tx_readyunderrun---- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
489 32003e?avr32?05/06 at32ap7000 26.7.6 audio dac interrupt clear register name: icr access type: write-only ? underrun: underrun interrupt clear 0: no effect. 1: clear the audio dac underrun interrupt. ? tx_ready: tx ready interrupt clear 0: no effect. 1: clear the audio dac tx ready interrupt. 31 30 29 28 27 26 25 24 --tx_readyunderrun---- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
490 32003e?avr32?05/06 at32ap7000 26.7.7 audio dac interrupt status register name: isr access type: read-only ? underrun: underrun interrupt status 0: no audio dac underrun has occured since t he last time isr was read or since reset. 1: at least one audio dac underrun has occured since the last time isr was read or since reset. ? tx_ready: tx ready interrupt status 0: no audio dac tx ready has occuredt since the last time isr was read. 1: at least one audio dac tx ready has occuredt since the last time isr was read. 31 30 29 28 27 26 25 24 --tx_readyunderrun---- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 --------
491 32003e?avr32?05/06 at32ap7000 26.8 frequency response figure 26-2. frequecy response, eq-fir+comb 4 0 1 2 3 4 5 6 7 8 9 10 x 10 4 -6 0 -5 0 -4 0 -3 0 -2 0 -1 0 0 10
492 32003e?avr32?05/06 at32ap7000 27. static memory controller (smc) rev: 6105a 27.1 features ? 6 chip selects available ? 64-mbyte address space per chip select ? 8-, 16- or 32-bit data bus ? word, halfword, byte transfers ? byte write or by te select lines ? programmable setup, pulse and hold ti me for read signals per chip select ? programmable setup, pulse and hold time for write signals per chip select ? programmable data float time per chip select ? compliant with lcd module ? external wait request ? automatic switch to slow clock mode ? asynchronous read in page mode supporte d: page size ranges from 4 to 32 bytes 27.2 description the static memory controller (smc) generates the signals that control the access to the exter- nal memory devices or peripheral devices. it has 6 chip selects and a 26-bit address bus. the 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. separate read and write control signals allow for direct memory and peripheral interfacing. read and write signal waveforms are fully parametrizable. the smc can manage wait requests from external devices to extend the current access. the smc is provided with an automatic slow clock mode. in slow clock mode, it switches from user- programmed waveforms to slow-rate specific waveforms on read and write signals. the smc supports asynchronous burst read in page mode access for page size up to 32 bytes.
493 32003e?avr32?05/06 at32ap7000 27.3 block diagram figure 27-1. smc block diagram bus matrix apb ncs[7:0] nwr0/nwe nwait smc pio controller a0/nbs0 nrd nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 a[25:2] user interface pmc mck d[31:0] smc chip select
494 32003e?avr32?05/06 at32ap7000 27.4 i/o lines description 27.5 multiplexed signals table 27-1. i/o line description name description type active level ncs[7:0] static memory controller chip select lines output low nrd read signal output low nwr0/nwe write 0/write enable signal output low a0/nbs0 address bit 0/byte 0 select signal output low nwr1/nbs1 write 1/byte 1 select signal output low a1/nwr2/nbs2 address bit 1/write 2/byte 2 select signal output low nwr3/nbs3 write 3/byte 3 select signal output low a[25:2] address bus output d[31:0] data bus i/o nwait external wait signal input low table 27-2. static memory controller (smc) multiplexed signals multiplexed signal s related function nwr0 nwe byte-write or byte-select access, see ?bat - byte write or byte select access? on page 496 a0 nbs0 8-bit or 16-/32-bit data bus, see ?data bus width? on page 496 nwr1 nbs1 byte-write or byte-select access see ?bat - byte write or byte select access? on page 496 a1 nwr2 nbs2 8-/16-bit or 32-bit data bus, see ?data bus width? on page 496 . byte-write or byte-select access, see ?bat - byte write or byte select access? on page 496 nwr3 nbs3 byte-write or byte-select access see ?bat - byte write or byte select access? on page 496
495 32003e?avr32?05/06 at32ap7000 27.6 application example 27.6.1 hardware interface figure 27-2. smc connections to st atic memory devices 27.7 product dependencies 27.7.1 i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory con- troller pins to their peripheral function. if i/o lines of the smc are not used by the application, they can be used for other purposes by the pio controller. static memory controller d0-d31 a2 - a25 a0/nbs0 nwr0/nwe nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 128k x 8 sram d0 - d7 a0 - a16 oe we cs d0 - d7 d8-d15 a2 - a18 128k x 8 sram d0-d7 cs d16 - d23 d24-d31 128k x 8 sram d0-d7 cs nwr1/nbs1 nwr3/nbs3 nrd nwr0/nwe 128k x 8 sram d0 - d7 oe we cs nrd a1/nwr2/nbs2 ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a2 - a18 a0 - a16 nrd oe we oe we nrd a2 - a18 a0 - a16 a2 - a18 a0 - a16
496 32003e?avr32?05/06 at32ap7000 27.8 external memory mapping the smc provides up to 26 address lines, a[25:0]. this allows each chip select line to address up to 64 mbytes of memory. if the physical memory device co nnected on one chip select is smaller than 64 mbytes, it wraps around and appears to be repeated within this space. the smc correctly handles any valid access to the memory devi ce within the page (see figure 27-1 ). a[25:0] is only significant for 8-bit memory, a[25:1 ] is used for 16-bit memory, a[25:2] is used for 32-bit memory. figure 27-3. memory connections for eight external devices 27.9 connection to external devices 27.9.1 data bus width a data bus width of 8, 16, or 32 bits can be selected for each chip select. this option is con- trolled by the field dbw in smc_mode (mode register) for the corresponding chip select. figure 27-4 shows how to connect a 512k x 8-bit memory on ncs2. figure 27-5 shows how to connect a 512k x 16-bit memory on ncs2. figure 27-6 shows two 16-bit memories connected as a single 32-bit memory 27.9.2 bat - byte write or byte select access each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. this is controll ed by the bat (bat = byte select access) field of the smc_mode register for the corresponding chip select. nrd nwe a[25:0] d[31:0] 8 or 16 or 32 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[0] - ncs[7] smc
497 32003e?avr32?05/06 at32ap7000 figure 27-4. memory connection for an 8-bit data bus figure 27-5. memory connection for a 16-bit data bus figure 27-6. memory connection for a 32-bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1 d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable
498 32003e?avr32?05/06 at32ap7000 27.9.2.1 byte write access byte write access supports one byte write signal per byte of the data bus and a single read signal. ? for 16-bit devices: the smc provides nwr0 and nwr1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. one single read signal (nrd) is provided. byte write access is used to connect 2 x 8-bit devices as a 16-bit memory. ? for 32-bit devices: nwr0, nwr1, nwr2 and nwr3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. one single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices as a 32-bit memory. byte write option is illustrated on figure 27-7 on page 498 . 27.9.2.2 byte select access in this mode, read/write operations can be enabled/disabled at a byte level. one byte-select line per byte of the data bus is provided. one nrd and one nwe signal control read and write. ? for 16-bit devices: the smc provides nbs0 and nbs1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. byte select access is used to connect one 16-bit device. ? for 32-bit devices: nbs0, nbs1, nbs2 and nbs3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. byte select access is used to connect two 16-bit devices. figure 27-8 on page 499 shows how to connect two 16-bit dev ices on a 32-bit data bus in byte select access mode, on ncs3. figure 27-7. connection of 2 x 8-bit devices on a 16-bit bus: byte write option smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0]
499 32003e?avr32?05/06 at32ap7000 27.9.2.3 signal multiplexing depending on the bat, only the write signals or the byte select signals are used. to save ios at the external bus interface, control signals at the smc interface are multiplexed. table 27-3 on page 499 shows signal multiplexing depending on the data bus width and the byte access type. for 32-bit devices, bits a0 and a1 are unused. for 16-bit devices, bit a0 of address is unused. when byte select option is selected, nwr1 to nwr3 are unused. when byte write option is selected, nbs0 to nbs3 are unused. figure 27-8. connection of 2x16-bit data bus on a 32-bit data bus (byte select option) smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 table 27-3. smc multiplexed signal translation signal name 32-bit bus 16-bit bus 8-bit bus device type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit byte access type (bat) byte select byte select byte write byte select byte write nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3
500 32003e?avr32?05/06 at32ap7000 27.10 standard read and write protocols in the following sections, the byte access type is not considered. byte select lines (nbs0 to nbs3) always have the same timing as the a ad dress bus. nwe represents either the nwe sig- nal in byte select access type or one of the byte write lines (nwr0 to nwr3) in byte write access type. nwr0 to nwr3 have the same ti mings and protocol as nwe. in the same way, ncs represents one of the ncs[0..6] chip select lines. 27.10.1 read waveforms the read cycle is shown on figure 27-9 on page 500 . the read cycle starts with the address setting on the memory address bus, i.e.: {a[25:2], a1, a0} for 8-bit devices {a[25:2], a1} for 16-bit devices a[25:2] for 32-bit devices. figure 27-9. standard read cycle 27.10.1.1 nrd waveform the nrd signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nrd_setup: the nrd setup time is defined as the setup of address before the nrd falling edge; 2. nrd_pulse: the nrd pulse length is the time between nrd falling edge and nrd rising edge; 3. nrd_hold: the nrd hold time is defined as the hold time of a ddress after the nrd rising edge. a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd_setup nrd_pulse nrd_hold mck nrd d[31:0] ncs_rd_setup ncs_rd_pulse ncs_rd_hold nrd_cycle
501 32003e?avr32?05/06 at32ap7000 27.10.1.2 ncs waveform similarly, the ncs signal can be divided into a setup time, pulse length and hold time: 1. ncs_rd_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_rd_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_rd_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. 27.10.1.3 read cycle the nrd_cycle time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. the total read cycle time is equal to: nrd_cycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timings are defined separately for each chip select as an integer number of master clock cycles. to ensure that the nrd and ncs timings are coherent, user must define the total read cycle instead of the hold timing. nrd_cycle implicitly defines the nrd hold time and ncs hold time as: nrd_hold = nrd_cycle - nrd setup - nrd pulse ncs_rd_hold = nrd_cycle - ncs_rd_setup - ncs_rd_pulse 27.10.1.4 null delay setup and hold if null setup and hold parame ters are programmed for nrd and/or ncs, nrd and ncs remain active continuously in case of consecutive read cycles in the same memory (see figure 27-10 ).
502 32003e?avr32?05/06 at32ap7000 figure 27-10. no setup, no hold on nrd and ncs read signals 27.10.1.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 27.10.2 read mode as ncs and nrd waveforms are defined independently of one other, the smc needs to know when the read data is available on the data bus. the smc does not compare ncs and nrd tim- ings to know which signal rises first. the read_mode parameter indicates which signal (ncs or nrd) controls the read operation. this parame ter resides in the smc_mode register of the corresponding chip select. 27.10.2.1 read is controlled by nrd (read_mode = 1): figure 27-11 on page 503 shows the waveforms of a read operation of a typical asynchronous ram. the read data is available t pacc after the falling edge of nrd, and turns to ?z? after the ris- ing edge of nrd. in this case, the read_mode mu st be set to 1 (read is controlled by nrd), to indicate that data is available with the rising edge of nrd. the smc samples the read data internally on the rising edge of master clock that generates the rising edge of nrd, whatever the programmed waveform of ncs may be. mck nrd_pulse ncs_rd_pulse nrd_cycle nrd_pulse nrd_pulse ncs_rd_pulse ncs_rd_pulse nrd_cycle nrd_cycle a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0]
503 32003e?avr32?05/06 at32ap7000 figure 27-11. read_mode = 1: data is sampled by smc before the rising edge of nrd 27.10.2.2 read is controlled by ncs (read_mode = 0) figure 27-12 on page 503 shows the typical read cycle of an lcd module. the read data is valid t pacc after the falling edge of the ncs signal and remains valid until the rising edge of ncs. data must be sampled when ncs is raised. in that case, the read_mode must be set to 0 (read is controlled by ncs): the smc internally samples the data on the rising edge of master clock that generates the rising edge of ncs, whatever the progra mmed waveform of nrd may be. figure 27-12. read_mode = 0: data is sampled by smc before the rising edge of ncs data sampling t pacc mck a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0] data sampling t pacc mck d[31:0] a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd
504 32003e?avr32?05/06 at32ap7000 27.10.3 write waveforms the write protocol is similar to the read protocol. it is depicted in figure 27-13 on page 504 . the write cycle starts with the address setting on the memory address bus. 27.10.3.1 nwe waveforms the nwe signal is characterized by a setu p timing, a pulse width and a hold timing. 1. nwe_setup: the nwe setup time is defined as the setup of address and data before the nwe falling edge; 2. nwe_pulse: the nwe pulse length is the time between nwe falling edge and nwe rising edge; 3. nwe_hold: the nwe hold time is defined as the hold time of address and data after the nwe rising edge. the nwe waveforms apply to all byte-write lines in byte write access mode: nwr0 to nwr3. 27.10.3.2 ncs waveforms the ncs signal waveforms in write operation are not the same that those applied in read opera- tions, but are separately defined: 1. ncs_wr_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_wr_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_wr_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. figure 27-13. write cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nwe_setup nwe_pulse nwe_hold mck nwe ncs_wr_setup ncs_wr_pulse ncs_wr_hold nwe_cycle
505 32003e?avr32?05/06 at32ap7000 27.10.3.3 write cycle the write_cycle time is defined as the total durat ion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. the total write cycle time is equal to: nwe_cycle = nwe_setup + nwe_pulse + nwe_hold = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe and ncs (write) timings are defined separately for each chip select as an integer num- ber of master clock cycles. to ensure that the nwe and ncs timings are coherent, the user must define the total wr ite cycle instead of the hold timing. this implicitly defines the nwe hold time and ncs (write) hold times as: nwe_hold = nwe_cycle - nwe_setup - nwe_pulse ncs_wr_hold = nwe_cycle - ncs_wr_setup - ncs_wr_pulse 27.10.3.4 null delay setup and hold if null setup parameters are programmed for nwe and/or ncs, nwe and/or ncs remain active continuously in case of consecutive wr ite cycles in the same memory (see figure 27-14 on page 505 ). however, for devices that perform write operations on the rising edge of nwe or ncs, such as sram, either a setup or a hold must be programmed. figure 27-14. null setup and hold values of ncs and nwe in write cycle 27.10.3.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. ncs mck nwe, nwr0, nwr1, nwr2, nwr3 d[31:0] nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1
506 32003e?avr32?05/06 at32ap7000 27.10.4 write mode the write_mode parameter in th e smc_mode register of the corresponding chip select indi- cates which signal controls the write operation. 27.10.4.1 write is controlled by nwe (write_mode = 1): figure 27-15 on page 506 shows the waveforms of a write operation with write_mode set to 1. the data is put on the bus during the pulse and hold steps of the nwe signal. the internal data buffers are turned out after the nwe_setup time, and until the end of the write cycle, regardless of the programmed waveform on ncs. figure 27-15. write_mode = 1. the write op eration is controlled by nwe 27.10.4.2 write is controlled by ncs (write_mode = 0) figure 27-16 on page 507 shows the waveforms of a write operation with write_mode set to 0. the data is put on the bus during the pulse and hold steps of the ncs signal. the internal data buffers are turned out after the ncs_wr_setup time, and until the end of the write cycle, regardless of the programmed waveform on nwe. mck d[31:0] ncs a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 nwe, nwr0, nwr1, nwr2, nwr3
507 32003e?avr32?05/06 at32ap7000 figure 27-16. write_mode = 0. the write op eration is controlled by ncs 27.10.5 coding timing parameters all timing parameters are defined for one chip select and are grouped together in one smc_register according to their type. the smc_setup register groups the definition of all setup parameters: ? nrd_setup, ncs_rd_setup, nwe_setup, ncs_wr_setup the smc_pulse register groups the definition of all pulse parameters: ? nrd_pulse, ncs_rd_pulse, nwe_pulse, ncs_wr_pulse the smc_cycle register groups the definition of all cycle parameters: ? nrd_cycle, nwe_cycle section 27-4 on page 507 shows how the timing parameters are coded and their permitted range. mck d[31:0] ncs nwe, nwr0, nwr1, nwr2, nwr3 a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 table 27-4. coding and range of timing parameters coded value number of bits effective value permitted range coded value effective value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 31 128 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 63 256 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 256 256+127 512 512+127 768 768+127
508 32003e?avr32?05/06 at32ap7000 27.10.6 reset values of timing parameters section 27-5 on page 508 gives the default value of timing parameters at reset. 27.10.7 usage restriction the smc does not check the validity of the user-programmed parameters. if the sum of setup and pulse parameters is larger than the corresponding cycle parameter, this leads to unpredictable behavior of the smc. for read operations: null but positive setup and hold of address and nrd and/or ncs can not be guaranteed at the memory interface because of the propagation dela y of theses signals through external logic and pads. if positive setup and hold values must be verified, then it is strictly recommended to pro- gram non-null values so as to cover possible skews between address, ncs and nrd signals. for write operations: if a null hold value is programmed on nwe, the smc can guarantee a positive hold of address, byte select lines, and ncs signal after the rising edge of nwe. this is true for write_mode = 1 only. see ?early read wait state? on page 509 . for read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. in read and write cycles, the setup and hold time parameters are defined in reference to the address bus. for external devices that require setup and hold time between ncs and nrd sig- nals (read), or between ncs and nwe signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 27.11 automatic wait states under certain circumstances, the smc automatica lly inserts idle cycles between accesses to avoid bus contention or operation conflict. 27.11.1 chip select wait states the smc always inserts an idle cycle between 2 transfers on separate chip selects. this idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. during chip select wait state, all control li nes are turned inactive: nbs0 to nbs3, nwr0 to nwr3, ncs[0..6], nrd lines are all set to 1. figure 27-17 on page 509 illustrates a chip select wait stat e between access on chip select 0 and chip select 2. table 27-5. reset values of timing parameters register reset value smc_setup 0x01010101 all setup timings are set to 1 smc_pulse 0x01010101 all pulse timings are set to 1 smc_cycle 0x00030003 the read and write operation last 3 master clock cycles and provide one hold cycle write_mode 1 write is controlled with nwe read_mode 1 read is controlled with nrd
509 32003e?avr32?05/06 at32ap7000 figure 27-17. chip select wait state between a read access on ncs0 and a write access on ncs2 27.11.2 early read wait state in some cases, the smc inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is not generated in addition to a chip select wait state. the early read cycle thus only occurs between a write and read access to the same memory device (same chip select). an early read wait state is automatically inserted if at least one of the following conditions is valid: ? if the write controlling signal has no hold time and the read controlling signal has no setup time ( figure 27-18 on page 510 ). ? in ncs write controlled mode (write_mode = 0), if there is no hold timing on the ncs signal and the ncs_rd_setup parameter is set to 0, regardless of the read mode ( figure 27-19 on page 510 ). the write operation must end with a ncs rising edge. without an early read wait state, the write operation could not complete properly. ? in nwe controlled mode (write_mode = 1) and if there is no hold timing (nwe_hold = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. if the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. see figure 27-20 on page 511 . a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 ncs0 nrd_cycle chip select wait state nwe_cycle mck ncs2 nrd nwe d[31:0] read to write wait state
510 32003e?avr32?05/06 at32ap7000 figure 27-18. early read wait state: write with no hold followed by read with no setup figure 27-19. early read wait state: ncs controlled write with no hold followed by a read with no ncs setup write cycle early read wait state mck nrd nwe read cycle no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0, a1 a[25:2] write cycle (write_mode = 0) early read wait state mck nrd ncs read cycle (read_mode = 0 or read_mode = 1) no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0,a1 a[25:2]
511 32003e?avr32?05/06 at32ap7000 figure 27-20. early read wait state: nwe-controlled write with no hold followed by a read with one set-up cycle 27.11.3 reload user configuration wait state the user may change any of the configuration parameters by writing the smc user interface. when detecting that a new user configuration has been written in the user interface, the smc inserts a wait state before starting the next access. the so called ?reload user configuration wait state? is used by the smc to load the new set of parameters to apply to next accesses. the reload configuration wait state is not applied in addition to the chip select wait state. if accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. on the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select. 27.11.3.1 user procedure to insert a reload configuration wait state, the smc detects a write access to any smc_mode register of the user interface. if the user only modifies timing registers (smc_setup, smc_pulse, smc_cycle registers) in the user interface, he must validate the modification by writing the smc_mode, even if no change was made on the mode parameters. a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 write cycle (write_mode = 1) early read wait state mck nrd internal write controlling signal external write controlling signal (nwe) d[31:0] read cycle (read_mode = 0 or read_mode = 1) no hold read setup = 1
512 32003e?avr32?05/06 at32ap7000 27.11.3.2 slow clock mode transition a reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see ?slow clock mode? on page 523 ). 27.11.4 read to write wait state due to an internal mechanism, a wait cycle is always inserted between consecutive read and write smc accesses. this wait cycle is referred to as a read to write wait stat e in this document. this wait cycle is applied in add ition to chip select and reload user configuration wait states when they are to be inserted. see figure 27-17 on page 509 .
513 32003e?avr32?05/06 at32ap7000 27.12 data float wait states some memory devices are slow to release the exte rnal bus. for such devices, it is necessary to add wait states (data float wait states) after a read access: ? before starting a read access to a different external memory ? before starting a write access to the same device or to a different external one. the data float output time (t df ) for each external memory device is programmed in the tdf_cycles field of the smc_mode register for the corresponding chip select. the value of tdf_cycles indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the executio n of a program from internal memory. the data float wait states management depends on the read_mode and the tdf_mode fields of the smc_mode register for the corresponding chip select. 27.12.1 read_mode setting the read_mode to 1 indicates to the smc that the nrd signal is responsible for turn- ing off the tri-state buffers of the external memory device. the data float period then begins after the rising edge of the nrd sign al and lasts tdf_cycles mck cycles. when the read operation is controlled by the ncs signal (read_mode = 0), the tdf field gives the number of mck cycles during which the data bus remains busy after the rising edge of ncs. figure 27-21 on page 514 illustrates the data float period in nrd-controlled mode (read_mode =1), assuming a data float period of 2 cycles (tdf_cycles = 2). figure 27-22 on page 514 shows the read operation when controlled by ncs (read_mode = 0) and the tdf_cycles parameter equals 3.
514 32003e?avr32?05/06 at32ap7000 figure 27-21. tdf period in nrd controlled read access (tdf = 2) figure 27-22. tdf period in ncs controlled read operation (tdf = 3) nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nrd controlled read operation tpacc mck nrd d[31:0] tdf = 2 clock cycles a[25:2] ncs tdf = 3 clock cycles tpacc mck d[31:0] ncs controlled read operation a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 nrd
515 32003e?avr32?05/06 at32ap7000 27.12.2 tdf optimization enabled (tdf_mode = 1) when the tdf_mode of the smc_mode register is set to 1 (tdf optimization is enabled), the smc takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. figure 27-23 on page 515 shows a read access controlled by nrd, followed by a write access controlled by nwe, on chip select 0. chip select 0 has been programmed with: nrd_hold = 4; read_mode = 1 (nrd controlled) nwe_setup = 3; write_mode = 1 (nwe controlled) tdf_cycles = 6; tdf_mode = 1 (optimization enabled). figure 27-23. tdf optimization: no tdf wait states are inserted if the tdf period is over when the next access begins 27.12.3 tdf optimization disabled (tdf_mode = 0) when optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. if the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait st ates will be inserted. figure 27-24 on page 516 , figure 27-25 on page 516 and figure 27-26 on page 517 illustrate the cases: ? read access followed by a read access on another chip select, ? read access followed by a write access on another chip select, ? read access followed by a write access on the same chip select, with no tdf optimization. a [25:2] ncs0 mck nrd nwe d[31:0] read to write wait state tdf_cycles = 6 read access on ncs0 (nrd controlled) nrd_hold= 4 nwe_setup= 3 write access on ncs0 (nwe controlled)
516 32003e?avr32?05/06 at32ap7000 figure 27-24. tdf optimization disabled (tdf mode = 0). tdf wait states between 2 read accesses on different chip selects figure 27-25. tdf mode = 0: tdf wait states between a read and a write access on different chip selects tdf_cycles = 6 tdf_cycles = 6 tdf_mode = 0 (optimization disabled) a[ 25:2] read1 cycle chip select wait state mck read1 controlling signal (nrd) read2 controlling signal (nrd) d[31:0] read1 hold = 1 read 2 cycle read2 setup = 1 5 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 tdf_cycles = 4 tdf_cycles = 4 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle chip select wait state read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 2 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
517 32003e?avr32?05/06 at32ap7000 figure 27-26. tdf mode = 0: tdf wait states between read and write accesses on the same chip select 27.13 external wait any access can be extended by an external device using the nw ait input signal of the smc. the exnw_mode field of the smc_mode register on the corresponding chip select must be set to either to ?10? (frozen mode) or ?11? (ready mode). when the exnw_mode is set to ?00? (disabled), the nwait signal is simply ignored on the correspo nding chip select. the nwait signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 27.13.1 restriction when one of the exnw_mode is enabled, i t is mandatory to program at least one hold cycle for the read/write controlling signal. for that reason, the nwait signal cannot be used in page mode ( ?asynchronous page mode? on page 526 ), or in slow clock mode ( ?slow clock mode? on page 523 ). the nwait signal is assumed to be a response of the external device to the read/write request of the smc. then nwait is examined by the smc only in the pulse state of the read or write controlling signal. the assertion of the nwait signal outside th e expected period has no impact on smc behavior. tdf_cycles = 5 tdf_cycles = 5 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 4 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
518 32003e?avr32?05/06 at32ap7000 27.13.2 frozen mode when the external device asserts the nwait signal (active low), and after internal synchroniza- tion of this signal, the smc state is frozen, i.e., smc internal counters are frozen, and all control signals remain unchanged. when the resynchronized nwait signal is deasserted, the smc completes the access, resuming the access from the point where it was stopped. see figure 27- 27 on page 518 . this mode must be selected when the ex ternal device uses the nwait signal to delay the access and to freeze the smc. the assertion of the nwait sign al outside the expected period is ignored as illustrated in figure 27-28 on page 519 . figure 27-27. write access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 110 1 4 5 63222210 write cycle d[31:0] nwait frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 internally synchronized nwait signal
519 32003e?avr32?05/06 at32ap7000 figure 27-28. read access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) read_mode = 0 (ncs_controlled) nrd_pulse = 2, nrd_hold = 6 ncs_rd_pulse =5, ncs_rd_hold =3 a [25:2] mck ncs nrd 10 43 43 2 555 22 0 210 210 1 read cycle assertion is ignored nwait internally synchronized nwait signal frozen state nbs0, nbs1, nbs2, nbs3, a0,a1
520 32003e?avr32?05/06 at32ap7000 27.13.3 ready mode in ready mode (exnw_mode = 11), the smc behaves differently. normally, the smc begins the access by down counting the setup and pulse counters of the read/write controlling signal. in the last cycle of the pulse phase, the resynchronized nwait signal is examined. if asserted, the smc suspends the access as shown in figure 27-29 on page 520 and figure 27-30 on page 521 . after deassertion, the access is completed: the hold step of the access is performed. this mode must be selected when the external de vice uses deassertion of the nwait signal to indicate its ability to complete the read or write operation. if the nwait signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in fig- ure 27-30 on page 521 . figure 27-29. nwait assertion in write access: ready mode (exnw_mode = 11) exnw_mode = 11 (ready mode) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 00 0 4 5 6321110 write cycle d[31:0] nwait internally synchronized nwait signal wait state nbs0, nbs1, nbs2, nbs3, a0,a1
521 32003e?avr32?05/06 at32ap7000 figure 27-30. nwait assertion in read access: ready mode (exnw_mode = 11) exnw_mode = 11(ready mode) read_mode = 0 (ncs_controlled) nrd_pulse = 7 ncs_rd_pulse =7 a[25:2] mck ncs nrd 4 5 63200 0 1 4 5 6321 1 read cycle assertion is ignored nwait internally synchronized nwait signal wait state assertion is ignored nbs0, nbs1, nbs2, nbs3, a0,a1
522 32003e?avr32?05/06 at32ap7000 27.13.4 nwait latency and read/write timings there may be a latency between the assertion of the read/w rite controlling signal and the asser- tion of the nwait signal by the device. t he programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. otherwise, the smc may enter the hold state of the access without detecting the nwait signal assertion. this is true in frozen mode as well as in ready mode. this is illustrated on fig- ure 27-31 on page 522 . when exnw_mode is enabled (ready or frozen), th e user must program a pulse length of the read and write controllin g signal of at least: minimal pulse length = nwait latency + 2 resynchronization cycles + 1 cycle figure 27-31. nwait latency exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 a [25:2] mck nrd 43 210 0 0 read cycle minimal pulse length nwait latency nwait intenally synchronized nwait signal wait state 2 cycle resynchronization nbs0, nbs1, nbs2, nbs3, a0,a1
523 32003e?avr32?05/06 at32ap7000 27.14 slow clock mode the smc is able to automatically apply a set of ?slow clock mode? read/write waveforms when an internal signal driven by the power management controller is asserted because mck has been turned to a slow clock rate (typically 32 khz clock rate). in this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. this mode is provided so as to avoid reprogramming the user interfac e with appropriate waveforms at very slow clock rate. when activated, the slow mode is active on all chip selects. 27.14.1 slow clock mode waveforms figure 27-32 on page 523 illustrates the read and write operations in slow clock mode. they are valid on all chip selects. section 27-6 on page 523 indicates the value of read and write parame- ters in slow clock mode. figure 27-32. read/write cycles in slow clock mode a[ 25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 a [25:2] mck nrd nrd_cycle = 2 1 1 ncs slow clock mode write slow clock mode read nbs0, nbs1, nbs2, nbs3, a0,a1 nbs0, nbs1, nbs2, nbs3, a0,a1 table 27-6. read and write timing parameters in slow clock mode read parameters duration (cycles) write parameters duration (cycles) nrd_setup 1 nwe_setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nrd_cycle 2 nwe_cycle 3
524 32003e?avr32?05/06 at32ap7000 27.14.2 switching from (to) slow clock mode to (from) normal mode when switching from slow clock mode to the nor mal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.see figure 27-33 on page 524 . the external device may not be fast enough to support such timings. figure 27-34 on page 525 illustrates the recommended procedur e to properly switch from one mode to the other. figure 27-33. clock rate transition occurs while the smc is performing a write operation a [25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 slow clock mode write slow clock mode internal signal from pmc 11 1 2 3 2 nwe_cycle = 7 normal mode write slow clock mode transition is detected: reload configuration wait state this write cycle finishes with the slow clock mode set of parameters after the clock rate transition slow clock mode write nbs0, nbs1, nbs2, nbs3, a0,a1
525 32003e?avr32?05/06 at32ap7000 figure 27-34. recommended procedure to switch from slow clock mo de to normal mode or from normal mode to slow clock mode a [25:2] ncs 1 mck nwe 1 1 slow clock mode write slow clock mode internal signal from pmc 2 3 2 normal mode write idle state reload configuration wait state nbs0, nbs1, nbs2, nbs3, a0,a1
526 32003e?avr32?05/06 at32ap7000 27.15 asynchronous page mode the smc supports asynchronous burst reads in page mode, providing that the page mode is enabled in the smc_mode register (pmen fiel d). the page size must be configured in the smc_mode register (ps field) to 4, 8, 16 or 32 bytes. the page defines a set of consecutive bytes into memory. a 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. the msb of data address defines the address of the page in memory, the lsb of address define the address of the data in the page as detailed in table 27-7 on page 526 . with page mode memory devices, the first access to one page (t pa ) takes longer than the subse- quent accesses to the page (t sa ) as shown in figure 27-35 on page 526 . when in page mode, the smc enables the user to define different r ead timings for the first access within one page, and next accesses within the page. notes: 1. a denotes the address bus of the memory device 2. for 16-bit devices, the bit 0 of address is igno red. for 32-bit devices, bits [1:0] are ignored. 27.15.1 protocol and timings in page mode figure 27-35 on page 526 shows the nrd and ncs timings in page mode access. figure 27-35. page mode read protocol (address msb and lsb are defined in table 27-7 on page 526 ) the nrd and ncs signals are held low during all read transfers, whatever the programmed val- ues of the setup and hold timings in the us er interface may be. moreover, the nrd and ncs timings are identical. the pulse length of the first access to the page is defined with the table 27-7. page address and data address within a page page size page address (1) data address in the page (2) 4 bytes a[25:2] a[1:0] 8 bytes a[25:3] a[2:0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] a[msb] ncs mck nrd d[31:0] ncs_rd_pulse nrd_pulse nrd_pulse tsa tpa tsa a[lsb]
527 32003e?avr32?05/06 at32ap7000 ncs_rd_pulse field of the smc_pulse register. the pulse length of subsequent accesses within the page are defined using the nrd_pulse parameter. in page mode, the programming of the read timings is described in table 27-8 on page 527 : the smc does not check the coherency of timings. it will always apply the ncs_rd_pulse timings as page access timing (t pa ) and the nrd_pulse for accesses to the page (t sa ), even if the programmed value for t pa is shorter than the programmed value for t sa . 27.15.2 byte access type in page mode the byte access type configuration remains active in page mode. for 16-bit or 32-bit page mode devices that require byte selection signals, configure the bat field of the smc_register to 0 (byt e select access type). 27.15.3 page mode restriction the page mode is not compatible with the use of the nwait signal. using the page mode and the nwait signal may lead to unpredictable behavior. 27.15.4 sequential and non-sequential accesses if the chip select and the msb of addresses as defined in table 27-7 on page 526 are identical, then the current access lies in the same page as the previous one, and no page break occurs. using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa ). figure 27-36 on page 528 illustrates access to an 8-bit mem- ory device in page mode, with 8-byte pages. access to d1 causes a page access with a long access time (t pa ). accesses to d3 and d7, though they are not sequential accesses, only require a short access time (t sa ). if the msb of addresses are different, the smc performs the access of a new page. in the same way, if the chip select is diffe rent from the previous access, a page break occurs. if two sequen- tial accesses are made to the page mode memory , but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. table 27-8. programming of read timings in page mode parameter value definition read_mode ?x? no impact ncs_rd_setup ?x? no impact ncs_rd_pulse t pa access time of first access to the page nrd_setup ?x? no impact nrd_pulse t sa access time of subsequent accesses in the page nrd_cycle ?x? no impact
528 32003e?avr32?05/06 at32ap7000 figure 27-36. access to non-sequential data within the same page a [25:3] 2 ], a1, a0 ncs mck nrd page address a1 a3 a7 d[7:0] ncs_rd_pulse nrd_pulse nrd_pulse d1 d3 d7
529 32003e?avr32?05/06 at32ap7000 27.16 static memory contro ller (smc) user interface the smc is programmed using the registers listed in table 27-9 on page 529 . for each chip select, a set of 4 registers is used to program the parameters of th e external device connected on it. in table 27-9 on page 529 , ?cs_number? denotes the chip select number. 16 bytes (0x1 0) are required per chip select. the user must complete writing the configuration by writing any one of the smc_mode registers. table 27-9. smc register mapping offset register name access reset state 0x10 x cs_number + 0x00 smc setup r egister smc_setup read/write 0x01010101 0x10 x cs_number + 0x04 smc pulse register smc_pulse read/write 0x01010101 0x10 x cs_number + 0x08 smc cycle register smc_cycle read/write 0x00030003 0x10 x cs_number + 0x0c smc mode register smc_mode read/write 0x10002103
530 32003e?avr32?05/06 at32ap7000 27.16.1 smc setup register register name: smc_setup[0 ..6] access type: read/write ? nwe_setup: nwe setup length the nwe signal setup length is defined as: nwe setup length = (128* nwe_setup [5] + nwe_setup[4:0]) clock cycles ? ncs_wr_setup: ncs setup length in write access in write access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_wr_setup [5] + ncs_wr_setup[4:0]) clock cycles ? nrd_setup: nrd setup length the nrd signal setup length is defined in clock cycles as: nrd setup length = (128* nrd_setup[5] + nrd_setup[4:0]) clock cycles ? ncs_rd_setup: ncs setup length in read access in read access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_rd_setup [5] + ncs_rd_setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ncs_rd_setup 23 22 21 20 19 18 17 16 ? ? nrd_setup 15 14 13 12 11 10 9 8 ? ? ncs_wr_setup 76543210 ? ? nwe_setup
531 32003e?avr32?05/06 at32ap7000 27.16.2 smc pulse register register name: smc_pulse[0..6] access type: read/write ? nwe_pulse: nwe pulse length the nwe signal pulse length is defined as: nwe pulse length = (256* nwe_pulse[6] + nwe_pulse[5:0]) clock cycles the nwe pulse length must be at least 1 clock cycle. ? ncs_wr_pulse: ncs pulse length in write access in write access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_wr_pul se[6] + ncs_wr_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. ? nrd_pulse: nrd pulse length in standard read access, the nrd signal pulse length is defined in clock cycles as: nrd pulse length = (256* nrd_pulse[ 6] + nrd_pulse[5:0]) clock cycles the nrd pulse length must be at least 1 clock cycle. in page mode read access, the nrd_pulse parameter defines the duration of the subsequent accesses in the page. ? ncs_rd_pulse: ncs pulse length in read access in standard read access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_rd_pul se[6] + ncs_rd_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. in page mode read access, the ncs_rd_pulse parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 ? ncs_rd_pulse 23 22 21 20 19 18 17 16 ? nrd_pulse 15 14 13 12 11 10 9 8 ? ncs_wr_pulse 76543210 ?nwe_pulse
532 32003e?avr32?05/06 at32ap7000 27.16.3 smc cycle register register name: smc_cycle[0..6] access type: read/write ? nwe_cycle: total write cycle length the total write cycle length is the total du ration in clock cycles of the write cycle. it is equal to the sum of the setup, pul se and hold steps of the nwe and ncs signals. it is defined as: write cycle length = (nwe_cycle[8:7 ]*256 + nwe_cycle[6:0]) clock cycles ? nrd_cycle: total read cycle length the total read cycle length is the total duration in clock cycles of the read cycle. it is equal to the sum of the setup, pulse and hold steps of the nrd and ncs signals. it is defined as: read cycle length = (nrd_cycle[8:7] *256 + nrd_cycle[6:0]) clock cycles 31 30 29 28 27 26 25 24 ???????nrd_cycle 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 ???????nwe_cycle 76543210 nwe_cycle
533 32003e?avr32?05/06 at32ap7000 27.16.4 smc mode register register name: smc_mode[0..6] access type: read/write ? read_mode: 1: the read operation is controlled by the nrd signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of nrd. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of nrd. 0: the read operation is controlled by the ncs signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of ncs. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of ncs. ?write_mode 1: the write operation is controlled by the nwe signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of nwe. 0: the write operation is controlled by the ncs signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of ncs. ? exnw_mode: nwait mode the nwait signal is used to extend the current read or writ e signal. it is only taken into account during the pulse phase of the read and writ e controlling signal. when the use of nwait is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal. ? disabled mode: the nwait input signal is ignored on the corresponding chip select. ? frozen mode: if asserted, the nwait signal freezes the current read or write cycle. after deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 ?? ps ???pmen 23 22 21 20 19 18 17 16 ? ? ? tdf_mode tdf_cycles 15 14 13 12 11 10 9 8 ?? dbw ???bat 76543210 ?? exnw_mode ?? write_mod e read_mode exnw_mode nwait mode 00disabled 01reserved 1 0 frozen mode 1 1 ready mode
534 32003e?avr32?05/06 at32ap7000 ? ready mode: the nwait si gnal indicates the availa bility of the external device at t he end of the pulse of the controlling read or write signal, to complete the access. if high, the access normally completes. if low, the access is extended until nwait returns high. ? bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. ? 1: byte write access type: ? write operation is controlled us ing ncs, nwr0, nwr1, nwr2, nwr3. ? read operation is controlled using ncs and nrd. ? 0: byte select access type: ? write operation is controlled using ncs, nwe, nbs0, nbs1, nbs2 and nbs3 ? read operation is controlled using ncs, nrd, nbs0, nbs1, nbs2 and nbs3 ? dbw: data bus width ? tdf_cycles: data float time this field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. the smc always provide one full cycle of bus turnaround after the tdf_cycles period. the external bus cannot be used by another chip select during tdf_cycles + 1 cycles. from 0 up to 15 tdf_cycles can be set. ? tdf_mode: tdf optimization 1: tdf optimization is enabled. ? the number of tdf wait states is optimized using the setup period of the next read/write access. 0: tdf optimization is disabled. ? the number of tdf wait states is inserted before the next access begins. ? pmen: page mode enabled 1: asynchronous burst read in page mode is applied on the corresponding chip select. 0: standard read is applied. ? ps: page size if page mode is enabled, this field indicates the size of the page in bytes. dbw data bus width 008-bit bus 0116-bit bus 1032-bit bus 11reserved ps page size 0 0 4-byte page 0 1 8-byte page 1 0 16-byte page 1 1 32-byte page
535 32003e?avr32?05/06 at32ap7000 28. sdram controller (sdramc) rev: 6100a 28.1 features ? numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path ? programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable ? energy-saving capabilities ? self-refresh, power-down and deep power modes supported ? supports mobile sdram devices ? error detection ? refresh error interrupt ? sdram power-up initialization by software ? cas latency of 1, 2, 3 supported ? auto precharge command not used 28.2 description the sdram controller (sdramc) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit sdram device. the page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the sdram controller supports a read or write burst length of one location. it keeps track of the active row in each bank, thus maximizing sd ram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. the sdram controller supports a cas latency of 1,2 or 3 and optimizes the read access depending on the frequency. the different modes available - self-refresh, power-down and deep power-down modes - mini- mize power consumption on the sdram device.
536 32003e?avr32?05/06 at32ap7000 28.3 block diagram figure 28-1. sdram controller block diagram 28.4 i/o lines description memory controller apb sdramc interrupt sdck sdcs sdramc_a[12:0] sdramc pio controller ba[1:0] sdcke ras cas sdwe nbs[3:0] user interface pmc mck d[31:0] sdramc chip select table 28-1. i/o line description name description type active level sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba[1:0] bank sele ct signals output ras row signal output low cas column signal output low sdwe sdram write enable output low nbs[3:0] data mask enable signals output low sdramc_a[12:0] address bus output d[31:0] data bus i/o
537 32003e?avr32?05/06 at32ap7000 28.5 application example 28.5.1 hardware interface figure 28-2 shows an example of sdram device connec tion to the sdram controller using a 32-bit data bus width. figure 28-3 shows an example of sdram device connection using a 16- bit data bus width. these examples are given for a direct connection of the devices to the sdram controller, without external bus in terface or pio cont roller multiplexing. figure 28-2. sdram controller connections to sdra m devices: 32-bit data bus width figure 28-3. sdram controller connections to sdra m devices: 16-bit data bus width sdram controller d0-d31 sdramc_a[0-12] ras cas sdck sdcke sdwe nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nbs1 nbs2 nbs3 sdcs d0-d7 d8-d15 ba0 ba1 a10 sdramc_a10 sdramc_a[0-9], sdramc_a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sdramc_a10 sdramc_a[0-9], sdramc_a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sdramc_a10 sdramc_a[0-9], sdramc_ a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sdramc_a10 sdramc_a[0-9], sdramc_a11 ba0 ba1 nbs0 nbs1 nbs3 nbs2 sdwe sdwe sdwe sdwe sdram controller d0-d31 sdramc_a[0-12] ras cas sdck sdcke sdwe nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nbs1 sdcs d0-d7 d8-d15 ba0 ba1 a10 sdramc_a10 sdramc_a[0-9], sdramc_a11 ba0 ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sdramc_a10 sdramc_a[0-9], sdramc_a11 ba0 ba1 nbs0 nbs1 sdwe sdwe
538 32003e?avr32?05/06 at32ap7000 28.5.2 software interface the sdram address space is organized into banks, rows, and columns. the sdram controller allows mapping different memory types according to the values set in the sdramc configura- tion register. the sdram controller?s function is to make the sdram device access protocol transparent to the user. table 28-2 to table 28-7 illustrate the sdram device memory mapping seen by the user in correlation with the device structure. various co nfigurations are illustrated. 28.5.2.1 32-bit memory data bus width notes: 1. m[1:0] is the byte address inside a 32-bit word. 2. bk[1] = ba1, bk[0] = ba0. table 28-2. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 09876543210 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 28-3. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 09876543210 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] table 28-4. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 09876543210 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0]
539 32003e?avr32?05/06 at32ap7000 28.5.2.2 16-bit memory data bus width notes: 1. m0 is the byte address inside a 16-bit half-word. 2. bk[1] = ba1, bk[0] = ba0. table 28-5. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 09876543210 bk[1:0] row[10:0] column[7:0] m 0 bk[1:0] row[10:0] column[8:0] m 0 bk[1:0] row[10:0] column[9:0] m 0 bk[1:0] row[10:0] column[10:0] m 0 table 28-6. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 09876543210 bk[1:0] row[11:0] column[7:0] m 0 bk[1:0] row[11:0] column[8:0] m 0 bk[1:0] row[11:0] column[9:0] m 0 bk[1:0] row[11:0] column[10:0] m 0 table 28-7. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 09876543210 bk[1:0] row[12:0] column[7:0] m 0 bk[1:0] row[12:0] column[8:0] m 0 bk[1:0] row[12:0] column[9:0] m 0 bk[1:0] row[12:0] column[10:0] m 0
540 32003e?avr32?05/06 at32ap7000 28.6 product dependencies 28.6.1 sdram device initialization the initialization sequence is generated by softw are. the sdram devices are initialized by the following sequence: 1. sdram features must be set in the configuration register: asynchronous timings (trc, tras, ...), number of column, rows, cas latency, and the data bus width. 2. for mobile sdram, temperature-compensated self refresh (tcsr), drive strength (ds) and partial array self refresh (pasr) must be set in the low power register. 3. the sdram memory type must be set in the memory device register. 4. a minimum pause of 200 s is provided to precede any signal toggle. 5. an all banks precharge command must be issued to the sdram devices. the applica- tion must set mode to 2 in the mode register and perform a write access to any sdram address. 6. eight auto-refresh (cbr) cycles are provided. the application must set the mode to 4 in the mode register and performs a write access to any sdram location eight times. 7. a mode register set (mrs) cycle must be issued to program the parameters of the sdram devices, in particular cas latency and burst length. the application must set mode to 3 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. 8. for mobile sdram initialization, an extended mode register set (emrs) cycle must be issued to program the sdram parameters (t csr, pasr, ds). the application must set mode to 5 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1] or ba[0] are set to 1. for example, with a 16-bit 128 mb sdram, (12 rows, 9 columns, 4 banks) bank address the sdram write access should be done at the address 0x20800000 or 0x20400000. 9. the application must go into normal mode, setting mode to 0 in the mode register and performing a write access at any location in the sdram. 10. write the refresh rate into the count field in the sdramc refresh timer register. (refresh rate = delay between refresh cycles). the sdram device requires a refresh every 15.625 us or 7.81us. with a 100 mhz frequency, the refresh timer count register must be set with (15.625/100 mhz) = 1562 or (7.81/100 mhz) = 781. after initialization, the sdram devices are fully functional.
541 32003e?avr32?05/06 at32ap7000 figure 28-4. sdram device initialization sequence 28.6.2 i/o lines the pins used for interfacing the sdram contro ller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the sdram controller pins to their peripheral function. if i/o lines of the sdram controller are not used by the application, they can be used for other purposes by the pio controller. 28.6.3 interrupt the sdram controller has an interrupt line connected to the interrupt controller. in order to han- dle interrupts, the interrupt controller must be programmed before configuring the sdram controller. using the sdram controller interrupt requires the ic to be programmed first.) sdck sdramc_a[9:0] a10 sdramc_a[12:11] sdcs ras cas sdwe nbs inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command sdcke t rp t rc t mrd
542 32003e?avr32?05/06 at32ap7000 28.7 functional description 28.7.1 sdram controller write cycle the sdram controller allows burst access or single access. in both cases, the sdram control- ler keeps track of the active row in each bank, th us maximizing performance. to initiate a burst access, the sdram controller uses the transfe r type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is car- ried out. if the next access is a write-sequential access, but the current a ccess is to a boundary page, or if the next access is in another ro w, then the sdram controller generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles ar e inserted between precharge/active (t rp ) commands and active/write (t rcd ) commands. for definition of these timing parameters, refer to the ?sdramc configuration register? on page 552 . this is described in figure 28-5 below. figure 28-5. write burst, 32-bit sdram access 28.7.2 sdram controller read cycle the sdram controller allows burst access, incremental burst of unspecified length or single access. in all cases, the sdram controller keeps track of the active row in each bank, thus maximizing performance of the sdram. if row and bank addresses do not match the previous row/bank address, then the sdram controller automatically generates a precharge command, activates the new row and starts the read command. to comply with the sdram timing param- eters, additional clock cycles on sdck are inserted between precharge and active commands (t rp ) and between active and read command (t rcd ). these two parameters are set in the config- uration register of the sdram controller. after a read command, additional wait states are generated to comply with the cas latency (1, 2 or 3 clock delays specified in the configuration register). sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rcd = 3 dna sdwe dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l
543 32003e?avr32?05/06 at32ap7000 for a single access or an incremented burst of unspecified length, the sdram controller antici- pates the next access. while the last value of t he column is returned by the sdram controller on the bus, the sdram controller anticipates the read to the next column and thus anticipates the cas latency. this reduces the effect of the cas latency on the internal bus. for burst access of specified length (4, 8, 16 words), access is not anticipated. this case leads to the best performance. if the burst is broken (border, busy mode, etc.), the next access is han- dled as an incrementing burst of unspecified length. figure 28-6. read burst, 32-bit sdram access 28.7.3 border management when the memory row boundary has been reached, an automatic page break is inserted. in this case, the sdram controller generates a precharge command, activates the new row and ini- tiates a read or write command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) com- mand. this is described in figure 28-7 below. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna sdwe dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2
544 32003e?avr32?05/06 at32ap7000 figure 28-7. read burst with boundary row access 28.7.4 sdram controller refresh cycles an auto-refresh command is used to refresh the sdram device. refresh addresses are gener- ated internally by the sdram device and incremented after each auto-refresh automatically. the sdram controller generates these auto-refresh commands periodically. an internal timer is loaded with the value in the register sdramc _tr that indicates the number of clock cycles between refresh cycles. a refresh error interrupt is generated when the previous auto-refresh command did not perform. it is acknowledged by reading the interrupt status register (sdramc_isr). when the sdram controller initia tes a refresh of the sdram devi ce, internal memory accesses are not delayed. however, if the cpu tries to ac cess the sdram, the slave indicates that the device is busy and the master is held by a wait signal. see figure 28-8 . sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rp = 3 sdwe row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 2 col b col c col d dma dmb dmc dmd row n dme
545 32003e?avr32?05/06 at32ap7000 figure 28-8. refresh cycle followed by a read access 28.7.5 power management three low-power modes are available: ? self-refresh mode: the sdram executes its own auto-refresh cycle without control of the sdram controller. current drained by the sdram is very low. ? power-down mode: auto-refresh cycles are controlled by the sdram controller. between auto-refresh cycles, the sdram is in power-down. current drained in power-down mode is higher than in self-refresh mode. ? deep power-down mode: (only available with mobile sdram) the sdram contents are lost, but the sdram does not drain any current. the sdram controller activates one low-power mode as soon as the sdram device is not selected. it is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the low power register. 28.7.5.1 self-refresh mode this mode is selected by programming the lpcb field to 1 in the sdramc low power register. in self-refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. all the inputs to the sdram device become ?don?t care? except sdcke, whic h remains low. as soon as the sdram device is selected, the sdram controller provides a sequence of commands and exits self-refresh mode. some low-power sdrams (e.g., mobile sdram) can refresh only one-quarter or half quarter or all banks of the sdram array. this feature reduc es the self refresh current. to configure this feature, temperature compensated self refresh (tcsr), partial array self refresh (pasr) and drive strength (ds) parameters must be set in the low power register and transmitted to the low-power sdram during the initialization. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d cas = 2 row m col a t rc = 8 t rcd = 3 dma row n
546 32003e?avr32?05/06 at32ap7000 the sdram device must remain in self-refresh mode for a minimum period of t ras and may remain in self-refresh mode for an indefinite period. this is described in figure 28-9 . figure 28-9. self-refresh mode behavior 28.7.5.2 low-power mode this mode is selected by programming the lpcb field to 2 in the sdramc low power register. power consumption is greater than in self-refresh mode. all the input and output buffers of the sdram device are deactivated except sdcke, which remains low. in contrast to self-refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). as no auto-refresh operations are performed by the sdram itself, the sdram controller carries out the refresh operation. the exit procedure is faster than in self-refresh mode. this is described in figure 28-10 . sdck sdcs ras cas sdramc_a[12:0] self refresh mode sdwe row t xsr = 3 sdcke write sdramc_srr srcb = 1 access request to the sdram controller
547 32003e?avr32?05/06 at32ap7000 figure 28-10. low-power mode behavior 28.7.5.3 deep power-down mode this mode is selected by programming the lpcb field to 3 in the sdramc low power register. when this mode is activated, all internal voltage generators inside the sdram are stopped and all data is lost. when this mode is enabled, the application must not access to the sdram until a new initializa- tion sequence is done (see ?sdram device initialization? on page 540 ). this is described in figure 28-11 . sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 sdcke low power mode
548 32003e?avr32?05/06 at32ap7000 figure 28-11. deep power-down mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d row n cke
549 32003e?avr32?05/06 at32ap7000 28.8 sdram controller user interface table 28-8. sdram controller memory map offset register name access reset state 0x00 sdramc mode register sd ramc_mr read/write 0x00000000 0x04 sdramc refresh timer regist er sdramc_tr read/write 0x00000000 0x08 sdramc configuration regist er sdramc_cr read/write 0x852372c0 0x0c sdramc high speed register sdramc_hsr read/write 0x00 0x10 sdramc low power register sdramc_lpr read/write 0x0 0x14 sdramc interrupt enable register sdramc_ier write-only ? 0x18 sdramc interrupt disable register sdramc_idr write-only ? 0x1c sdramc interrupt mask register sdramc_imr read-only 0x0 0x20 sdramc interrupt status register sdramc_isr read-only 0x0 0x24 sdramc memory device register sdramc_mdr read 0x0 0x28 - 0xfc reserved ? ? ?
550 32003e?avr32?05/06 at32ap7000 28.8.1 sdramc mode register register name :sdramc_mr access type : read/write reset value : 0x00000000 ? mode: sdramc command mode this field defines the command issued by the sdram controller when the sdram device is accessed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? mode table 28-9. mode description 0 0 0 normal mode. any access to the sdram is decoded normally. 0 0 1 the sdram controller issues a nop command when t he sdram device is accessed regardless of the cycle. 010 the sdram controller issues an ?all banks precharge? command when the sdram device is accessed regardless of the cycle. 011 the sdram controller issues a ?load mode register ? command when the sdram device is accessed regardless of the cycle. the address offset with respec t to the sdram device base address is used to program the mode register. for instance, when this mode is acti vated, an access to the ?sdram_base + offset? address generates a ?load mode register? command with the valu e ?offset? written to the sdram device mode register. 100 the sdram controller issues an ?auto-refresh? comm and when the sdram device is accessed regardless of the cycle. previously, an ?all banks precharge? command must be issued. 101 the sdram controller issues an extended load mode regi ster command when the sd ram device is accessed regardless of the cycle. the address offset with respec t to the sdram device base address is used to program the mode register. for instance, when this mode is acti vated, an access to the ?sdram_base + offset? address generates an ?extended load mode register? command with the value ?offset? written to the sdram device mode register. 1 1 0 deep power-down mode. enters deep power-down mode.
551 32003e?avr32?05/06 at32ap7000 28.8.2 sdramc refresh timer register register name :sdramc_tr access type : read/write reset value : 0x00000000 ? count: sdramc refresh timer count this 12-bit field is loaded into a timer that generates the refr esh pulse. each time the refresh pulse is generated, a refresh burst is initiated. the value to be loaded depends on the sdramc clock frequency (mck: master clock), the refresh rate of the sdram device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. to refresh the sdram device, this 12-bit field must be written. if this condition is not satisfied, no refresh command is issued and no refresh of the sdram device is carried out. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? count 76543210 count
552 32003e?avr32?05/06 at32ap7000 28.8.3 sdramc configuration register register name : sdramc_cr access type : read/write reset value : 0x852372c0 ? nc: number of column bits reset value is 8 column bits. ? nr: number of row bits reset value is 11 row bits. ? nb: number of banks reset value is two banks. 31 30 29 28 27 26 25 24 txsr tras 23 22 21 20 19 18 17 16 trcd trp 15 14 13 12 11 10 9 8 trc twr 76543210 dbw cas nb nr nc nc column bits 008 019 1010 1111 nr row bits 00 11 01 12 10 13 11 reserved nb number of banks 02 14
553 32003e?avr32?05/06 at32ap7000 ? cas: cas latency reset value is two cycles. in the sdramc, only a cas latency of one, two and three cycles is managed. ? dbw: data bus width reset value is 16 bits 0: data bus width is 32 bits. 1: data bus width is 16 bits. ? twr: write recovery delay reset value is two cycles. this field defines the write recovery time in numb er of cycles. number of cycles is between 0 and 15. ? trc: row cycle delay reset value is seven cycles. this field defines the delay between a refresh and an activate command in numbe r of cycles. number of cycles is between 0 and 15. ? trp: row precharge delay reset value is three cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 0 and 15. ? trcd: row to column delay reset value is two cycles. this field defines the delay between an activate comman d and a read/write command in number of cycles. number of cycles is between 0 and 15. ? tras: active to precharge delay reset value is five cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 0 and 15. ? txsr: exit self refr esh to active delay reset value is height cycles. this field defines the delay between scke set high and an activate command in numb er of cycles. number of cycles is between 0 and 15. cas cas latency (cycles) 00 reserved 01 1 10 2 11 3
554 32003e?avr32?05/06 at32ap7000 28.8.4 sdramc high speed register register name : sdramc_hsr access type : read/write ? da: decode cycle enable 0: decode cycle is disabled. 1: decode cycle is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????da
555 32003e?avr32?05/06 at32ap7000 28.8.5 sdramc low power register register name :sdramc_lpr access type : read/write reset value :0x0 ? lpcb: low-power configuration bits ? pasr: partial array self-refresh (only for low-power sdram) tcr parameter is transmitted to the sdram during initialization to specify whether only one quarter, one half quarter or all banks of the sdram array are enabled. disabled banks are not refreshed in self-refresh mode. this parameter must be set according to the sdram device specification. ? tcsr: temperature compensated self-r efresh (only for low-power sdram) tcsr parameter is transmitted to the sdram during initiali zation to set the refresh interval during self-refresh mode depending on the temperature of the low-power sdram. this parameter must be set according to the sdram device specification. ? ds: drive strength (only for low-power sdram) ds parameter is transmitted to the sdram during initialization to sele ct the sdram strength of data output. this parame- ter must be set according to the sdram device specification. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?? timeout ds tcsr 76543210 ? pasr ? ? lpcb 00 low power feature is inhibited: no power-down, self -refresh or deep power-down command is issued to the sdram device. 01 the sdram controller issues a self-refresh comm and to the sdram device, the sdclk clock is deactivated and the sdcke signal is set low. t he sdram device leaves the self refresh mode when accessed and enters it after the access. 10 the sdram controller issues a power-down command to the sdram device after each access, the sdcke signal is set to low. the sdram device leaves the power-down mode when accessed and enters it after the access. 11 the sdram controller issues a deep power-down command to the sdram device. this mode is unique to low-power sdram.
556 32003e?avr32?05/06 at32ap7000 ? timeout: time to define when low-power mode is enabled 00 the sdram controller activates the sdram low-power mo de immediately after the end of the last transfer. 01 the sdram controller activates the sdram low-powe r mode 64 clock cycles afte r the end of the last transfer. 10 the sdram controller activates the sdram low-power mode 128 clock cycles after the end of the last transfer. 11 reserved.
557 32003e?avr32?05/06 at32ap7000 28.8.6 sdramc interrupt enable register register name :sdramc_ier access type :write-only ? res: refresh error status 0: no effect. 1: enables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
558 32003e?avr32?05/06 at32ap7000 28.8.7 sdramc interrupt disable register register name :sdramc_idr access type :write-only ? res: refresh error status 0: no effect. 1: disables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
559 32003e?avr32?05/06 at32ap7000 28.8.8 sdramc interrupt mask register register name :sdramc_imr access type : read-only ? res: refresh error status 0: the refresh error interrupt is disabled. 1: the refresh error interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
560 32003e?avr32?05/06 at32ap7000 28.8.9 sdramc interrupt status register register name :sdramc_isr access type : read-only ? res: refresh error status 0: no refresh error has been detected since the register was last read. 1: a refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res
561 32003e?avr32?05/06 at32ap7000 28.8.10 sdramc memory device register register name :sdramc_mdr access type : read/write ? md: memory device type 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? md 00 sdram 01 low-power sdram 10 reserved 11 reserved.
562 32003e?avr32?05/06 at32ap7000 29. error corrected code (ecc) controller rev: 6143a 29.1 features ? hardware error corrected code (ecc) generation ? detection and correction by software ? supports nand flash and smartmedia ? devices with 8- or 16-bit data path. ? supports nand flash/smartmedia with page size s of 528, 1056, 2112 and 4224 bytes, specified by software 29.2 description nand flash/smartmedia devices contain by default invalid blocks which have one or more invalid bits. over the nand flash/smartmedia lifetime, additional invalid blocks may occur which can be detected/corrected by ecc code. the ecc controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. the ecc controller is capable of single bit error correction and 2-bit random detection. w hen nand flash/smartmedia have more than 2 bits of errors, the data cannot be corrected. the ecc user interface is compliant with the arm ? advanced peripheral bus (apb rev2). 29.3 block diagram figure 29-1. block diagram user interface ctrl/ecc algorithm static memory controller apb nand flash smartmedia logic ecc controller
563 32003e?avr32?05/06 at32ap7000 29.4 functional description a page in nand flash and smartmedia memories contains an area for main data and an addi- tional area used for redundancy (ecc). the page is organized in 8-bit or 16-bit words. the page size corresponds to the number of words in the main data plus the number of words in the extra area used for redundancy. the only configuration requir ed for ecc is the nand flash or the smartmedia page size (528/1056/2112/4224). page size is configured setting the pagesize field in the ecc mode register (ecc_mr). ecc is automatically computed as soon as a read (00h)/write (80h) command to the nand flash or the smartmedia is detected. read and write access must start at a page boundary. ecc is computed as soon as the counter reaches the page size. values in the ecc parity reg- ister (ecc_pr) and ecc nparity register (ecc_npr) are then valid and locked until a new start condition (read/wr ite command followed by fi ve access address cycles). 29.4.1 write access once the flash memory page is written, the computed ecc code is available in the ecc parity error (ecc_pr) and ecc_nparit y error (ecc_npr) registers. the ecc code value must be written by the software application at the end of the page, in the extra area used for redundancy. 29.4.2 read access after reading main data in the page area, the application can perform read access to the extra area used for redundancy. error detection is automatically performed by the ecc controller. the application can check the ecc status regi ster (ecc_sr) for any detected errors. it is up to the application to correct any detected error. ecc computation can detect four differ- ent circumstances: ? no error: xor between the ecc computation and the ecc code stored at the end of the nand flash or smartmedia page is equal to 0. no error flags in the ecc status register (ecc_sr). ? recoverable error: only the recerr flag in the ecc status register (ecc_sr) is set. the corrupted word offset in the read page is defined by the wordaddr field in the ecc parity register (ecc_pr). the corrupted bit position in the concerned word is defined in the bitaddr field in the ecc parity register (ecc_pr). ? ecc error: the eccerr flag in the ecc status register is set. an error has been detected in the ecc code stored in the flash memory. the position of the corrupted bit can be found by the application performing an xor between the parity and the nparity contained in the ecc code stored in the flash memory. ? non correctable error: the mulerr flag in the ecc status register is set. several unrecoverable errors have been detected in the flash memory page. ecc status register, ecc parity register and ecc nparity register are cleared when a read/write command is detected or a software register is enabled. for single bit error correction and double bit erro r detection (sec-ded) hsiao code is used. 32- bit ecc is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit
564 32003e?avr32?05/06 at32ap7000 words. of the 32 ecc bits, 26 bits are for line parity and 6 bits are for column parity. they are generated according to the schemes shown in figure 29-2 and figure 29-3 . figure 29-2. parity generation for 512/1024/2048/4096 8-bit words1 to calculate p8? to px? and p8 to px, apply the algorithm that follows. page size = 2 n for i =0 to n begin for (j = 0 to page_size_byte) begin if(j[i] ==1) p[2 i+3 ]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ] else p[2 i+3 ]?=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ]' end end bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' p16 p16' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 p8 p8' p16 p16' p32 p32 1st byte p32 2nd byte 3rd byte 4 th byte page size th byte (page size -1 )th byte px px' page size = 512 px = 2048 page size = 1024 px = 4096 page size = 2048 px = 8192 page size = 4096 px = 16384 (page size -2 )th byte (page size -3 )th byte p1 p1' p1' p1 p1 p1' p1' p1 p2 p2' p2 p2' p4 p4' p1=bit7(+)bit5(+)bit3(+)bit1(+)p1 p2=bit7(+)bit6(+)bit3(+)bit2(+)p2 p4=bit7(+)bit6(+)bit5(+)bit4(+)p4 p1'=bit6(+)bit4(+)bit2(+)bit0(+)p1' p2'=bit5(+)bit4(+)bit1(+)bit0(+)p2' p4'=bit7(+)bit6(+)bit5(+)bit4(+)p4'
565 32003e?avr32?05/06 at32ap7000 figure 29-3. parity generation for 512/1024/2048/4096 16-bit words 1st word 2nd word 3rd word 4th word (page size -3 )th word (page size -2 )th word (page size -1 )th word page size th word (+) (+)
566 32003e?avr32?05/06 at32ap7000 to calculate p8? to px? and p8 to px, apply the algorithm that follows. page size = 2 n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) p[2 i+3 ]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 n+3 ] else p[2 i+3 ]?=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)p[2 i+3 ]' end end
567 32003e?avr32?05/06 at32ap7000 29.5 ecc user interface table 29-1. ecc register mapping offset register register name access reset 0x00 ecc control register ecc_cr write-only 0x0 0x04 ecc mode register ecc_mr read/write 0x0 0x8 ecc status register ecc_sr read-only 0x0 0x0c ecc parity register ecc_pr read-only 0x0 0x10 ecc nparity register ecc_npr read-only 0x0 0x14-0xf8 reserved ? ? ? 0x14 - 0xfc reserved ? ? ?
568 32003e?avr32?05/06 at32ap7000 29.5.1 ecc control register name: ecc_cr access type: write-only ? rst: reset parity provides reset to current ecc by software. 1: reset secc parity and ecc nparity register 0: no effect 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????rst
569 32003e?avr32?05/06 at32ap7000 29.5.2 ecc mode register register name : ecc_mr access type : read/write ? pagesize: page size this field defines the page size of the nand flash device. a word has a value of 8 bits or 16 bits, depending on the nand flash or smartmedia memory organization. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? pagesize page size description 00 528 words 01 1056 words 10 2112 words 11 4224 words
570 32003e?avr32?05/06 at32ap7000 29.5.3 ecc status register register name : ecc_sr access type : read-only ? recerr: recoverable error 0 = no errors detected 1 = errors detected. if mul_error is 0, a single correctable error was detected. otherwise multiple uncorrected errors were detected ? eccerr: ecc error 0 = no errors detected 1 = a single bit error occurred in the ecc bytes. read both ecc parity and ecc parityn register, the error occurred at the location which contains a 1 in the least significant 16 bits. ? mulerr: multiple error 0 = no multiple errors detected 1 = multiple errors detected 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????mulerreccerrrecerr
571 32003e?avr32?05/06 at32ap7000 29.5.4 ecc parity register register name : ecc_pr access type : read-only during a page write, the value of the entire register must be written in the extra area used for redundancy (for a 512-byte page size: address 512-513) ? bitaddr during a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. ? wordaddr during a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organiza- tion) where an error occurred, if a single error was detected. if multiple errors were detected, this value is meaningless. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 wordaddr 76543210 wordaddr bitaddr
572 32003e?avr32?05/06 at32ap7000 29.5.5 ecc nparity register register name : ecc_npr access type : read-only ? nparity: during a write, the value of this register must be written in the extra area used for redundancy (for a 512-byte page size: address 514-515) 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 nparity 76543210 nparity
573 32003e?avr32?05/06 at32ap7000 30. multimedia card interface (mci) rev: 6101c 30.1 features ? compatible with multimedia card specification version 2.2 ? compatible with sd memory card specification version 1.0 ? cards clock rate up to ma ster clock divided by 2 ? embedded power management to slow down clock rate when not used ? supports 2 multiplexed slot(s) ? each slot for either a multimediacard bus (up to 30 cards) or an sd memory card ? support for stream, block and mu lti-block data read and write ? supports connection to dma controller ? minimizes processor interventi on for large buffer transfers 30.2 description the mci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. the mci supports stream, block and multi-block data read and write, and is compatible with a dma controller, minimizing processor intervention for large buffer transfers. the mci operates at a rate of up to master cloc k divided by 2 and supports the interfacing of 2 slot(s). each slot may be used to interface with a multimediacard bus (up to 30 cards) or with a sd memory card. only one slot can be selected at a time (slots are multiplexed). a bit field in the sd card register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the multimediacard on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). the sd memory card interface also supports multimedia card operations. the main differences between sd and multimedia cards are the initialization process and the bus topology.
574 32003e?avr32?05/06 at32ap7000 30.3 block diagram figure 30-1. block diagram mci interface interrupt control pio pdc / dma apb bridge pm mck mci interrupt mcck mccda mcda0 mcda1 mcda2 mcda3 mccdb mcdb0 mcdb1 mcdb2 mcdb3 apb
575 32003e?avr32?05/06 at32ap7000 30.4 application block diagram figure 30-2. application block diagram 30.5 pin name list note: 1. i: input, o: output, pp: push/pull, od: open drain. 23456 17 mmc 23456 17 8 sdcard 9 physical layer mci interface application layer ex: file system, audio, security, etc. table 30-1. i/o lines description pin name pin description type (1) comments mccda/mccdb command/response i/o/pp/ od cmd of an mmc or sd card mcck clock i/o clk of an mmc or sd card mcda0 - mcda3 data 0..3 of slot a i/o/pp dat0 of an mmc dat[0..3] of an sd card mcdb0 - mcdb3 data 0..3 of slot b i/o/pp dat0 of an mmc dat[0..3] of an sd card
576 32003e?avr32?05/06 at32ap7000 30.6 product dependencies 30.6.1 i/o lines the pins used for interfacing the multimedia cards or sd cards may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral functions to mci pins. 30.6.2 power management the mci may receive a clock from the power manager (pm), so the programmer must first con- figure the pm to enable the mci clock. 30.6.3 interrupt the mci interface has an interrupt line connected to the interrupt controller (intc). handling the mci interrupt requires programming the intc before configuring the mci. 30.7 bus topology figure 30-3. multimedia memory card bus topology the multimedia card communication is based on a 7- pin serial bus interface. it has three com- munication lines and four supply lines. note: 1. i: input, o: output, pp : push/pull, od: open drain. table 30-2. bus topology pin number name type (1) description mci pin name (slot x) 1 rsv nc not connected 2 cmd i/o/pp/od command/response mccdx 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data 0 mcdx0 23456 17 mmc
577 32003e?avr32?05/06 at32ap7000 figure 30-4. mmc bus connections (one slot) figure 30-5. sd memory card bus topology the sd memory card bus includes the signals listed in table 30-3 on page 577 . note: 1. i: input, o: output, pp: push pull, od: open drain table 30-3. sd memory card bus signals pin number name type (1) description mci pin name (slot x) 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcdx3 2 cmd pp command/response mccdx 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcdx0 8 dat[1] i/o/pp data line bit 1 mcdx1 9 dat[2] i/o/pp data line bit 2 mcdx2 23456 1 7 23456 1 7 23456 17 mcda0 mccda mcck mmc1 mmc2 mmc3 mci 23456 17 8 sd card 9
578 32003e?avr32?05/06 at32ap7000 figure 30-6. sd card bus connections with two slots figure 30-7. mixing multimedia and sd memory cards with two slots when the mci is configured to operate with sd memory cards, the width of the data bus can be selected in the sdcr regi ster. clearing the sdcbus bit in this register means that the width is one bit; setting it means that the width is four bits. in the case of multimedia cards, only the data line 0 is used. the other data lines can be used as independent pios. 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 1 9 23456 17 8 sd card 2 9 mcdb0 - mcdb3 mccdb 23456 1 7 23456 1 7 23456 17 mmc1 mmc2 mmc3 mcda0 mcck mccda 23456 17 8 sd card 9 mcdb0 - mcdb3 mccdb
579 32003e?avr32?05/06 at32ap7000 30.8 multimedia card operations after a power-on reset, the cards are initialized by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: ? command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. ? response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. a response is transferred serially on the cmd line. ? data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a sess ion address assigned during the initialization phase by the bus controller to all currently connected cards. their unique cid number identifies individual cards. the structure of commands, resp onses and data blocks is descr ibed in the multimedia-card system specification version 2.2. see also table 30-4 on page 580 . multimediacard bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their infor- mation directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock mcck. two types of data transfer commands are defined: ? sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. ? block-oriented commands: these commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop co mmand follows on the cm d line similarly to the sequential read. the mci provides a set of registers to perform the entire range of multimedia card operations. 30.8.1 command - response operation after reset, the mci is disabled and becomes va lid after setting the mcien bit in the cr (mci control register). the bit pwsen saves power by dividing the mci clock by 2 pwsdiv + 1 when the bus is inactive. the command and the response of the card are clocked out with the rising edge of the mcck. all the timings for multimedia card are defined in the multimediacard sy stem specification ver- sion 2.2. the two bus modes (open drain and push/pull) needed to process all the operations are defined in the mci command register. the cmdr allows a command to be carried out.
580 32003e?avr32?05/06 at32ap7000 for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the cmdr control register are described in table 30-4 and table 30-5 . note: bcr means broadcast command with response. the argr contains the argument field of the command. to send a command, the user must perform the following steps: ? fill the argument register (a rgr) with the command argument. ? set the command register (cmdr) (see table 30-5 ). the command is sent immediately after writing the command register. the status bit cmdrdy in the status register (sr) is asserted when the command is completed. if the command requires a response, it can be read in the mci response register (rspr). the response size can be from 48 bits up to 136 bits depending on the command. the mci embeds an error detection to pre- vent any corrupted data during the transfer. the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (ier) allows using an interrupt method. host command n id cycles cid cmd s t content crc e z ****** z s t content z z z table 30-4. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 30-5. fields and values for cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to response) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command)
581 32003e?avr32?05/06 at32ap7000 figure 30-8. command/response functional flow diagram note: 1. if the command is send_op_cond, the crc error flag is always present (refer to r3 response in the multimediacard specification). 30.8.2 data transfer operation the multimedia card allo ws several read/write operations (single block, multiple blocks, stream, etc.). these operations can be done using the a dma cont roller. in all cases, the block length must be defined in the mode register. 30.8.3 read operation the following flowchart shows how to read a single block with or without us e of dma facilities. in this example, a polling method is used to wait for the end of read. similarly, the user can config- ure the interrupt enable register (ier) to trigger an interrupt at the end of read. these two methods can be applied for all multimedia card read functions. return ok return error (1) set the command argument mci_argr = argument (1) set the command mci_cmdr = command read mci_sr cmdrdy status error flags? read response if required ye s wait for command ready status flag check error bits in the status register (1) 0 1
582 32003e?avr32?05/06 at32ap7000 figure 30-9. read functional flow diagram note: 1. this command is supposed to have been correctly sent (see figure 30-8 ). read status register mci_sr send command sel_desel_card to select the card send command set_blocklen read with dma reset the pdcmode bit mci_mr &= ~pdcmode set the block length (in bytes) mci_mr |= (blocklenght <<16) number of words to read = 0 ? poll the bit rxrdy = 0? read data = mci_rdr number of words to read = number of words to read -1 send command read_single_block (1) ye s set the block length (in bytes) mci_mr |= (blocklength << 16) configure the dma controller send command read_single_block (1) wait for data from mmc data received? no return ye s no no ye s ye s no number of words to read = blocklength/4 dma transfer complete ? no return ye s
583 32003e?avr32?05/06 at32ap7000 30.8.4 write operation in write operation, the mci mode register (mr) is used to define the padding value when writing non-multiple block size. if the bit dmapadv is 0, then 0x00 value is us ed when padding data, otherwise 0xff is used. the following flowchart shows how to write a single block with or without use of dma facilities. polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (imr). this flowchart can be adapted to perform all the multimedia card write functions.
584 32003e?avr32?05/06 at32ap7000 figure 30-10. write functional flow diagram note: 1. this command is supposed to have been correctly sent (see figure 30-8 ). send command sel_desel_card to select the card send command set_blocklen reset the pdcmode bit mci_mr &= ~pdcmode set the block length mci_mr |= (blocklenght <<16) send command write_single_block (1) no read status register mci_sr number of words to write = 0 ? poll the bit txrdy = 0? mci_tdr = data to write number of words to write = number of words to write -1 ye s return no ye s no number of words to write = blocklength/4 write with dma set the block length (in bytes) mci_mr |= (blocklength << 16) configure the dma controller send command write_single_block (1) wait for data transfer to mmc complete data transmitted? no ye s ye s dma transfer complete ? no return ye s
585 32003e?avr32?05/06 at32ap7000 30.9 sd card operations the multimedia card interface allows processing of sd memory card (secure digital memory card) commands. the sd memory card includes a copyright protection mechanism that com- plies with the security requirements of the sd mi standard (secure digital music initiative), is faster and applicable to higher memory capacity. the physical form factor, pin assignment and data transfer protocol are forward-com-patible with the multimedia card with some additions. the sd memory card communication is ba sed on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specifica- tion. the main difference between the sd memory card and the multimedia card is the initialization process. the sd card register (sdcr) allows select ion of the card slot and the data bus width. the sd card bus allows dynamic configuration of the number of data lines. after power up, by default, the sd memory card uses only dat0 for data transfer. after initialization, the host can change the bus width (number of active data lines).
586 32003e?avr32?05/06 at32ap7000 30.10 user interface note: 1. the response register can be read by n accesses at the same rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. table 30-6. register mapping offset register register name read/write reset 0x00 control register cr write ? 0x04 mode register mr read/write 0x0 0x08 data timeout register dtor read/write 0x0 0x0c sd card register sdcr read/write 0x0 0x10 argument register argr read/write 0x0 0x14 command register cmdr write ? 0x18 - 0x1c reserved ? ? ? 0x20 response register (1) rspr read 0x0 0x24 response register (1) rspr read 0x0 0x28 response register (1) rspr read 0x0 0x2c response register (1) rspr read 0x0 0x30 receive data register rdr read 0x0 0x34 transmit data register tdr write ? 0x38 - 0x3c reserved ? ? ? 0x40 status register sr read 0xc0e5 0x44 interrupt enable register ier write ? 0x48 interrupt disable register idr write ? 0x4c interrupt mask register imr read 0x0 0x100-0x124 reserved for the pdc ? ? ?
587 32003e?avr32?05/06 at32ap7000 30.10.1 mci control register name: cr access type: write-only ? mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. ? mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. ? pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. warning: before enabling this mode, the user must set a value different from 0 in the pwsdiv field (mode register mr) . ? pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. ? swrst: software reset 0 = no effect. 1 = resets the mci. a software triggered hardware reset of the mci interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? pwsdis pwsen mcidis mcien
588 32003e?avr32?05/06 at32ap7000 30.10.2 mci mode register name: mr access type: read/write ? clkdiv: clock divider multimedia card interface clock (mcck) is master clock (mck) divided by (2*(clkdiv+1)). ? pwsdiv: power saving divider multimedia card interface clock is divided by 2 (pwsdiv) + 1 when entering power saving mode. warning: this value must be different from 0 before enabling the power save mode in the cr (pwsen bit). ? dmapadv: dma padding value 0 = 0x00 value is used when padding data in write transfer. 1 = 0xff value is used when padding data in write transfer. ? blklen: data block length this field determines the size of the data block. bits 16 and 17 must be written to 0. 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 -dmapadv??? pwsdiv 76543210 clkdiv
589 32003e?avr32?05/06 at32ap7000 30.10.3 mci data timeout register name: dtor access type: read/write ? dtocyc: data timeout cycle number ? dtomul: data ti meout multiplier these fields determine the maximum number of master clock cycles that the mci waits between two data block transfers. it equals (dtocyc x multiplier). multiplier is defined by dtomul as shown in the following table: if the data time-out set by dtocyc and dtomul has been exceeded, the data time-out error flag (dtoe) in the mci status register (sr) raises. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? dtomul dtocyc dtomul multiplier 0001 00116 010128 011256 1001024 1014096 1 1 0 65536 1 1 1 1048576
590 32003e?avr32?05/06 at32ap7000 30.10.4 mci sd card register name: sdcr access type: read/write ? sdcsel: sd card selector 0 = sdcard slot a selected. 1= sdcard slot b selected. ? sdcbus: sd card bus width 0 = 1-bit data bus 1 = 4-bit data bus 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sdcbus ? ? ? sdcsel
591 32003e?avr32?05/06 at32ap7000 30.10.5 mci argument register name: argr access type: read/write ? arg: command argument 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg
592 32003e?avr32?05/06 at32ap7000 30.10.6 mci command register name: cmdr access type: write-only this register is write-protecte d while cmdrdy is 0 in sr. if an interrupt command is sent, this register is only writeable by an interrupt response (field spcmd). this means that the current command execution cannot be interrupted or modified. ? cmdnb: command number ? rsptyp: response type ? ? spcmd: special command 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? trtyp trdir trcmd 15 14 13 12 11 10 9 8 ? ? ? maxlat opdcmd spcmd 76543210 rsptyp cmdnb rsp response type 0 0 no response. 0 1 48-bit response. 1 0 136-bit response. 1 1 reserved. spcmd command 0 0 0 not a special cmd. 001 initialization cmd: 74 clock cycles for in itialization sequence. 010 synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 011reserved. 100 interrupt command: corresponds to the interrupt mode (cmd40). 101 interrupt response: corresponds to the interrupt mode (cmd40).
593 32003e?avr32?05/06 at32ap7000 ? opdcmd: open drain command 0 = push pull command 1 = open drain command ? maxlat: max latency for command to response 0 = 5-cycle max latency 1 = 64-cycle max latency ? trcmd: transfer command ? trdir: transfer direction 0 = write 1 = read ? trtyp: transfer type trcmd transfer type 0 0 no data transfer 0 1 start data transfer 1 0 stop data transfer 11reserved trtyp transfer type 00block 0 1 multiple block 10stream 11reserved
594 32003e?avr32?05/06 at32ap7000 30.10.7 mci sd response register name: rspr access type: read-only ? rsp: response note: 1. the response register can be read by n accesses at the same rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp
595 32003e?avr32?05/06 at32ap7000 30.10.8 mci sd receive data register name: rdr access type: read-only ? data: data to read 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
596 32003e?avr32?05/06 at32ap7000 30.10.9 mci sd transmit data register name: tdr access type: write-only ? data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
597 32003e?avr32?05/06 at32ap7000 30.10.10 mci status register name: sr access type: read-only ? cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the cmdr. ? rxrdy: receiver ready 0 = no data has been received since the last read of rdr. 1 = data has been received since the last read of rdr. ? txrdy: transmit ready 0= the last data written in tdr has not yet been transferred in the shift register. 1= the last data written in tdr has been transferred in the shift register. ? dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data tran sfer is still in progress, including crc16 calculatio n. cleared at the end of the crc16 calculation. ? notbusy: data not busy 0 = the card is not ready for new data transfer. 1 = the card is ready for new data transfer (data line dat0 high corresponding to a free data receive buffer in the card). ? rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the cmdr. ? rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. ? rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the response. cleared when writing in the cmdr. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 - - ?????? 76543210 - - notbusy dtip - txrdy rxrdy cmdrdy
598 32003e?avr32?05/06 at32ap7000 ? rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the cmdr. ? rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the cmdr has been exceeded. cleared when writing in the cmdr. ? dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared when reading sr. ? dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in dtor has been exceeded. cleared when reading sr. ? ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. ? unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid inform ation (not written). cleared when sending a new data transfer command.
599 32003e?avr32?05/06 at32ap7000 30.10.11 mci interrupt enable register name: ier access type: write-only ? cmdrdy: command ready interrupt enable ? rxrdy: receiver ready interrupt enable ? txrdy: transmit ready interrupt enable ? dtip: data transfer in progress interrupt enable ? notbusy: data not busy interrupt enable ? rinde: response index er ror interrupt enable ? rdire: response direction error interrupt enable ? rcrce: response crc error interrupt enable ? rende: response end bit error interrupt enable ? rtoe: response time-out error interrupt enable ? dcrce: data crc error interrupt enable ? dtoe: data time-out error interrupt enable ? ovre: overrun in terrupt enable ? unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 - - ?????? 76543210 - - notbusy dtip - txrdy rxrdy cmdrdy
600 32003e?avr32?05/06 at32ap7000 30.10.12 mci interrupt disable register name: idr access type: write-only ? cmdrdy: command ready interrupt disable ? rxrdy: receiver ready interrupt disable ? txrdy: transmit ready interrupt disable ? dtip: data transfer in progress interrupt disable ? notbusy: data not busy interrupt disable ? rinde: response index er ror interrupt disable ? rdire: response direction error interrupt disable ? rcrce: response crc error interrupt disable ? rende: response end bit error interrupt disable ? rtoe: response time-out error interrupt disable ? dcrce: data crc error interrupt disable ? dtoe: data time-out er ror interrupt disable ? ovre: overrun in terrupt disable ? unre: underrun interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 - - ?????? 76543210 - - notbusy dtip - txrdy rxrdy cmdrdy
601 32003e?avr32?05/06 at32ap7000 30.10.13 mci interrupt mask register name: imr access type: read-only ? cmdrdy: command ready interrupt mask ? rxrdy: receiver ready interrupt mask ? txrdy: transmit ready interrupt mask ? dtip: data transfer in progress interrupt mask ? notbusy: data not busy interrupt mask ? rinde: response index error interrupt mask ? rdire: response directio n error interrupt mask ? rcrce: response crc error interrupt mask ? rende: response end bit error interrupt mask ? rtoe: response time-out error interrupt mask ? dcrce: data crc error interrupt mask ? dtoe: data time-out error interrupt mask ? ovre: overrun interrupt mask ? unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 - - ?????? 76543210 - - notbusy dtip - txrdy rxrdy cmdrdy
602 32003e?avr32?05/06 at32ap7000 31. ethernet mac 10/100 (macb) rev: 6119b 31.1 features ? compatible with ieee standard 802.3 ? 10 and 100 mbit/s operation ? full- and half-duplex operation ? statistics counter registers ? mii/rmii interface to the physical layer ? interrupt genera tion to signal receive an d transmit completion ? dma master on receive and transmit channels ? transmit and receive fifos ? automatic pad and crc generation on transmitted frames ? automatic discard of frames received with errors ? address checking logic supports up to four specific 48-bit addresses ? supports promiscuous mode where all vali d received frames are copied to memory ? hash matching of unicast and multicast destination addresses ? external address matching of received frames ? physical layer management through mdio interface ? half-duplex flow control by forcing collisions on incoming frames ? full-duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames ? support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames ? multiple buffers per receive and transmit frame ? wake-on-lan support ? jumbo frames up to 10240 bytes supported 31.2 description the macb module implements a 10/100 ethernet mac compatible with the ieee 802.3 stan- dard using an address checker, statistics and co ntrol registers, receive and transmit blocks, and a dma interface. the address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis- ter for matching multicast and unicast addresses. it can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. the statistics register block contains register s for counting various types of events associated with transmit and receive operations. these register s, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with ieee 802.3.
603 32003e?avr32?05/06 at32ap7000 31.3 block diagram figure 31-1. macb block diagram apb slave register interface dma interface address checker statistics registers control registers ethernet receive ethernet transmit mdio mii/rmii rx fifo tx fifo ahb master
604 32003e?avr32?05/06 at32ap7000 31.4 functional description figure 31-1 on page 603 illustrates the different blocks of the macb module. the control registers drive the mdio interface, setup dma activity, start frame transmission and select modes of operation such as full- or half-duplex. the receive block checks for valid preamble, fcs, alignment and length, and presents received frames to the address checking block and dma interface. the transmit block takes data from the dma interface, adds preamble and, if necessary, pad and fcs, and transmits data according to the csma/cd (carrier sense multiple access with col- lision detect) protocol. the start of transmission is deferred if crs (carrier sense) is active. if col (collision) becomes active during transmission, a jam se quence is asserted and the transmission is retried after a random back off. crs and col have no effect in full duplex mode. the dma block connects to external memory thro ugh its ahb bus interface. it contains receive and transmit fifos for buffering frame data. it loads the transmit fifo and empties the receive fifo using ahb bus master operations. receive da ta is not sent to memory until the address checking logic has determined that the frame should be copied. receive or transmit frames are stored in one or more buffers. receive buffers have a fixed length of 128 bytes. transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. the dma block manages the transmit and receive framebuffer queues. these queues can hold mul- tiple frames. 31.4.1 memory interface frame data is transferred to and from the macb through the dma interface. all transfers are 32- bit words and may be single accesses or bursts of 2, 3 or 4 words. burst accesses do not cross sixteen-byte boundaries. bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. the dma controller performs six types of operation on the bus. in order of priority, these are: 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write 31.4.1.1 fifo the fifo depths are 124 bytes. data is typically transferred into and out of the fifos in bursts of four words. for receive, a bus request is asserted when the fifo contains four words and has space for three more. for trans- mit, a bus request is generated when there is space for four words, or when there is space for two words if the next transfer is to be only one or two words. thus the bus latency must be less than the time it takes to load the fifo and transmit or receive three words (12 bytes) of data. at 100 mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. in addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the
605 32003e?avr32?05/06 at32ap7000 fifos. for a 60 mhz master clock this takes 100 ns, making the bus latency requirement 860 ns. 31.4.1.2 receive buffers received frames, optionally including crc/fcs, ar e written to receive buffers stored in mem- ory. each receive buffer is 128 bytes long. the start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. the receive buffer start location is a word address. for the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. if the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. if the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zer oes except for the ?start of frame? bit and the offset bits, if appropriate. bit zero of the address field is written to one to show the buffer has been used. the receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. the final buff er descriptor status word contains the complete frame status. refer to table 31-1 for details of the receive buffer descriptor list. table 31-1. receive buffer descriptor entry bit function word 0 31:2 address of beginning of buffer 1 wrap - marks last descriptor in receive buffer descriptor list. 0 ownership - needs to be zero for the macb to write data to the receive buffer. the macb sets this to one once it has successfully written a frame to memory. software has to clear this bit before the buffer can be used again. word 1 31 global all ones broadcast address detected 30 multicast hash match 29 unicast hash match 28 external address match 27 reserved for future use 26 specific address register 1 match 25 specific address register 2 match 24 specific address register 3 match 23 specific address register 4 match 22 type id match 21 vlan tag detected (i.e., type id of 0x8100) 20 priority tag detected (i.e., type id of 0x8100 and null vlan identifier) 19:17 vlan priority (only valid if bit 21 is set) 16 concatenation format indicator (cfi) bit (only valid if bit 21 is set)
606 32003e?avr32?05/06 at32ap7000 to receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. bit zero must be written with zero. bit one is the wrap bit and indicates the last entry in the list. the start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. as soon as the receive block starts writing received frame data to the receive fifo, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. if the filter block then indicates that the frame should be copied to memory, the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recov- ered. if the current buffer pointer has its wrap bit set or is the 1024 th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. otherwise, the next receive buffer location is read from the next word in memory. there is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. this is added with the valu e originally written to the receive buffer queue pointer register to produce a pointer into the list. a read of the receive buffer queue pointer reg- ister returns the pointer value, which is the queue entry currently being accessed. the counter is reset after receive status is written to a descript or that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. the value written to the receive buffer pointer regis- ter may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. the system bus specification states that bursts should not cross 1k boundaries. as receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three signi ficant bits set to zero. as receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used . if a receive error is detected the receive buffer currently being written is recovered. previous buffers are not recovered. software should search through the used bits in the buffer descriptors to find out how many frames have been received. it should be checking the start-of-frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are used. for crc errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. 15 end of frame - when set the buffer contains the end of a frame. if end of frame is no t set, then the only other valid status are bits 12, 13 and 14. 14 start of frame - when set the buffer contains the start of a frame. if both bits 15 a nd 14 are set, then the buffer contains a whole frame. 13:12 receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. updated with the current values of the network configuration register. if jum bo frame mode is enabled through bit 3 of the network configuration register, then bits 13: 12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. 11:0 length of frame including fcs (if selected). bits 13:12 are also used if jumbo frame mode is selected. table 31-1. receive buffer descrip tor entry (continued) bit function
607 32003e?avr32?05/06 at32ap7000 for a properly working ethernet system, there should be no excessively long frames or frames greater than 128 bytes with crc/ fcs errors. collision fragments are less than 128 bytes long. therefore, it is a rare occurrence to find a frame fragment in a receive buffer. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dma block sets the buffer not available bit in the receive status register and triggers an interrupt. if bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. a receive overrun condition occurs when bus was not granted in time or because hresp was not ok (bus error). in a receive overrun conditi on, the receive overrun interrupt is asserted and the buffer currently being written is recovered. the next frame received with an address that is recognized reuses the buffer. if bit 17 of the network configuration register is set, the fcs of received frames shall not be cop- ied to memory. the frame length indicated in the receive status field shall be reduced by four bytes in this case. 31.4.1.3 transmit buffer frames to be transmitted are stored in one or more transmit buffers. transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in ieee standard 802.3. zero length buffers are allowed. the maximum number of buffers permitted for each transmit frame is 128. the start location for each transmit buffer is stored in memory in a list of transmit buffer descrip- tors at a location pointed to by the transmit buffer queue pointer register. each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. frames can be transmitted with or without automatic crc gen- eration. if crc is automatically generated, padding is also automatically generated to take frames to a minimum length of 64 bytes. table 31-2 on page 608 defines an entry in the transmit buffer descriptor list. to transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in the fi rst word of each list entry. the second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with crc and whether the buffer is the last buffer in the frame. after transmission, the control bits are written back to the second word of the first buffer along with the ?used? bit and other status information. before a transmission, bit 31 is the ?used? bit which must be zero when the control word is read. it is written to one when a frame has been transmitted. bits 27, 28 and 29 indicate various transmit error conditions. bit 30 is the ?wrap? bit which can be set for any buffer within a frame. if no wrap bit is encountered after 1024 descrip- tors, the queue pointer rolls over to the start. the transmit buffer queue pointer register must not be written while transmit is active. if a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. if transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. note that disabling receive does not have the same effect on the receive queue pointer.
608 32003e?avr32?05/06 at32ap7000 once the transmit queue is init ialized, transmit is activate d by writing to bit 9, the transmit start bit of the network control register. transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writ ing to the transmit halt bit of the network control register. (transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) rewrit ing the start bit while transmission is active is allowed. transmission control is implemented with a tx_go variable which is readable in the transmit sta- tus register at bit location 3. the tx_go variable is reset when: ? transmit is disabled ? a buffer descriptor with its ownership bit set is read ? a new value is written to the transmit buffer queue pointer register ? bit 10, tx_halt, of the network control register is written ? there is a transmit error such as too many retries or a transmit underrun. to set tx_go, write to bit 9, tx_start, of the network control register. transmit halt does not take effect until any ongoing transmit finishes. if a collision occurs during transmission of a multi- buffer frame, transmission automatically restarts from the first buffer of the frame. if a ?used? bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. transmission stops, tx_er is asserted and the fcs is bad. if transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. software needs to re-initialize the transmit queue after a trans- mit error. if transmission stops due to a ?used? bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written table 31-2. transmit buffer descriptor entry bit function word 0 31:0 byte address of buffer word 1 31 used. needs to be zero for the macb to read data from the tran smit buffer. the macb sets this to one for the first buffer of a frame once it has been successfully transmitted. software has to clear this bit before the buffer can be used again. note: this bit is only set for the first buffer in a frame unlike receive where all buffers have the used bit set once used. 30 wrap. marks last descriptor in transmit buffer descriptor list. 29 retry limit exceeded, transmit error detected 28 transmit underrun, occurs either when hresp is not ok (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. 27 buffers exhausted in mid frame 26:17 reserved 16 no crc. when set, no crc is appended to the current frame. this bit only needs to be set for the last buffer of a frame.
609 32003e?avr32?05/06 at32ap7000 31.4.2 transmit block this block transmits frames in accordance wi th the ethernet ieee 802.3 csma/cd protocol. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo a word at a time. data is transmi tted least significant nibble first. if necessary, padding is added to increase the frame length to 60 bytes. crc is calculated as a 32-bit polyno- mial. this is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. if the no crc bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor crc are appended. in full-duplex mode, frames are transmitted immediately. back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. in half-duplex mode, the transmitter checks carrier sense. if asserted, it waits for it to de-assert and then starts transmission afte r the interframe gap of 96 bit times. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and retries transmission after the back off time has elapsed. the back-off time is based on an xor of the 10 least significant bits of the data coming from the transmit fifo and a 10-bit pseudo random number. the number of bits used depends on the number of collisions seen. after the first collision, 1 bit is used, after the second 2, and so on up to 10. above 10, all 10 bits are used. an error is indicated and no further attempts are made if 16 attempts cause collisions. if transmit dma underruns, bad crc is automa tically appended using the same mechanism as jam insertion and the tx_er signal is asserted. in a properly configured system, this should never happen. if the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. this provides a way of implementing flow control in half-duplex mode. 31.4.3 pause frame support the start of an 802.3 pause frame is as follows: the network configuration register contains a receive pause enable bit (13). if a valid pause frame is received, the pause time register is updated with the frame?s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. an interrupt 15 last buffer. when set, this bit indicates the last buffer in the current frame has been reached. 14:11 reserved 10:0 length of buffer table 31-2. transmit buffer descrip tor entry (continued) bit function table 31-3. start of an 802.3 pause frame destination address source address type (mac control frame) pause opcode pause time 0x0180c2000001 6 bytes 0x8808 0x0001 2 bytes
610 32003e?avr32?05/06 at32ap7000 (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. if bit 13 is set in the network configuration register and the value of the pause time reg- ister is non-zero, no new frame is transmitted until the pause time register has decremented to zero. the loading of a new pause time, and hence the pausing of transmission, only occurs when the macb is configured for full-duplex operation. if the macb is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is st ill triggered. a valid pause frame is defined as having a destin ation address that matches either the address stored in specific address register 1 or matches 0x0180c2000001 and has the mac control frame type id of 0x8808 and the pause opcode of 0x0001. pause frames that have fcs or other errors are treated as invalid and are discarded. valid pause frames received increment the pause frame received statistic register. the pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. for test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. if the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. an interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt mask register). auto matic transmission of pause frames is supported through the transmit pause frame bits of the network control register and the tx_pause and tx_pause_zero inputs. if either bit 11 or bit 12 of the network control register is written to with a 1, or if the input signal tx_pause is toggled, a pause frame is transmitted only if full duplex is selected in the network configuration register and transmit is enabled in the network control register. pause frame transmission occurs immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. the transmitted pause frame is comprised of the items in the following list: ? a destination address of 01-80-c2-00-00-01 ? a source address taken from the specific address 1 register ? a type id of 88-08 (mac control frame) ? a pause opcode of 00-01 ? a pause quantum ? fill of 00 to take the frame to minimum frame length ? valid fcs the pause quantum used in the generated frame depends on the trigger source for the frame as follows: 1. if bit 11 is written with a one, the pause quantum comes from the transmit pause quan- tum register. the transmit pause quantum register resets to a value of 0xffff giving a maximum pause quantum as a default. 2. if bit 12 is written with a one, the pause quantum is zero. 3. if the tx_pause input is toggled and the tx_pause_zero input is held low until the next toggle, the pause quantum comes from the transmit pause quantum register. 4. if the tx_pause input is toggled and the tx_pause_zero input is held high until the next toggle, the pause quantum is zero.
611 32003e?avr32?05/06 at32ap7000 after transmission, no interrupts are generated and the only statistics register that is incre- mented is the pause frames transmitted register. 31.4.4 receive block the receive block checks for valid preamble, fcs, alignment and length, presents received frames to the dma block and stores the frames destination address for use by the address checking block. if, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the dma bl ock. the dma block then ceases sending data to memory. at the end of frame reception, the receive block indicates to the dma block whether the frame is good or bad. the dma block recovers the current receive buffer if the frame was bad. the receive block signals the register block to increment the alignment error, the crc (fcs) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. the enable bit for jumbo frames in the network configuration register allows the macb to receive jumbo frames of up to 10240 bytes in size. this operation does not form part of the ieee802.3 specification and is disabled by default. when ju mbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 31.4.5 address checking block the address checking (or filter) block indicates to the dma block which receive frames should be copied to memory. whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame?s destination add ress. in this implementation of the macb, the frame?s source address is not checked. provided that bit 18 of the network configuration regis- ter is not set, a frame is not copied to memory if the macb is transmitting in half duplex mode at the time a destination address is received. if bit 18 of the network configuration register is set, frames can be received while transmitting in half-duplex mode. ethernet frames are transmitted a byte at a time, least significant bit first. the first six bytes (48 bits) of an ethernet frame make up the destination address. the first bit of the destination address, the lsb of the first byte of the frame, is the group/individual bit: this is one for multicast addresses and zero for unicast. the all ones address is the broadcast address, and a special case of multicast. the macb supports recognition of four specific addresses. each specific address requires two registers, specific address register bottom and specific address register top. specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. the addresses st ored can be specific, group, local or universal. the destination address of received frames is compared against the data stored in the specific address registers once they have been activated. the addresses are deactivated at reset or when their corresponding specific a ddress register bottom is written. they are activated when specific address register top is written. if a receive frame address ma tches an active address, the frame is copied to memory.
612 32003e?avr32?05/06 at32ap7000 the following example illustrates the use of the address match registers for a mac address of 21:43:65:87:a9:cb. preamble 55 sfd d5 da (octet0 - lsb) 21 da(octet 1) 43 da(octet 2) 65 da(octet 3) 87 da(octet 4) a9 da (octet5 - msb) cb sa (lsb) 00 sa 00 sa 00 sa 00 sa 00 sa (msb) 43 sa (lsb) 21 the sequence above shows the beginning of an et hernet frame. byte order of transmission is from top to bottom as shown. for a successful match to specific address 1, the following address matching registers must be set up: ? base address + 0x98 0x87654321 (bottom) ? base address + 0x9c 0x0000cba9 (top) and for a successful match to the type id register, the following should be set up: ? base address + 0xb8 0x00004321 31.4.6 broadcast address the broadcast address of 0xffffffffffff is recognized unless the ?no broadcast? bit in the network configuration register is set. 31.4.7 hash addressing the hash address register is 64 bits long and ta kes up two locations in the memory map. the least significant bits are stored in hash register bottom and the most significant bits in hash reg- ister top. the unicast hash enable and the multicast hash enab le bits in the network configuration register enable the reception of hash matched frames. the destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. the hash function is an exclusive or of every sixth bit of the destination address.
613 32003e?avr32?05/06 at32ap7000 hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is , the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. if the hash index points to a bit that is set in the hash register, then the frame is matched accord- ing to whether the frame is multicast or unicast. a multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. a unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. to receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 31.4.8 external address matching the external address signal (eam) is enabled by bit 9 in the network configuration register. when enabled, the filter block sends the store frame and the external address match status sig- nal to the dma block if the external address match signal is asserted (from a source external to the macb) and the destination address has been received and the frame has not completed. for the dma block to be able to copy the frame to memory, the external address signal must be asserted before four words have been loaded into the receive fifo. 31.4.9 copy all frames (or promiscuous mode) if the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. for example, frames that are too long, too short, or have fcs errors or rx_er asserted during reception are discarded and all others are received. frames with fcs errors are copied to memory if bit 19 in the network configuration register is set. 31.4.10 type id checking the contents of the type_id register are compared against the length/type id of received frames (i.e., bytes 13 and 14). bit 22 in the receive buffer descriptor status is set if there is a match. the reset state of this register is zero which is unlikely to match the length/type id of any valid ether- net frame. note: a type id match does not affect whether a frame is copied to memory.
614 32003e?avr32?05/06 at32ap7000 31.4.11 vlan support an ethernet encoded 802.1q vlan tag looks like this: the vlan tag is inserted at the 13 th byte of the frame, adding an extra four bytes to the frame. if the vid (vlan identifier) is null (0x000), this indicates a priority-tagged frame. the mac can support frame lengths up to 1536 bytes, 18 byte s more than the original ethernet maximum frame length of 1518 bytes. this is achieved by setting bit 8 in the network configuration register. the following bits in the receive buffer descrip tor status word give information about vlan tagged frames: ? bit 21 set if receive frame is vlan tagged (i.e. type id of 0x8100) ? bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null vid). (if bit 20 is set bit 21 is set also.) ? bit 19, 18 and 17 set to priority if bit 21 is set ? bit 16 set to cfi if bit 21 is set 31.4.12 phy maintenance the register man enables the macb to communi cate with a phy by means of the mdio inter- face. it is used during auto-negotiation to ensure that the macb and the phy are configured for the same speed and duplex configuration. the phy maintenance register is implemented as a shift register. writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 mck cycles later when bit ten is set to zero, and bit eleven is set to one in the net- work configuration register). an interrupt is generated as this bit is set. during this time, the msb of the register is output on the mdio pin and the lsb updated from the mdio pin with each mdc cycle. this causes transmission of a phy management frame on mdio. reading during the shift operation returns the current contents of the shift register. at the end of management operation, the bits have shifted back to their original locations. for a read opera- tion, the data bits are updated with data read from the phy. it is important to write the correct values to the register to ensure a valid phy management frame is produced. the mdio interface can read ieee 802.3 clause 45 phys as well as clause 22 phys. to read clause 45 phys, bits[31:28] should be written as 0x0011. for a description of mdc generation, see the network configuration register in the ?network control register? on page 621 . 31.4.13 media independent interface the ethernet mac is capable of interfacing to both rmii and mii interfaces. the rmii bit in the usrio register controls the interface that is sele cted. when this bit is set, the rmii interface is selected, else the mii interface is selected. table 31-4. 802.1q vlan tag tpid (tag protocol identifier) 16 bi ts tci (tag control information) 16 bits 0x8100 first 3 bits priority, then cfi bit, last 12 bits vid
615 32003e?avr32?05/06 at32ap7000 the mii and rmii interface are capable of both 10mb/s and 100mb/s data rates as described in the ieee 802.3u standard. the signals used by the mii and rmii interfaces are described in table 31-5 . the intent of the rmii is to provide a reduced pin count alternative to the ieee 802.3u mii. it uses 2 bits for transmit (etx0 and etx1) and tw o bits for receive (erx0 and erx1). there is a transmit enable (etxen), a receive error (e rxer), a carrier sense (ecrs_dv), and a 50 mhz reference clock (etxck_erefck) for 100mb/s data rate. 31.4.13.1 rmii transmit and receive operation the same signals are used internally for both the rmii and the mii operations. the rmii maps these signals in a more pin-efficient manner. the transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. the carrier sense and data valid signals are combined into the ecrsdv signal. this signal contains information on carrier sense, fifo status, and validity of t he data. transmit error bit (etxer) and collision detect (ecol) are not used in rmii mode. table 31-5. pin configuration pin name mii rmii etxck_erefck etxck: transmit clock erefck: reference clock ecrs ecrs: carrier sense ecol ecol: collision detect erxdv erxdv: data valid ecrsdv: carrier sense/data valid erx0 - erx3 erx0 - erx3: 4-bit receiv e data erx0 - erx1: 2-bit receive data erxer erxer: receive error erxer: receive error erxck erxck: receive clock etxen etxen: transmit enable etxen: transmit enable etx0-etx3 etx0 - etx3: 4-bit transmit data etx0 - etx1: 2-bit transmit data etxer etxer: transmit error
616 32003e?avr32?05/06 at32ap7000 31.5 programming interface 31.5.1 initialization 31.5.1.1 configuration initialization of the macb configuration (e.g. frequency ratios) must be done while the transmit and receive circuits are disabled. see the description of the network control register and network configuration register later in this document. 31.5.1.2 receive buffer list receive data is written to areas of data (i.e., buffers) in system memory. these buffers are listed in another data structure that also resides in main memory. this data structure (receive buffer queue) is a sequence of descriptor entries as defined in ?receive buffer descriptor entry? on page 605 . it points to this data structure. figure 31-2. receive buffer list to create the list of buffers: 1. allocate a number ( n ) of buffers of 128 bytes in system memory. 2. allocate an area 2 n words for the receive buffer descriptor entry in system memory and create n entries in this list. mark all entries in th is list as owned by macb, i.e., bit 0 of word 0 set to 0. 3. if less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. write address of receive buffer descriptor entry to macb register receive_buffer queue pointer. 5. the receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. receive buffer queue pointer (mac register) receive buffer 0 receive buffer 1 receive buffer n receive buffer descriptor list (in memory) (in memory)
617 32003e?avr32?05/06 at32ap7000 31.5.1.3 transmit buffer list transmit data is read from the system memory these buffers are listed in another data structure that also resides in main memory. this data st ructure (transmit buffer queue) is a sequence of descriptor entries (as defined in table 31-2 on page 608 ) that points to this data structure. to create this list of buffers: 1. allocate a number ( n ) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. up to 128 buffers per frame are allowed. 2. allocate an area 2 n words for the transmit buffer descriptor entry in system memory and create n entries in this list. mark all entrie s in this list as owned by macb, i.e. bit 31 of word 1 set to 0. 3. if fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit ? bit 30 in word 1 set to 1. 4. write address of transmit buffer descriptor entry to macb register transmit_buffer queue pointer. 5. the transmit circuits can then be enabled by writing to the network control register. 31.5.1.4 address matching the macb register-pair hash address and the four specific address register-pairs must be writ- ten with the required values. each register-pair comprises a bottom register and top register, with the bottom register being written first. the addre ss matching is disabled for a particular reg- ister-pair after the bottom-register has been written and re-enabled when the top register is written. see section ?31.4.5? on page 611. for details of address matching. each register-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. 31.5.1.5 interrupts there are 14 interrupt conditions that are detected within the macb. these are ored to make a single interrupt. this interrupt is passed to the interrupt controller. on receipt of the interrupt sig- nal, the cpu enters the interrupt handler. to ascertain which interrupt has been generated, read the interrupt status register. note that this register clears itself when read. at reset, all interrupts are disabled. to enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. to disable an interrupt, write to in terrupt disable register with the pertinent interrupt bit set to 1. to check whether an interrupt is enabled or disabled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 31.5.1.6 transmitting frames to set up a frame for transmission: 1. enable transmit in the network control register. 2. allocate an area of system memory for transmit data. this does not have to be contigu- ous, varying byte lengths can be used as long as they conclude on byte borders. 3. set-up the transmit buffer list. 4. set the network control register to enable transmission and enable interrupts. 5. write data for transmission into these buffers. 6. write the address to transmit buffer descriptor queue pointer. 7. write control and length to word one of the transmit buffer descriptor entry. 8. write to the transmit start bit in the network control register.
618 32003e?avr32?05/06 at32ap7000 31.5.1.7 receiving frames when a frame is received and the receive circuits are enabled, the macb checks the address and, in the following cases, the frame is written to system memory: ? if it matches one of the four specific address registers. ? if it matches the hash address function. ? if it is a broadcast address (0xf fffffffffff) and broadcasts are allowed. ? if the macb is configured to copy all frames. ? if the eam is asserted before four words have been loaded into the receive fifo. the register receive buffer queue pointer points to the next entry (see table 31-1 on page 605 ) and the macb uses this as the address in system memory to write the frame to. once the frame has been completely and successfully received an d written to system memory, the macb then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. once this is complete an interrupt re ceive complete is set. software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. if the macb is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. if there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not avail able is set. if the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
619 32003e?avr32?05/06 at32ap7000 31.6 ethernet mac 10/100 (m acb) user interface table 31-6. ethernet mac 10/100 (macb) register mapping offset register name access reset value 0x00 network control register ncr read/write 0 0x04 network configuration register ncfg read/write 0x800 0x08 network status register nsr read-only - 0x0c reserved 0x10 reserved 0x14 transmit status regi ster tsr read/write 0x0000_0000 0x18 receive buffer queue pointer register rbqp read/write 0x0000_0000 0x1c transmit buffer queue pointer register tbqp read/write 0x0000_0000 0x20 receive status regist er rsr read/write 0x0000_0000 0x24 interrupt status regi ster isr read/write 0x0000_0000 0x28 interrupt enable register ier write-only - 0x2c interrupt disable register idr write-only - 0x30 interrupt mask register imr read-only 0x0000_3fff 0x34 phy maintenance register man read/write 0x0000_0000 0x38 pause time register ptr read/write 0x0000_0000 0x3c pause frames received re gister pfr read/write 0x0000_0000 0x40 frames transmitted ok r egister fto read/write 0x0000_0000 0x44 single collision frames register scf read/write 0x0000_0000 0x48 multiple collision frames register mcf read/write 0x0000_0000 0x4c frames received ok register fro read/write 0x0000_0000 0x50 frame check sequence errors register fcse read/write 0x0000_0000 0x54 alignment errors regi ster ale read/write 0x0000_0000 0x58 deferred transmission frames register dtf read/write 0x0000_0000 0x5c late collisions register lcol read/write 0x0000_0000 0x60 excessive collisions register ecol read/write 0x0000_0000 0x64 transmit underrun errors register tund read/write 0x0000_0000 0x68 carrier sense errors register cse read/write 0x0000_0000 0x6c receive resource errors register rre read/write 0x0000_0000 0x70 receive overrun errors register rov read/write 0x0000_0000 0x74 receive symbol errors register rse read/write 0x0000_0000 0x78 excessive length errors register ele read/write 0x0000_0000 0x7c receive jabbers register rja read/write 0x0000_0000 0x80 undersize frames regi ster usf read/write 0x0000_0000 0x84 sqe test errors register ste read/write 0x0000_0000 0x88 received length field mismatch register rle read/write 0x0000_0000
620 32003e?avr32?05/06 at32ap7000 0x8c transmitted pause frames register tpf read/write 0x0000_0000 0x90 hash register bottom [31:0] register hrb read/write 0x0000_0000 0x94 hash register top [63:32] register hrt read/write 0x0000_0000 0x98 specific address 1 bottom register sa1b read/write 0x0000_0000 0x9c specific address 1 top r egister sa1t read/write 0x0000_0000 0xa0 specific address 2 bottom register sa2b read/write 0x0000_0000 0xa4 specific address 2 top register sa2t read/write 0x0000_0000 0xa8 specific address 3 bottom register sa3b read/write 0x0000_0000 0xac specific address 3 top register sa3t read/write 0x0000_0000 0xb0 specific address 4 bottom register sa4b read/write 0x0000_0000 0xb4 specific address 4 top r egister sa4t read/write 0x0000_0000 0xb8 type id checking register tid read/write 0x0000_0000 0xbc transmit pause quantum register tpq read/write 0x0000_ffff 0xc0 user input/output register usrio read/write 0x0000_0000 0xc4 wake on lan register wol read/write 0x0000_0000 0xc8 - 0xfc reserved ? ? ? table 31-6. ethernet mac 10/100 (macb) register mapping (continued) offset register name access reset value
621 32003e?avr32?05/06 at32ap7000 31.6.1 network control register register name: ncr access type: read/write ? lb: loopback asserts the loopback signal to the phy. ? re: receive enable when set, enables the macb to receive data. when reset, frame reception stops immediately and the receive fifo is cleared. the receive queue pointer register is unaffected. ? te: transmit enable when set, enables the ethernet transmitter to send data. when reset, transmission stops immediately, the transmit fifo and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descrip- tor list. ? mpe: management port enable set to one to enable the management port. when zero, forces mdio to high impedance state and mdc low. ? clrstat: clear statistics registers this bit is write only. writing a one clears the statistics registers. ? incstat: increment statistics registers this bit is write only. writing a one increments all the statistics registers by one for test purposes. ? westat: write enable for statistics registers setting this bit to one makes the statistics regi sters writable for functional test purposes. ? bp: back pressure if set in half duplex mode, forces collisions on all received frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? tzq tpf thalt tstart bp 76543210 westat incstat clrstat mpe te re ? lb
622 32003e?avr32?05/06 at32ap7000 ? tstart: start transmission writing one to this bit starts transmission. ? thalt: transmit halt writing one to this bit halts transmission as soon as any ongoing frame transmission ends. ? tpf: transmit pause frame writing one to this bit transmits a pause frame with the pause quantum from the transmit pause quantum register at the next available transmitter idle time. ? tzq: transmit zero quantum pause frame writing a one to this bit transmits a pause frame with zero pause quantum at the next available transmitter idle time.
623 32003e?avr32?05/06 at32ap7000 31.6.2 network configuration register register name: ncfgr access type: read/write ? spd: speed set to 1 to indicate 100 mbit/s operation, 0 for 10 mbit/s. the value of this pin is reflected on the speed pin. ? fd: full duplex if set to 1, the transmit block ignores the state of collision and carr ier sense and allows receiv e while transmitting. also co n- trols the half_duplex pin. ? caf: copy all frames when set to 1, all valid frames are received. ? jframe: jumbo frames set to one to enable jumbo frames of up to 10240 bytes to be accepted. ? nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. ? mti: multicast hash enable when set, multicast frames are received when the 6-bit hash functi on of the destination address points to a bit that is set in the hash register. ? uni: unicast hash enable when set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. ? big: receive 1536 bytes frames setting this bit means the macb receives frames up to 1536 bytes in length. normally, the macb would reject any frame above 1518 bytes. ? eae: external address match enable when set, the eam pin can be used to copy frames to memory. ? clk: mdc clock divider 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????irxfcsefrhddrfcsrlce 15 14 13 12 11 10 9 8 rbof pae rty clk eae big 76543210 uni mti nbc caf jframe ? fd spd
624 32003e?avr32?05/06 at32ap7000 set according to system clock speed. this determines by what number system clock is divided to generate mdc. for conformance with 802.3, mdc must not exceed 2.5mhz (mdc is only active during mdio read and write operations). ? rty: retry test must be set to zero for normal operation. if set to one, the back off between collisions is always one slot time. setting this bit to one helps testing the too many retries condition. also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. ?pae: pause enable when set, transmission pauses when a valid pause frame is received. ? rbof: receive buffer offset indicates the number of bytes by which the received data is offset from the start of the first receive buffer. ? rlce: receive length field checking enable when set, frames with measured lengths shorter than their length fields are di scarded. frames containing a type id in bytes 13 and 14 ? length/type id = 0600 ? are not be counted as length errors. ? drfcs: discard receive fcs when set, the fcs field of received frames are not be copied to memory. ? efrhd: enable frames to be received in half-duplex mode wh ile transmitting. ? irxfcs: ignore rx fcs when set, frames with fcs/crc errors are not rejected and no fcs error statistics are counted. for normal operation, this bit must be set to 0. clk mdc 00 mck divided by 8 (mck up to 20 mhz) 01 mck divided by 16 (mck up to 40 mhz) 10 mck divided by 32 (mck up to 80 mhz) 11 mck divided by 64 (mck up to 160 mhz) rbof offset 00 no offset from start of receive buffer 01 one-byte offset from start of receive buffer 10 two-byte offset from start of receive buffer 11 three-byte offset from start of receive buffer
625 32003e?avr32?05/06 at32ap7000 31.6.3 network status register register name: nsr access type: read-only ?link returns status of link pin. ?mdio returns status of the mdio_in pin. use the phy main tenance register for reading managed frames rather than this bit. ?idle 0 = the phy management logic is idle (i.e., has completed). 1 = the phy logic is running. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????idlemdiolink
626 32003e?avr32?05/06 at32ap7000 31.6.4 transmit status register register name: tsr access type: read/write this register, when read, provides details of the status of a tr ansmit. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? ubr: used bit read set when a transmit buffer descriptor is read with its used bit set. cleared by writing a one to this bit. ? col: collision occurred set by the assertion of collision. cle ared by writing a one to this bit. ? rle: retry limit exceeded cleared by writing a one to this bit. ? tgo: transmit go if high transmit is active. ? bex: buffers exhausted mid frame if the buffers run out during transmission of a frame, then transmission stops, fcs shall be bad and tx_er asserted. cleared by writing a one to this bit. ? comp: transmit complete set when a frame has been transmitted. cleared by writing a one to this bit. ? und: transmit underrun set when transmit dma was not able to read data from memory, either because the bus was not granted in time, because a not ok hresp(bus error) was returned or because a used bit was read midway through frame transmission. if this occurs, the transmitter forces bad crc. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bex tgo rle col ubr
627 32003e?avr32?05/06 at32ap7000 31.6.5 receive buffer queue pointer register register name: rbqp access type: read/write this register points to the entry in the receive buffer queue (des criptor list) currently being used. it is written with the st art location of the receive buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origina l values after either 1024 buffers or when the wrap bit of the entry is set. reading this register returns the location of the descriptor cu rrently being accessed. this value increments as buffers are used. software should not use this register for determining where to remove received frames from the queue as it con- stantly changes as new frames are received. software should instead work its way through the buffer descriptor queue checking the used bits. receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k boundary, in violation of the system bus specification. ? addr: receive buffer queue pointer address written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
628 32003e?avr32?05/06 at32ap7000 31.6.6 transmit buffer queue pointer register register name: tbqp access type: read/write this register points to the entry in the transmit buffer queue (descriptor list) currently being used. it is written with the s tart location of the transmit buffer descriptor list. the lower order bits increment as buffers are used up and wrap to their origin al values after either 1024 buffers or when the wrap bit of the entry is set. this register can only be written when bit 3 in the transmit status register is low. as transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k boundary, in violation of the system bus specification. ? addr: transmit buffer queue pointer address written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmit - ted or about to be transmitted. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
629 32003e?avr32?05/06 at32ap7000 31.6.7 receive status register register name: rsr access type: read/write this register, when read, provides details of the status of a re ceive. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? bna: buffer not available an attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. the dma rereads the pointer each time a new frame starts un til a valid pointer is found. this bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. cleared by writing a one to this bit. ? rec: frame received one or more frames have been received and placed in memory. cleared by writing a one to this bit. ? ovr: receive overrun the dma block was unable to store the receive frame to me mory, either because the bus was not granted in time or because a not ok hresp(bus error) was returned. the buffer is recovered if this happens. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????ovrrecbna
630 32003e?avr32?05/06 at32ap7000 31.6.8 interrupt status register register name: isr access type: read/write ? mfd: management frame done the phy maintenance register has completed its operation. cleared on read. ? rcomp: rece ive complete a frame has been stored in memory. cleared on read. ? rxubr: receive used bit read set when a receive buffer descriptor is read with its used bit set. cleared on read. ? txubr: transmit used bit read set when a transmit buffer descriptor is read with its used bit set. cleared on read. ? tund: ethernet transmit buffer underrun the transmit dma did not fetch frame data in time for it to be transmitted or hresp returned not ok. also set if a used bit is read mid-frame or when a new transmit queue pointer is written. cleared on read. ? rle: retry limit exceeded cleared on read. ? txerr: transmit error transmit buffers exhausted in mid-frame - transmit error. cleared on read. ? tcomp: transmit complete set when a frame has been transmitted. cleared on read. ? link: link change set when the external link signal changes. cleared on read. ? rovr: receive overrun set when the receive overrun status bit gets set. cleared on read. ? hresp: hresp not ok set when the dma block sees a bus error . cleared on read. ? pfr: pause frame received indicates a valid pause has been received. cleared on a read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ?link ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
631 32003e?avr32?05/06 at32ap7000 ? ptz: pause time zero set when the pause time register, 0x38 decrements to zero. cleared on a read.
632 32003e?avr32?05/06 at32ap7000 31.6.9 interrupt enable register register name: ier access type: read/write ? mfd: management frame sent enable management done interrupt. ? rcomp: rece ive complete enable receive co mplete interrupt. ? rxubr: receive used bit read enable receive used bit read interrupt. ? txubr: transmit used bit read enable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun enable transmit underrun interrupt. ? rle: retry limit exceeded enable retry limit exceeded interrupt. ? txerr enable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete enable transmit co mplete interrupt. ? link: link change enable link cha nge interrupt. ? rovr: receive overrun enable receive overrun interrupt. ? hresp: hresp not ok enable hresp not ok interrupt. ? pfr: pause frame received enable pause frame received interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr link ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
633 32003e?avr32?05/06 at32ap7000 ? ptz: pause time zero enable pause time zero interrupt.
634 32003e?avr32?05/06 at32ap7000 31.6.10 interrupt disable register register name: idr access type: read/write ? mfd: management frame sent disable management done interrupt. ? rcomp: rece ive complete disable receive comp lete interrupt. ? rxubr: receive used bit read disable receive used bit read interrupt. ? txubr: transmit used bit read disable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun disable transmit underrun interrupt. ? rle: retry limit exceeded disable retry limit exceeded interrupt. ? txerr disable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete disable transmit complete interrupt. ? link: link change disable link change interrupt. ? rovr: receive overrun disable receive overrun interrupt. ? hresp: hresp not ok disable hresp not ok interrupt. ? pfr: pause frame received disable pause frame received interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr link ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
635 32003e?avr32?05/06 at32ap7000 ? ptz: pause time zero disable pause time zero interrupt.
636 32003e?avr32?05/06 at32ap7000 31.6.11 interrupt mask register register name: imr access type: read/write ? mfd: management frame sent management done interrupt masked. ? rcomp: rece ive complete receive complete interrupt masked. ? rxubr: receive used bit read receive used bit read interrupt masked. ? txubr: transmit used bit read transmit used bit read interrupt masked. ? tund: ethernet transmit buffer underrun transmit underrun interrupt masked. ? rle: retry limit exceeded retry limit exceeded interrupt masked. ? txerr transmit buffers exhausted in mid-frame interrupt masked. ? tcomp: transmit complete transmit complete interrupt masked. ? link: link change link change interrupt masked. ? rovr: receive overrun receive overrun interrupt masked. ? hresp: hresp not ok hresp not ok interrupt masked. ? pfr: pause frame received pause frame received interrupt masked. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr link ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
637 32003e?avr32?05/06 at32ap7000 ? ptz: pause time zero pause time zero interrupt masked.
638 32003e?avr32?05/06 at32ap7000 31.6.12 phy maintenance register register name: man access type: read/write ?data for a write operation this is written with the data to be written to the phy. after a read operation this contains the data read from the phy. ?code: must be written to 10. reads as written. ? rega: register address specifies the register in the phy to access. ? phya: phy address ? rw: read/write 10 is read; 01 is write. any other va lue is an invalid ph y management frame ? sof: start of frame must be written 01 for a valid frame. 31 30 29 28 27 26 25 24 sof rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
639 32003e?avr32?05/06 at32ap7000 31.6.13 pause time register register name: ptr access type: read/write ? ptime: pause time stores the current value of the pause time register which is decremented every 512 bit times. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ptime 76543210 ptime
640 32003e?avr32?05/06 at32ap7000 31.6.14 hash register bottom register name: hrb access type: read/write ? addr: bits 31:0 of the hash address register. see ?hash addressing? on page 612 . 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
641 32003e?avr32?05/06 at32ap7000 31.6.15 hash register top register name: hrt access type: read/write ? addr: bits 63:32 of the hash address register. see ?hash addressing? on page 612 . 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
642 32003e?avr32?05/06 at32ap7000 31.6.16 specific address 1 bottom register register name: sa1b access type: read/write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
643 32003e?avr32?05/06 at32ap7000 31.6.17 specific address 1 top register register name: sa1t access type: read/write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
644 32003e?avr32?05/06 at32ap7000 31.6.18 specific address 2 bottom register register name: sa2b access type: read/write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
645 32003e?avr32?05/06 at32ap7000 31.6.19 specific address 2 top register register name: sa2t access type: read/write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
646 32003e?avr32?05/06 at32ap7000 31.6.20 specific address 3 bottom register register name: sa3b access type: read/write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
647 32003e?avr32?05/06 at32ap7000 31.6.21 specific address 3 top register register name: sa3t access type: read/write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
648 32003e?avr32?05/06 at32ap7000 31.6.22 specific address 4 bottom register register name: sa4b access type: read/write ? addr least significant bits of the destination address. bit zero indicates whether the address is multicast or unicast and corre- sponds to the least significant bit of the first byte received. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
649 32003e?avr32?05/06 at32ap7000 31.6.23 specific address 4 top register register name: sa4t access type: read/write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
650 32003e?avr32?05/06 at32ap7000 31.6.24 type id checking register register name: tid access type: read/write ? tid: type id checking for use in comparisons with rece ived frames typeid/length field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tid 76543210 tid
651 32003e?avr32?05/06 at32ap7000 31.6.25 transmit pause quantum register register name: tpq access type: read/write ? tpq: transmit pause quantum used in hardware generation of transmitted pause frames as value for pause quantum. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tpq 76543210 tpq
652 32003e?avr32?05/06 at32ap7000 31.6.26 user input/output register register name: usrio access type: read/write ?rmii when set, this bit enables the rmii operation mode. when reset, it selects the mii mode. ?eam when set, this bit causes a frame to be copied to memory, if this feature is enabled by the eae bit in ncfgr. otherwise, no frame is copied. ?tx_pause toggling this bit causes a pause frame to be transmitted. ? tx_pause_zero selects either zero or the transmit quantum register as the transmitted pause frame quantum. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???? tx_pause_ zero tx_pause eam rmii
653 32003e?avr32?05/06 at32ap7000 31.6.27 wake-on-lan register register name: wol access type: read/write ? ip: arp request ip address written to define the least significant 16 bits of the target ip address that is matched to generate a wake-on-lan event. a value of zero does not generate an event, even if this is matched by the received frame. ? mag: magic packet event enable when set, magic packet events causes the wol output to be asserted. ? arp: arp request event enable when set, arp request events causes the wol output to be asserted. ? sa1: specific address register 1 event enable when set, specific address 1 events causes the wol output to be asserted. ? mti: multicast hash event enable when set, multicast ha sh events causes the wol output to be asserted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????mtisa1arpmag 15 14 13 12 11 10 9 8 ip 76543210 ip
654 32003e?avr32?05/06 at32ap7000 31.6.28 macb statistic registers these registers reset to zero on a read and stick at all ones when they count to their maximum value. they should be read frequently enough to prevent loss of data. the receive statis tics registers are only incremented when the receive enable bit is set in the network control register. to write to these registers, bit 7, westat, in the network control register, ncr, must be set. the statistics register block contains the following registers. 31.6.28.1 pause frames received register register name: pfr access type: read/write ? frok: pause frames received ok a 16-bit register counting the number of good pause frames received. a good frame has a length of 64 to 1518 (1536 if bit 8, big, in network configuration regist er, ncfgr, is set) and has no fcs, alignment or receive symbol errors. 31.6.28.2 frames transmitted ok register register name: fto access type: read/write ? ftok: frames transmitted ok a 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ftok 15 14 13 12 11 10 9 8 ftok 76543210 ftok
655 32003e?avr32?05/06 at32ap7000 31.6.28.3 single collis ion frames register register name: scf access type: read/write ? scf: single collision frames a 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 31.6.28.4 multicollision frames register register name: mcf access type: read/write ? mcf: multicollision frames a 16-bit register counting th e number of frames experiencing between two an d fifteen collisions prio r to being successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 scf 76543210 scf 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mcf 76543210 mcf
656 32003e?avr32?05/06 at32ap7000 31.6.28.5 frames received ok register register name: fro access type: read/write ? frok: frames received ok a 24-bit register counting the number of good frames receiv ed, i.e., address recognized and successfully copied to mem- ory. a good frame is of length 64 to 1518 bytes (1536 if bit 8, big, in network configuration register, ncfgr, is set) and has no fcs, alignment or receive symbol errors. 31.6.28.6 frames check sequence errors register register name: fcse access type: read/write ? fcse: frame check sequence errors an 8-bit register counting frames that are an integral number of bytes, have bad crc and are between 64 and 1518 bytes in length (1536 if bit 8, big, in network configuration register, ncfgr, is set). this register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 frok 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 fcse
657 32003e?avr32?05/06 at32ap7000 31.6.28.7 alignment errors register register name: ale access type: read/write ? ale: alignment errors an 8-bit register counting frames that are not an integral number of bytes long and have bad crc when their length is trun- cated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8, big, in network configuration register, ncfgr, is set). this register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. 31.6.28.8 deferred transmission frames register register name: dtf access type: read/write ? dtf: deferred transmission frames a 16-bit register counting the number of frames experiencing defer ral due to carrier sense being active on their first attempt at transmission. frames invo lved in any collision are not c ounted nor are fr ames that experienced a transmit underrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ale 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dtf 76543210 dtf
658 32003e?avr32?05/06 at32ap7000 31.6.28.9 late collisions register register name: lcol access type: read/write ? lcol: late collisions an 8-bit register counting the number of frames that experience a collis ion after the slot time (512 bits) has expired. a late collision is counted twice; i.e., both as a collision and a late collision. 31.6.28.10 excessive collisions register register name: excol access type: read/write ? excol: excessive collisions an 8-bit register counting the number of frames that faile d to be transmitted because t hey experienced 16 collisions. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 lcol 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 excol
659 32003e?avr32?05/06 at32ap7000 31.6.28.11 transmit underrun errors register register name: tund access type: read/write ? tund: transmit underruns an 8-bit register counting the number of frames not transmitte d due to a transmit dma underrun. if this register is incre- mented, then no other statistics register is incremented. 31.6.28.12 carrier sense errors register register name: cse access type: read/write ? cse: carrier sense errors an 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after bein g asserted in a transmit frame without collis ion (no underrun). on ly incremented in half-duplex mode. the only effect of a carrier sense error is to increment this register. the behavior of the other statistics registers is unaffected by the detection of a carrier sense error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tund 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cse
660 32003e?avr32?05/06 at32ap7000 31.6.28.13 receive reso urce errors register register name: rre access type: read/write ? rre: receive resource errors a 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 31.6.28.14 receive overrun errors register register name: rovr access type: read/write ? rovr: receive overrun an 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive dma overrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rre 76543210 rre 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rovr
661 32003e?avr32?05/06 at32ap7000 31.6.28.15 receive symbol errors register register name: rse access type: read/write ? rse: receive symbol errors an 8-bit register counting the number of frames that had rx_er asserted during reception. receive symbol errors are also counted as an fcs or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8, big, in network configuration register, ncfgr, is set). if the frame is larger, it is recorded as a jabber error. 31.6.28.16 excessive length errors register register name: ele access type: read/write ? exl: excessive length errors an 8-bit register counting the number of frames received exce eding 1518 bytes (1536 if bit 8, big, in network configuration register, ncfgr, is set) in length but do not have either a crc error, an alignment error nor a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rse 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 exl
662 32003e?avr32?05/06 at32ap7000 31.6.28.17 receive jabbers register register name: rja access type: read/write ? rjb: receive jabbers an 8-bit register counting the number of frames received exce eding 1518 bytes (1536 if bit 8, big, in network configuration register, ncfgr, is set) in length and have either a crc error, an alignment error or a receive symbol error. 31.6.28.18 undersize frames register register name: usf access type: read/write ? usf: undersize frames an 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a crc error, an alignment error or a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rjb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 usf
663 32003e?avr32?05/06 at32ap7000 31.6.28.19 sqe test errors register register name: ste access type: read/write ? sqer: sqe test errors an 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 31.6.28.20 received length field mismatch register register name: rle access type: read/write ? rlfm: receive length field mismatch an 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. checking is enabled through bit 16 of the netw ork configuration register. frames containing a type id in bytes 13 and 14 (i.e., length/type id 0x0600) are not counted as length field errors, neither are excessive length frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sqer 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rlfm
664 32003e?avr32?05/06 at32ap7000 31.6.28.21 transmitted pause frames register register name: tpf access type: read/write ? tpf: transmitted pause frames a 16-bit register counting the number of pause frames transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tpf 76543210 tpf
665 32003e?avr32?05/06 at32ap7000 32. usb device - high speed (480 mbits/s) rev: 6227a 32.1 features ? usb v2.0 high speed compli ant, 480 mbits per second ? utmi compliant ? 7 endpoints ? embedded dual-port ram for endpoints ? suspend/resume logic (command of utmi) ? up to three memory banks for endpoints (not for control endpoint) ? 4 kbytes of dpram ? compatible with embedded arm9tdmi ? processor 32.2 description the usb high speed device (udphs) is compliant with the universal seri al bus (usb), rev 2.0 high speed device specification. each endpoint can be configured in one of several usb transfer types. it can be associated with one, two or three banks of a dual-port ram used to store the current data payload. if two or three banks are used, one dpr bank is read or written by the processor, while the other is read or written by the usb device peripheral. this f eature is mandatory for isochronous endpoints. the default size of the dpram is 4 kb. suspend and resume are automatically detected by the udphs device, which notifies the pro- cessor by raising an interrupt. table 32-1. udphs endpoint description endpoint # mnemonic nb bank dma high band width max. endpoint size endpoint type 0 ep0 1 n n 64 control 1 ep1 2 y y 512 ctrl/bulk/iso/interrupt 2 ep2 2 y y 512 ctrl/bulk/iso/interrupt 3 ep3 3 y n 64 ctrl/bulk/interrupt 4 ep4 3 y n 64 ctrl/bulk/interrupt 5 ep5 3 y y 1024 ctrl/bulk/interrupt 6 ep6 3 y y 1024 ctrl/bulk/interrupt
666 32003e?avr32?05/06 at32ap7000 32.3 block diagram figure 32-1. block diagram: 32 bits system clock domain usb clock domain ctrl status rd/wr/ready apb interface usb2.0 core ept alloc ahb1 dma ahb0 local ahb slave interface master ahb multiplexer slave dpram utmi 16/8 bits apb bus ahb bus ahb bus
667 32003e?avr32?05/06 at32ap7000 32.4 typical connection figure 32-2. board schematic note: 1. values are guidelines only. actual values are tbd. table 32-2. components typical values symbol value (1) unit r1 6.8 1% k r2 39 1% c1 10 pf usb connector mini ab nc / d- / d+ / gnd hsdp hsdm fsdp fsdm bias r2 r2 r1 c1 1234
668 32003e?avr32?05/06 at32ap7000 32.5 usb v2.0 high speed device introduction the usb v2.0 high speed device provides communication services to/from host when attached. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with a usb device through a set of commu- nication flows. 32.5.1 usb v2.0 high speed transfer types a communication flow is carried over one of f our transfer types defined by the usb device. a device provides several logical communication pipes with the host. to each logical pipe is associated an endpoint. transfer through a pipe belongs to one of the four transfer types: ? control transfers: used to configure a device at attach time and can be used for other device- specific purposes, including control of other pipes on the device. ? bulk data transfers: generated or consumed in relatively large burst quantities and have wide dynamic latitude in transmission constraints. ? interrupt data transfers: used for timely but reliable delivery of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics. ? isochronous data transfers: occupy a prenegotiated amount of usb bandwidth with a prenegotiated delivery latency. (also called streaming real time transfers.) as indicated below, transfers are sequential events carried out on the usb bus. endpoints must be configured according to the transfer type they handle. table 32-3. usb communication flow transfer direction bandwidth endpoin t size error detection retrying control bidirectional not guaranteed 8,16,32,64 yes automatic isochronous unidirectional guaranteed 8-1024 yes no interrupt unidirectional not guaranteed 8-1024 yes yes bulk unidirectional not guaranteed 8-512 yes yes
669 32003e?avr32?05/06 at32ap7000 32.5.2 usb transfer event definitions a transfer is composed of one or several transactions; notes: 1. control transfer must use endpoints with one bank and can be aborted using a stall handshake. 2. isochronous transfers must use endpoint s configured with two or three banks. an endpoint handles all transactions related to the type of transfer for which it has been configured. 32.5.3 usb v2.0 high speed bus transactions each transfer results in one or more transactions over the usb bus. there are five kinds of transactions flowing across the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 4. status in transaction 5. status out transaction table 32-4. usb transfer events control (bidirectional) control transfers (1) ? setup transaction > data in transactions > status out transaction ? setup transaction > data out tran sactions > status in transaction ? setup transaction > st atus in transaction in (device toward host) bulk in transfer ? data in transaction > data in transaction interrupt in transfer ? data in transaction > data in transaction isochronous in transfer (2) ? data in transaction > data in transaction out (host toward device) bulk out transfer ? data out transaction > data out transaction interrupt out transfer ? data out transaction > data out transaction isochronous out transfer (2) ? data out transaction > data out transaction
670 32003e?avr32?05/06 at32ap7000 figure 32-3. control read and write sequences a status in or out transaction is identical to a data in or out transaction. 32.5.4 endpoint configuration the endpoint 0 is always a control endpoint, it must be programmed and active in order to be enabled when the end of reset interrupt occurs. to configure the endpoints: ? fill the configuration register (udphs_eptcfg) with the endpoint size, direction (in or out), type (ctrl, bulk, it, iso) and the number of banks. ? fill the number of transactions (n b_trans) for isochronous endpoints. note: for control endpoints the direction has no effect. ? verify that the ept_mapd flag is set. this flag is set if the endpoint size and the number of banks are correct compared to the fifo maximum capacity and the maximum number of allowed banks. ? configure control flags of the endpoint and enable it in udphs_eptctlenbx according to ?udphs endpoint contro l register? on page 722 . control endpoints can generate interrupts and use only 1 bank. all endpoints (except endpoint 0) can be configur ed either as bulk, interrupt or isochronous. see table 32-1. udphs endpoint description . the maximum packet size they can accept corresponds to the maximum endpoint size. note: the endpoint size of 1024 is reserved for isochronous endpoints. the size of the dpram is 4 kb. the dpr is shared by all active endpoints. the memory size required by the active endpoints must not exceed the size of the dpram. control write setup tx data out tx data out tx data stage control read setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
671 32003e?avr32?05/06 at32ap7000 size_dpram = size _ept0 + nb_bank_ept1 x size_ept1 + nb_bank_ept2 x size_ept2 + nb_bank_ept3 x size_ept3 + nb_bank_ept4 x size_ept4 + nb_bank_ept5 x size_ept5 + nb_bank_ept6 x size_ept6 +... (refer to 32.6.17 udphs endpoint configuration register ) if a user tries to configure endpoints with a size the sum of which is greater than the dpram, then the ept_mapd is not set. the application has access to the physical block of dpr reserved for the endpoint through a 64 kb logical address space. the physical block of dpr allocated for the endpoint is remapped all along the 64 kb logical address space. the application can write a 64 kb buffer linearly. figure 32-4. logical address space for dpr access: configuration examples of udphs_eptctlx ( udphs endpoint control register ) for bulk in endpoint type follow below. 64 kb ep0 64 kb ep1 64 kb ep2 dpr logical address 8 to 64 b 8 to1024 b 8 to1024 b 8 to1024 b 64 kb ep3 ... 8 to 64 b 8 to 64 b 8 to 64 b ... ... x banks y banks z banks 8 to1024 b 8 to1024 b 8 to1024 b
672 32003e?avr32?05/06 at32ap7000 ?with dma ? auto_valid: automatically validate the packet and switch to the next bank. ? ept_enabl: enable endpoint. ? without dma: ? tx_bk_rdy: an interrupt is generated after each transmission. ? ept_enabl: enable endpoint. configuration examples of bulk out endpoint type follow below. ?with dma ? auto_valid: automatically validate the packet and switch to the next bank. ? ept_enabl: enable endpoint. ? without dma ? rx_bk_rdy: an interrupt is sent after a new packet has been stored in the endpoint fifo. ? ept_enabl: enable endpoint.
673 32003e?avr32?05/06 at32ap7000 32.5.5 dma usb packets of any length may be transferred when required by the udphs device. these transfers always feature sequential addressing. packet data ahb bursts may be locked on a dma buffer basis for drastic overall ahb bus band- width performance boost with pa ged memories. these clock-cycl e consuming memory row (or bank) changes will then likely not occur, or occu r only once instead of dozens times, during a single big usb packet dma transfer in case another ahb master addresses the memory. this means up to 128-word single-cycle unbroken ahb bursts for bulk endpoints and 256-word sin- gle-cycle unbroken bursts for isochronous endpo ints. this maximum burst length is then controlled by the lowest programmed usb endpoint size (ept_size bit in the udphs_eptcfgx register) and dma size (buff_length bit in the udphs_dmacontrolx register). the udphs device average throughput may be up to nearly 60 mbytes. its internal slave aver- age access latency decreases as bu rst length increases due to the 0 wait-state side effect of unchanged endpoi nts. if at least 0 wait-state word burst capability is also pr ovided by the exter- nal dma ahb bus slaves, eac h of both dma ahb busses need less than 50% bandwidth allocation for full udphs bandwidth usage at 30 mhz, and less than 25% at 60 mhz. the udphs dma channel transfer descriptor is described in ?udphs dma channel transfer descriptor? on page 733 figure 32-5. example of dma chained list: data buff 1 data buff 2 data buff 3 memory area transfer descriptor next descriptor address dma channel address dma channel control transfer descriptor next descriptor address dma channel address dma channel control transfer descriptor next descriptor address dma channel address dma channel control udphs registers (current transfer descriptor) udphs next descriptor dma channel address dma channel control null
674 32003e?avr32?05/06 at32ap7000 32.5.6 handling transactions with usb v2.0 device peripheral 32.5.6.1 setup transaction the setup packet is valid in the dpr while rx_s etup is set. once rx_setup is cleared by the application, the udphs accepts the next packets sent over the device endpoint. when a valid setup packet is accepted by the udphs: ? the udphs device automatically acknowledges the setup packet (sends an ack response) ? payload data is written in the endpoint ? sets the rx_setup interrupt ? the byte_count field in the udphs_eptstax register is updated an endpoint interrupt is generated while rx_ setup in the udphs_eptstax register is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must detect rx_setup polling udphs_eptstax or catching an interrupt, read the setup packet in the fifo, then clear the rx_setup bit in the udphs_eptclrsta register to acknowledge the setup stage. if stall_snt was set to 1, then this bit is automatically reset when a setup token is detected by the device. then, the device still accepts the setup stage. (see section 32.5.6.15 ?stall? on page 686 ). 32.5.6.2 nyet nyet is a high speed only handshake. it is retu rned by a high speed endpoint as part of the ping protocol. high speed devices must support an improved nak mechanism for bulk out and control end- points (except setup stage). this mechanism allows the device to tell the host whether it has sufficient endpoint space for the next out transfe r (see usb 2.0 spec 8.5.1 nak limiting via ping flow control). the nyet/ack response to a high speed bulk out transfer and the ping response are auto- matically handled by hardware in the udphs_ept ctlx register (except when the user wants to force a nak response by using the nyet_dis bit). if the endpoint responds instead to the out/data transaction with an nyet handshake, this means that the endpoint accepted the data but does not have room for another data payload. the host controller must return to using a ping token until the endpoint indicates it has space available.
675 32003e?avr32?05/06 at32ap7000 figure 32-6. nyet example with two endpoint banks 32.5.6.3 data in 32.5.6.4 bulk in or interrupt in data in packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) in transfer. data buffers are sent packet by packet under the control of the application or under the control of the dma channel. there are three ways for an application to transfer a buffer in several packets over the usb: ? packet by packet (see 32.5.6.5 below) ? 64 kb (see 32.5.6.5 below) ?dma (see 32.5.6.6 below) 32.5.6.5 bulk in or interrupt in: sending a packet under application control (device to host) the application can write one or several banks. a simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. algorithm description for each packet: ? the application waits for tx_pk_rdy flag to be cleared in the udphs_eptstax register before it can perform a write access to the dpr. ? the application writes one usb packet of data in the dpr through the 64 kb endpoint logical memory window. ? the application sets tx_pk_rdy flag in the udphs_eptsetstax register. the application is notified that it is possible to write a new packet to the dpr by the tx_pk_rdy interrupt. this interrupt can be enabled or masked by setting the tx_pk_rdy bit in the udphs_eptctlenb/udp hs_eptctldis register. algorithm description to fill several packets: using the previous algorithm, the application is interrupted for each packet. it is possible to reduce the application overhead by writing linearly several banks at the same time. the auto_valid bit in the udphs_eptctlx must be set by writing the auto_valid bit in the udphs_eptctlenbx register. the auto-valid-bank mechanism allows the transfer of data (in and out) without the interven- tion of the cpu. this means that bank validation (set tx_pk_rdy or clear the rx_bk_rdy bit) is done by hardware. t = 0 t = 125 s t = 250 s t = 375 s t = 500 s t = 625 s data 0 ack data 1 nyet ping ack data 0 nyet ping nack ping ack bank 1 bank 0 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 e f f e f e' f e f f e' f e f e: empty e': begin to empty f: full
676 32003e?avr32?05/06 at32ap7000 ? the application checks the busy_bank_sta field in the udphs_eptstax register. the application must wait that at least one bank is free. ? the application writes a number of bytes inferior to the number of free dpr banks for the endpoint. each time the application writes the last byte of a bank, the tx_pk_rdy signal is automatically set by the udphs. ? if the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the tx_pk_rdy bit in the udphs_eptsetstax register. the application is notified that all banks are free, so that it is possible to write another burst of packets by the busy_bank interrupt. this interrupt can be enabled or masked by setting the busy_bank flag in the udphs_eptctle nb and udphs_eptctldis registers. this algorithm must not be used for isochronous transfer. in this case, the ping-pong mechanism does not operate. a zero length packet can be sent by setting just the tx_pktrdy flag in the udphs_eptsetstax register. 32.5.6.6 bulk in or interrupt in: sending a buffer using dma (device to host) the udphs integrates a dma host controller. this dma controller can be used to transfer a buffer from the memory to the dpr or from the dpr to the processor memory under the udphs control. the dma can be used for all transfer types except control transfer. example dma configuration: 1. program udphs_dmaaddressx with the addre ss of the buffer that should be transfer. 2. enable the interrupt of the dma in udphs_ien 3. program udphs_ dmacontrolx: ? size of buffer to send: size of the buffer to be sent to the host. ? end_b_en: the endpoint can validate the packet (according to the values programmed in the auto_valid and shrt_pckt fields of udphs_eptctlx.) (see ?udphs endpoint control register? on page 722 and figure 32-11. autovalid with dma ) ? end_buffit: generate an interrupt when the buff_count in udphs_dmastatusx reaches 0. ? chann_enb: run and stop at end of buffer the auto-valid-bank mechanism allows the transfer of data (in & out) without the intervention of the cpu. this means that bank validation (s et tx_pk_rdy or clear the rx_bk_rdy bit) is done by hardware. a transfer descriptor can be used. instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to udphs_dmanxtdsc to be processed after setting the ldnxt_dsc field (load next descrip- tor now) in udphs_dmacontrolx register. the structure that defines this transfer descriptor must be aligned. each buffer to be transferred must be described by a dma transfer descriptor (see ?udphs dma channel transfer descriptor? on page 733 ). transfer descriptors are chained. before exe- cuting transfer of the buffer, the udphs may fetch a new transfer descriptor from the memory address pointed by the udphs_dmanxtdscx regi ster. once the transfer is complete, the transfer status is updated in the udphs_dmastatusx register.
677 32003e?avr32?05/06 at32ap7000 to chain a new transfer descriptor with the current dma transfer, the dma channel must be stopped. to do so, intdis_dma and tx_bk_rdy may be set in the udphs_eptctlenbx register. it is also possible for the application to wait for the completion of all transfers. in this case the ldnxt_dsc field in the last transfer descriptor udphs_dmacontrolx register must be set to 0 and chann_enb set to 1. then the application can chain a new transfer descriptor. the intdis_dma can be used to stop the current dma transfer if an enabled interrupt is trig- gered. this can be used to stop dma transfers in case of errors. the application can be notified at the end of any buffer transfer (enb_buffit bit in the udphs_dmacontrolx register). figure 32-7. data in transfer for endpoint with one bank usb bus packets fifo content tx_complt flag (udphs_eptstax) tx_pk_rdy flag (udphs_eptstax) prevous data in tx microcontroller loads data in fifo data is sent on usb bus interrupt pending set by firmware cleared by hardware set by the firmware cleared by hardware interrupt pending cleared by firmware dpr access by firmware dpr access by hardware cleared by firmware payload in fifo set by hardware data in 2 token in nak ack data in 1 token in token in ack data in 1 load in progress data in 2
678 32003e?avr32?05/06 at32ap7000 figure 32-8. data in transfer for endpoint with two banks figure 32-9. data in followed by status out transfer at the end of a control transfer note : a nak handshake is always generated at the first status stage token. read by usb device read by udphs device fifo (dpr) bank 0 tx_complt flag (udphs_eptstax) interrupt cleared by firmware virtual tx_pk_rdy bank 1 (udphs_eptstax) ack token in ack set by firmware, data payload written in fifo bank 1 cleared by hardware data payload fully transmitted token in usb bus packets set by hardware set by hardware set by firmware, data payload written in fifo bank 0 written by fifo (dpr) bank1 microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 udphs device send bank 0 microcontroller load data in bank 0 udphs device send bank 1 interrupt pending data in data in cleared by hardware switch to next bank virtual tx_pk_rdy bank 0 (udphs_eptstax) token out data in token in ack ack data out (zlp) rx_bk_rdy (udphs_eptstax) tx_complt (udphs_eptstax) set by hardware set by hardware usb bus packets cleared by firmware cleared by firmware device sends a status out to host device sends the last data payload to host interrupt pending token out ack data out (zlp)
679 32003e?avr32?05/06 at32ap7000 figure 32-10. data out followed by status in transfer note : before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). if not certain (non-predictable data stage length), then the software should wait for a nak-in interrupt before proceeding to the status stage. this pre- caution should be taken to av oid collision in the fifo. token in ack data out token out ack data in usb bus packets rx_bk_rdy (udphs_eptstax) cleared by firmware set by hardware clear by hardware tx_pk_rdy (udphs_eptstax) set by firmware host sends the last data payload to the device device sends a status in to the host interrupt pending
680 32003e?avr32?05/06 at32ap7000 figure 32-11. autovalid with dma note: in the illustration above autovalid validates a bank as full, although this might not be the case, in order to continue pr ocessing data and to send to dma. 32.5.6.7 isochronous in isochronous-in is used to transmit a stream of data whose timing is implied by the delivery rate. isochronous transfer provides periodic, continuous communication between host and device. it guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. if the endpoint is not available (tx_pk_rdy = 0), then the device does not answer to the host. an err_fl_iso interrupt is generated in the udphs_eptstax register and once enabled, then sent to the cpu. the stall_snt command bit is not used for an iso-in endpoint. bank 0 bank 1 bank 0 bank (usb) write write bank 0 write bank 1 write bank 0 bank 0 bank (system) bank 1 bank 0 bank 1 virtual tx_pk_rdy bank 0 virtual tx_pk_rdy bank 1 tx_pk_rdy (virtual 0 & virtual 1) bank 0 is full bank 1 is full bank 0 is full in data 0 in data 1 in data 0 bank 1 bank 1 bank 0
681 32003e?avr32?05/06 at32ap7000 32.5.6.8 high bandwidth isochronous endpoint handling: in example for high bandwidth isochronous endpoints, the dma can be programmed with the number of transactions (buff_length field in udphs_ dmacontrolx) and the system should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem. a response should be made to the first token in recognized inside a microframe under the fol- lowing conditions: ? if at least one bank has been validated, the correct datax corresponding to the programmed number of transactions per microframe (nb_trans) should be answered. in case of a subsequent missed or corrupted token in inside the microframe, the udphs core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. if this flush occurs, an er ror condition is flagg ed (err_flush is set in udphs_eptstax). ? if no bank is validated yet, the default data0 zlp is answered and underflow is flagged (err_fl_iso is set in udphs_eptstax). then, no data bank is flushed at microframe end. ? if no data bank has been validated at the time when a response should be made for the second transaction of nb_trans = 3 transactions microframe, a data1 zlp is answered and underflow is flagged (err_fl_iso is set in udphs_eptstax). if and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (err_flus h is set in udphs_eptstax). ? if no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a data0 zlp is answered and underflow is flagged (err_fl_iso is set in udphs_eptstax). if and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (err_flush is set in udphs_eptstax). ? if at the end of a microframe no valid token in has been recognized, no data bank is flushed and no error condition is reported. at the end of a microframe in which at least one data bank has been transmitted, if less than nb_trans banks have been validated for that microframe, an error condition is flagged (err_trans is set in udphs_eptstax). cases of error (in udphs_eptstax) ? err_fl_iso: there was no data to transmit inside a microframe, so a zlp is answered by default. ? err_flush: at least one packet has been sent inside the microframe, but the number of token in received is lesser than the number of transactions actually validated (tx_bk_rdy) and likewise with the nb_trans programmed. ? err_trans: at least one packet has been sent inside the microframe, but the number of token in received is lesser than the number of programmed nb_trans transactions and the packets not requested were not validated. ? err_fl_iso + err_flush: at least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token in. ? err_fl_iso + err_trans: at least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token in and the data can be discarded at the microframe end.
682 32003e?avr32?05/06 at32ap7000 ? err_flush + err_trans: the first token in has been answered and it was the only one received, a second bank has been validated but not the third, whereas nb_trans was waiting for three transactions. ? err_fl_iso + err_flush + err_trans: the first token in has been treated, the data for the second token in was not available in time, but the second bank has been validated before the end of the microframe. the third bank has not been validated, but three transactions have been set in nb_trans. 32.5.6.9 data out 32.5.6.10 bulk out or interrupt out like data in, data out packets are sent by the host during the data or the status stage of con- trol transfer or during an interrupt/bulk/isochronous out transfer. data buffers are sent packet by packet under the control of the application or under the control of the dma channel. 32.5.6.11 bulk out or interrupt out: receiving a packet under application control (host to device) algorithm description for each packet: ? the application enables an interrupt on rx_bk_rdy. ? when an interrupt on rx_bk_rdy is received , the application know s that udphs_eptstax register byte_count bytes have been received. ? the application reads the byte_count bytes from the endpoint. ? the application clears rx_bk_rdy. note: if the application does not know the size of the transfer, it may not be a good option to use auto_valid. because if a zero-length-packet is received, the rx_bk_rdy is automatically cleared by the auto_valid hardwa re and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the udphs_eptstax register. algorithm to fill several packets: ? the application enables the interrupts of busy_bank and auto_valid. ? when a busy_bank interrupt is received, the application knows that all banks available for the endpoint have be en filled. thus, the application can read all banks available. if the application doesn?t know the size of t he receive buffer, instead of using the busy_bank interrupt, the application must use rx_bk_rdy. 32.5.6.12 bulk out or interrupt out: sending a buffer using dma (host to device) to use the dma setting, the auto_valid field is mandatory. see 32.5.6.6 bulk in or interrupt in: sending a buffer using dma (device to host) for more information. dma configuration example: 1. first program udphs_dmaaddressx with the address of the buff er that should be transferred. 2. enable the interrupt of the dma in udphs_ien 3. program the dma channe lx control register: ? size of buffer to be sent. ? end_b_en: can be used for out packet truncation (discarding of unbuffered packet data) at the end of dma buffer.
683 32003e?avr32?05/06 at32ap7000 ? end_buffit: generate an interrupt when buff_count in the udphs_dmastatusx register reaches 0. ? end_tr_en: end of transfer enable, the udphs device can put an end to the current dma transfer, in case of a short packet. ? end_tr_it: end of transfer interrupt enable, an interrupt is sent after the last usb packet has been transferred by the dma, if the usb transfer ended with a short packet. (beneficial when the receive size is unknown.) ? chann_enb: run and stop at end of buffer. for out transfer, the bank will be automatical ly cleared by hardware when the application has read all the bytes in the bank (the bank is empty). note: when a zero-length-packet is received, rx_bk_rdy bit in udphs_eptstax is cleared automatically by auto_valid, and the application knows of the end of buffer by the presence of the end_tr_it. note: if the host sends a zero-length packet, and the endpoint is free, then the device sends an ack. no data is written in the endpoint, the rx_by_rdy interrupt is generated, and the byte_count field in udphs_eptstax is null. figure 32-12. data out transfer for endpoint with one bank ack token out nak token out ack token out data out 1 usb bus packets rx_bk_rdy set by hardware cleared by firmware, data payload written in fifo fifo (dpr) content written by udphs device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out 2 data out 2 host sends the next data payload written by udphs device (udphs_eptstax) interrupt pending
684 32003e?avr32?05/06 at32ap7000 figure 32-13. data out transfer for an endpoint with two banks 32.5.6.13 high bandwidth isochronous endpoint out figure 32-14. bank management, example of three transactions per microframe usb 2.0 supports individual high speed isochronous endpoints that require data rates up to 192 mb/s (24 mb/s): 3x1024 data bytes per microframe. to support such a rate, two or three banks ma y be used to buffer the three consecutive data packets. the microcontroller (or the dma) should be able to empty the banks very rapidly (at least 24 mb/s on average). nb_trans field in udphs_eptcfgx register = number of transactions per microframe. if nb_trans > 1 then it is high bandwidth. token out ack data out 3 token out data out 2 token out data out 1 data out 1 data out 2 data out 2 ack cleared by firmware usb bus packets virtual rx_bk_rdy bank 0 virtual rx_bk_rdy bank 1 set by hardware data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by udphs device write in progress read by microcontroller read by microcontroller set by hardware, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data 2 in bank 1, host sends third data payload cleared by firmware write by hardware fifo (dpr) (udphs_eptstax) interrupt pending interrupt pending rx_bk_rdy = (virtual bank 0 | virtual bank 1) data out 1 data out 3 m data 0 m data 0 m data 1 data 2 data 2 m data 1 t = 0 t = 52.5 s (40% of 125 s) rx_bk_rdy t = 125 s rx_bk_rdy usb line read bank 3 read bank 2 read bank 1 read bank 1 usb bus transactions microcontroller fifo (dpr) access
685 32003e?avr32?05/06 at32ap7000 example: ? if nb_trans = 3, the sequence should be either ?mdata0 ? mdata0/data1 ? mdata0/data1/data2 ? if nb_trans = 2, the sequence should be either ?mdata0 ? mdata0/data1 ? if nb_trans = 1, the sequence should be ? data0 32.5.6.14 isochronous endpoint handling: out example the user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the udphs_eptstax register in the three bit fields as follows: ? togglesq_sta: pid of the data stored in the current bank ? current_bank: number of the bank currently being accessed by the microcontroller. ? busy_bank_sta: number of busy bank this is particularly useful in case of a missing data packet. if the inter-packet delay between the out token and the data is greater than the usb standard, then the iso-out transaction is ignored. (payload data is not written, no interrupt is generated to the cpu.) if there is a data crc (cyclic redundancy check) error, the payload is, none the less, written in the endpoint. the err_criso flag is set in udphs_eptstax register. if the endpoint is already full, the packet is not written in the dpram. the err_fl_iso flag is set in udphs_eptstax. if the payload data is greater than the maximum size of the endpoint, then the err_ovflw flag is set. it is the task of the cpu to manage this error. the data packet is written in the endpoint (except the extra data). if the host sends a zero length packet, and the endpoint is free, no data is written in the end- point, the rx_bk_rdy flag is set, and the byt e_count field in udphs_eptstax register is null. the frcestall command bit is unused for an isochonous endpoint. otherwise, payload data is written in the endpoint, the rx_bk_rdy interrupt is generated and the byte_count in udphs_eptst ax register is updated.
686 32003e?avr32?05/06 at32ap7000 32.5.6.15 stall stall is returned by a function in response to an in token or after the data phase of an out or in response to a ping transaction. stall indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported. ?out to stall an endpoint, set the frcestall bit in udphs_eptsetstax register and after the stall_snt flag has been set, set the toggle_seg bit in the udphs_eptclrstax register. ?in set the frcestall bit in udphs_eptsetstax register. figure 32-15. stall handshake data out transfer figure 32-16. stall handshake data in transfer token out stall pid data out usb bus packets cleared by firmware set by firmware frcestall stall_snt set by hardware interrupt pending cleared by firmware token in stall pid usb bus packets cleared by firmware set by firmware frcestall stall_snt set by hardware cleared by firmware interrupt pending
687 32003e?avr32?05/06 at32ap7000 32.5.7 speed identification the high speed reset is managed by the hardware. at the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. at the end of the re set process (full or high), the endreset interrupt is generated. then the cpu should read the speed bit in udphs_intstax to ascertain the speed mode of the device. 32.5.8 usb v2.0 high speed global interrupt interrupts are defined in section 32.6.3 ?udphs interrupt enable register? (udphs_ien) and in section 32.6.4 ?udphs interrupt status register? (udphs_intsta). 32.5.9 endpoint interrupts interrupts are enabled in udphs_ien (see section 32.6.3 ?udphs interrupt enable register? ) and individually masked in udphs_eptctlenbx (see section 32.6.18 ?udphs endpoint control enable register? ). table 32-5. endpoint interrupt source masks shrt_pckt short packet interrupt busy_bank busy bank interrupt nak_out nakout interrupt nak_in/err_flush nakin/error flush interrupt stall_snt/err_criso/err_nb_tra stall sent/crc e rror/number of transaction error interrupt rx_setup/err_fl_iso received setup/error flow interrupt tx_pk_rd /err_trans tx packet read/transaction error interrupt tx_complt transmitted in da ta complete interrupt rx_bk_rdy received out data interrupt err_ovflw overflow error interrupt mdata_rx mdata interrupt datax_rx datax interrupt
688 32003e?avr32?05/06 at32ap7000 figure 32-17. udphs interrupt control interface det_suspd micro_sof ien_sof endreset wake_up endofrsm upstr_res usb global it sources ept0 it sources busy_bank nak_out (udphs_eptctlenbx) nak_in/err_flush stall_snt/err_criso/err_nb_tra rx_setup/err_fl_iso tx_bk_rdy/err_trans tx_complt rx_bk_rdy err_ovflw mdata_rx datax_rx (udphs_ien) ept1-6 it sources global it mask global it sources ep mask ep sources (udphs_ien) ept_int_0 ep mask ep sources (udphs_ien) ept_int_x (udphs_eptctlx) int_dis_dma dma ch x (udphs_dmacontrolx) en_buffit end_tr_it desc_ld_it mask mask mask (udphs_ien) dma_int_x shrt_pckt husb2dev interrupt disable dma channelx request
689 32003e?avr32?05/06 at32ap7000 32.5.10 power modes 32.5.10.1 controllin g device states a usb device has several possible states. refer to chapter 9 (usb device framework) of the universal serial bus specification, rev 2.0. figure 32-18. udphsdevice state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the us b device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 a on the usb bus. while in suspend mode, the host may wake up a de vice by sending a resume signal (bus activ- ity) or a usb device may send a wake-up request to the host, e.g., waking up a pc by moving a usb mouse. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
690 32003e?avr32?05/06 at32ap7000 the wake-up feature is not mandatory for all devices and must be negotiated with the host. 32.5.10.2 from powered state to default state (reset) after its connection to a usb host, the usb device waits for an end-of-bus reset. the unmasked flag endreset is set in the udphs_ien re gister and an inte rrupt is triggered. once the endreset interrupt has be en triggered, the devi ce enters default st ate. in this state, the udphs software must: ? enable the default endpoint, setting the ept_enabl flag in the udphs_eptctlenb[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in ept_int_0 of the udphs_ien register. the enumeration then begins by a control transfer. ? configure the interrupt mask register which has been reset by the usb reset detection ? enable the transceiver. in this state, the en_udphs bit in udphs_ctrl register must be enabled. 32.5.10.3 from default state to address state (address assigned) after a set address standard device request, the usb host peripheral enters the address state. warning : before the device enters address state, it must achieve the status in transaction of the control transfer, i.e., the udphs device sets its new address once the tx_complt flag in the udphs_eptctl[0] register has been received and cleared. to move to address state, the driver software sets the dev_addr field and the faddr_en flag in the udphs_ctrl register. 32.5.10.4 from address state to configured state (device configured) once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the bk_number, ept_type, ept_dir and ept_size fields in the udphs_eptcfgx registers and enabling them by setting the ept_enabl flag in the udphs_eptctlenbx registers, and, optionally, enabling corresponding interrupts in the udphs_ien register. 32.5.10.5 entering suspend state (bus activity) when a suspend (no bus activity on the usb bus ) is detected, the det_suspd signal in the udphs_sta register is set. this triggers an in terrupt if the corresponding bit is set in the udphs_ien register. this flag is cleared by wr iting to the udphs_clrint register. then the device enters suspend mode. in this state bus powered devices must drain less than 500 a from the 5v vbus. as an exam- ple, the microcontroller switches to slow clock, disables the pl l and main osc illator, and goes into idle mode. it may also switch off other devices on the board. the udphs device peripheral clocks can be s witched off. resume ev ent is asynchronously detected. 32.5.10.6 receiving a host resume in suspend mode, a resume event on the usb bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed).
691 32003e?avr32?05/06 at32ap7000 once the resume is detected on the bus, the signal wake_up in the udphs_intsta is set. it may generate an interrupt if the corresponding bit in the udphs_ien register is set. this inter- rupt may be used to wake-up th e core, enable pll an d main oscillators and configure clocks. 32.5.10.7 sending an external resume in suspend state it is possible to wake-up the host by sending an external resume. the device waits at least 5 ms after being entered in suspend state before sending an external resume. the device must force a k state from 1 to 15 ms to resume the host. 32.5.11 test mode a device must support the test_mode feature when in the default, address or configured high speed device states. test_mode can be: ?test_j ?test_k ? test_packet ? test_seo_nak (see section 32.6.11 ?udphs test register? on page 708 for definitions of each test mode.) const char test_packet_buffer[] = { // jkjkjkjk * 9 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // jjkkjjkk * 8 0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa, // jjkkjjkk * 8 0xee,0xee,0xee,0xee,0xee,0xee,0xee,0xee, // jjjjjjjkkkkkkk * 8 0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, // jjjjjjjk * 8 0x7f,0xbf,0xdf,0xef,0xf7,0xfb,0xfd, // {jkkkkkkk * 10}, jk 0xfc,0x7e,0xbf,0xdf,0xef,0xf7,0xfb,0xfd,0x7e };
692 32003e?avr32?05/06 at32ap7000 32.6 usb high speed device (udphs) user interface table 32-6. register mapping offset register name access reset 0x00 udphs control register udphs_ctrl read/write 0x0000_0200 0x04 udphs frame number register udphs_fnum read 0x0000_0000 0x08 - 0x0c reserved ? ? ? 0x10 udphs interrupt enable register udphs_ien read/write 0x0000_0010 0x14 udphs interrupt status register udphs_intsta read 0x0000_0000 0x18 udphs clear interrupt register udphs_clrint write ? 0x1c udphs endpoints reset register udphs_eptrst write ? 0x20 - 0xcc reserved ? ? ? 0xd0 udphs test sof counter register udphs_tstsofcnt read/write 0x0000_0000 0xd4 udphs test a counter register udphs_tstcnta read/write 0x0000_0000 0xd8 udphs test b counter register udphs_tstcntb read/write 0x0000_0000 0xdc udphs test mode register udphs_tstmodereg read/write 0x0000_0000 0xe0 udphs test register udphs_tst read/write 0x0000_0000 0xe4 - 0xe8 reserved ? ? ? 0xec udphs paddrsize register udphs_ippaddrsize read 0x0000_4000 0xf0 udphs name1 register udphs_ipname1 read 0x4855_5342 0xf4 udphs name2 register udphs_ipname2 read 0x3244_4556 0xf8 udphs features register udphs_ipfeatures read 0xfc udphs version register udphs_ipversion read 0x100 udphs endpoint configuration register udphs_eptcfgx read/write 0x0000_0000 0x104 udphs endpoint control enable register udphs_eptctlenbx write ? 0x108 udphs endpoint control disable register udphs_eptctldisx write ? 0x10c udphs endpoint control register udphs_eptctlx read 0x0000_0000 (1) 0x110 reserved ? ? ? 0x114 udphs endpoint set status register udphs_eptsetstax write ? 0x118 udphs endpoint clear status register udphs_eptclrstax write ? 0x11c udphs endpoint status register udphs_eptsta read 0x0000_0040 0x120 - 0x1fc endpoints 1 to 7 0x200 - 0x2fc endpoints 8 to 15 0x200 - 0x30c reserved ? ? ? 0x300 - 0x30c reserved ? ? ? 0x310 udphs dma next descriptor address register udphs_dmanxtdscx read/write 0x0000_0000 0x314 udphs dma channelx address register udphs_dmaaddressx r ead/write 0x0000_0000
693 32003e?avr32?05/06 at32ap7000 note: 1. the reset value for udphs_eptctl0 is 0x0000_0001 0x318 udphs dma channelx control register udphs_dmacontrolx read/write 0x0000_0000 0x31c udphs dma channelx status register udphs_dmastatusx read/write 0x0000_0000 0x320 - 0x37c dma channel 2 to 7 table 32-6. register mapping (continued) offset register name access reset
694 32003e?avr32?05/06 at32ap7000 32.6.1 udphs control register name: udphs_ctrl access type: read/write ? dev_addr: udphs address read: this field contains the default address (0) after power-up or udphs bus reset. write: this field is written with the value set by a set_address request received by the device firmware. ? faddr_en: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = only the default function address is used (0). 1 = this bit is set by the device firm ware after a successful status phase of a set_address transaction. when set, the only address accepted by the udphs cont roller is the one stored in the udphs a ddress field. it will not be cleared after- wards by the device firmware. it is cleared by hardware on hardware reset, or when udphs bus reset is received (see above). ? en_udphs: udphs enable read: 0 = udphs is disabled. 1 = udphs is enabled. write: 0 = disable and reset the udphs controller, disable the udphs transceiver. 1 = enables the udphs controller. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????rewakeupdetachen_udphs 76543210 faddr_en dev_addr
695 32003e?avr32?05/06 at32ap7000 ? detach: detach command read: 0 = udphs is attached. 1 = udphs is detached, utmi transceiver is suspended. write: 0 = pull up the dp line (attach command). 1 = simulate a detach on the udphs line and force the utmi transceiver into suspend state (suspend m = 0). ? rewakeup : send remote wake up read: 0 = remote wake up is disabled. 1 = remote wake up is enabled. write: 0 = no effect. 1 = force an external interrupt on the udphs controller for remote wake up purposes. an upstream resume is sent only after the udphs bus has been in suspend st ate for at least 5 ms. this bit is automatically cleared by hardware at the end of the upstream resume.
696 32003e?avr32?05/06 at32ap7000 32.6.2 udphs frame number register name: udphs_fnum access type: read ? micro_frame_num: microframe number number of the received microframe (0 to 7) in one frame.this field is reset at the beginning of each new frame (1 ms). one microframe is received each 125 microseconds (1 ms/8). ? frame_number: frame number as defined in the packet field formats this field is provided in the last received sof packet (see int_sof in the udphs interrupt status register ). ? fnum_err: frame number crc error this bit is set by hardware when a corrupted frame number in start of frame packet (or micro sof) is received. this bit and the int_sof (or micro_sof) interrupt are updated at the same time. 31 30 29 28 27 26 25 24 fnum_err??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? frame_number 76543210 frame_number micro_frame_num
697 32003e?avr32?05/06 at32ap7000 32.6.3 udphs interrupt enable register name: udphs_ien access type: read/write ? det_suspd: suspend interrupt enable read: 0 = suspend interrupt is disabled. 1 = suspend interrupt is enabled. write 0 = disable suspend interrupt. 1 = enable suspend interrupt. ? micro_sof: micro-sof interrupt enable read: 0 = micro-sof interrupt is disabled. 1 = micro-sof interrupt is enabled. write 0 = disable micro-sof interrupt. 1 = enable micro-sof interrupt. ? int_sof: sof interrupt enable read: 0 = sof interrupt is disabled. 1 = sof interrupt is enabled. write 0 = disable sof interrupt. 1 = enable sof interrupt. 31 30 29 28 27 26 25 24 dma_int_6 dma_int_5 dma_int_4 d ma_int_3 dma_int_2 dma_int_1 ? 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ept_int_7 ept_int_6 ept_int_5 ept_int_4 ept_int_3 ept_int_2 ept_int_1 ept_int_0 76543210 upstr_res endofrsm wake_up endreset int_sof micro_sof det_suspd ?
698 32003e?avr32?05/06 at32ap7000 ? endreset: end of reset interrupt enable read: 0 = end of reset interrupt is disabled. 1 = end of reset interrupt is enabled. write 0 = disable end of reset interrupt. 1 = enable end of reset interrupt. ? wake_up: wake up cpu interrupt enable read: 0 = wake up cpu interrupt is disabled. 1 = wake up cpu interrupt is enabled. write 0 = disable wake up cpu interrupt. 1 = enable wake up cpu interrupt. ? endofrsm: end of resume interrupt enable read: 0 = resume interrupt is disabled. 1 = resume interrupt is enabled. write 0 = disable resume interrupt. 1 = enable resume interrupt. ? upstr_res: upstream resume interrupt enable read: 0 = upstream resume interrupt is disabled. 1 = upstream resume interrupt is enabled. write 0 = disable upstream resume interrupt. 1 = enable upstream resume interrupt. ? ept_int_x: endpointx interrupt enable read: 0 = the interrupts for this endpoint are disabled. 1 = the interrupts for this endpoint are enabled. write 0 = disable the interrupts for this endpoint. 1 = enable the interrupts for this endpoint.
699 32003e?avr32?05/06 at32ap7000 ? dma_int_x: dma channelx interrupt enable read: 0 = the interrupts for this channel are disabled. 1 = the interrupts for this channel are enabled. write 0 = disable the interrupts for this channel. 1 = enable the interrupts for this channel.
700 32003e?avr32?05/06 at32ap7000 32.6.4 udphs interrupt status register name: udphs_intsta access type: read-only ? speed: speed status 0 = reset by hardware when the hardware is in full speed mode. 1 = set by hardware when the hardware is in high speed mode ? det_suspd: suspend interrupt 0 = cleared by setting the det_suspd bit in udphs_clrint register 1 = set by hardware when a udphs suspend (idle bus for three frame periods, a j state for 3 ms) is detected. this triggers a udphs interrupt when the det_suspd bit is set in udphs_ien register. ? micro_sof: micro start of frame interrupt 0 = cleared by setting the micro_sof bit in udphs_clrint register. 1 = set by hardware when an udphs micro start of frame pi d (sof) has been detected (every 125 us) or synthesized by the macro. this triggers a udphs interrupt when the micro_sof bit is set in udphs_ien. in case of detected sof, the micro_frame_num field in udphs_fnum register is incremented and the frame_number field doesn?t change. note: the micro start of frame interrupt (micro_sof), and the star t of frame interrupt (int_sof) are not generated at the same time. ? int_sof: start of frame interrupt 0 = cleared by setting the int_sof bit in udphs_clrint. 1 = set by hardware when an udphs start of frame pid (s of) has been detected (every 1 ms) or synthesized by the macro. this triggers a udphs interrupt when the int_sof bit is set in udphs_ien register. in case of detected sof, in high speed mode, the micro_frame_number field is cl eared in udphs_fnum register and the frame_number field is updated. ? endreset: end of reset interrupt 0 = cleared by setting the endreset bit in udphs_clrint. 1 = set by hardware when an end of reset has been detected by the udphs controller. this triggers a udphs interrupt when the endreset bit is set in udphs_ien. 31 30 29 28 27 26 25 24 dma_int_6 dma_int_5 dma_int_4 dma_int_3 dma_int_2 dma_int_1 ? 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ept_int_7 ept_int_6 ept_int _5 ept_int_4 ept_int_3 ept_i nt_2 ept_int_1 ept_int_0 76543210 upstr_res endofrsm wake_up endreset int_sof micro_sof det_suspd speed
701 32003e?avr32?05/06 at32ap7000 ? wake_up: wake up cpu interrupt 0 = cleared by setting the wake_up bit in udphs_clrint. 1 = set by hardware when the udphs cont roller is in suspend state and is re-act ivated by a filtered non-idle signal from the udphs line (not by an upstream resume). this tr iggers a udphs interrupt wh en the wake_up bit is set in udphs_ien register. when receiving this interrupt, the user has to enable the device controller clock prior to operation. note: this interrupt is generated even if the device controller clock is disabled. ? endofrsm: end of resume interrupt 0 = cleared by setting the endofrsm bit in udphs_clrint. 1 = set by hardware when the udphs controller detects a good en d of resume signal initiated by the host. this triggers a udphs interrupt when the endofr sm bit is set in udphs_ien. ? upstr_res: upstream resume interrupt 0 = cleared by setting the upstr_res bit in udphs_clrint. 1 = set by hardware when the udphs controller is sending a resume signal called ?upstream resume?. this triggers a udphs interrupt when the upstr_ res bit is set in udphs_ien. ? ept_int_x: endpointx interrupt 0 = reset when the udphs_eptstax interrupt source is cleared. 1 = set by hardware when an interrupt is triggered by the ud phs_eptstax register and this endpoint interrupt is enabled by the ept_int_x bit in udphs_ien. ? dma_int_x: dma channelx interrupt 0 = reset when the udphs_dmastatusx interrupt source is cleared. 1 = set by hardware when an interrupt is triggered by the dma channelx and this endpoint interrupt is enabled by the dma_int_x bit in udphs_ien.
702 32003e?avr32?05/06 at32ap7000 32.6.5 udphs clear interrupt register name: udphs_clrint access type: write only ? det_suspd: suspend interrupt clear 0 = no effect. 1 = clear the det_suspd bit in udphs_intsta. ? micro_sof: micro start of frame interrupt clear 0 = no effect. 1 = clear the micro_sof bit in udphs_intsta. ? int_sof: start of frame interrupt clear 0 = no effect. 1 = clear the int_sof bit in udphs_intsta. ? endreset: end of re set interrupt clear 0 = no effect. 1 = clear the endreset bit in udphs_intsta. ? wake_up: wake up cpu interrupt clear 0 = no effect. 1 = clear the wake_up bit in udphs_intsta. ? endofrsm: end of resume interrupt clear 0 = no effect. 1 = clear the endofrsm bit in udphs_intsta. ? upstr_res: upstream resume interrupt clear 0 = no effect. 1 = clear the upstr_res bit in udphs_intsta. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 upstr_res endofrsm wake_up endreset int_sof micro_sof det_suspd ?
703 32003e?avr32?05/06 at32ap7000 32.6.6 udphs endpoints reset register name: udphs_eptrst access type: write only ? rst_ept_x: endpointx reset 0 = no effect. 1 = reset the endpointx state. setting this bit clears the endpoint status udphs_ eptstax register, except fo r the togglesq_sta field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 76543210 rst_ept_7 rst_ept_6 rst_ept _5 rst_ept_4 rst_ept_3 rst_ ept_2 rst_ept_1 rst_ept_0
704 32003e?avr32?05/06 at32ap7000 32.6.7 udphs test sof counter register name: udphs_tstsofcnt access type: read/write ? sofcntmax: sof counter max value ? sofctload: sof counter load 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sofctload sofcntmax
705 32003e?avr32?05/06 at32ap7000 32.6.8 udphs test a counter register name: udphs_tstcnta access type: read/write ? cntaload: a counter load ? cntamax: a counter max value 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cntaload cntamax 76543210 cntamax
706 32003e?avr32?05/06 at32ap7000 32.6.9 udphs test b counter register name: udphs_tstcntb access type: read/write ? cntbload: b counter load ? cntbmax: b counter max value 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cntbload ? cntbmax
707 32003e?avr32?05/06 at32ap7000 32.6.10 udphs test mode register name: udphs_tstmodereg access type: read/write ? tstmode: udphs core testmodereg 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?? tstmode
708 32003e?avr32?05/06 at32ap7000 32.6.11 udphs test register name: udphs_tst access type: read/write ? speed_cfg: speed configuration read/write: speed configuration: ? tst_j: test j mode read and write: 0 = no effect. 1 = set to send the j state on the udphs line. this enables the testing of the high output drive level on the d+ line. ? tst_k: test k mode read and write: 0 = no effect. 1 = set to send the k state on the udphs line. this enables the testing of the high output drive level on the d- line. ? tst_pkt: test packet mode read and write: 0 = no effect. 1 = set to repetitively transmit the packet stored in the current bank. this enables the testing of rise and fall times, eye pa t- terns, jitter, and any other dynamic waveform specifications. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? opmode2 tst_pkt tst_k tst_j speed_cfg 00 normal mode: the macro is in full speed mode, ready to make a high speed identification, if the host supports it and then to automatically switch to high speed mode 01 reserved 10 force high speed: set this value to force the hardware to work in high speed mode. only for debug or test purpose. 11 force full speed: set this value to force the hardware to work only in full speed mode. in this configuration, the macro will not respond to a high speed reset handshake
709 32003e?avr32?05/06 at32ap7000 ? opmode2: opmode2 read and write: 0 = no effect. 1 = set to force the opmode signal (utmi interface) to ?10?, to disable the bit-stuffing and the nrzi encoding. note: for the test mode, test_se0_nak (see universal serial bus specification, revision 2.0: 7.1.20, test mode sup- port). force the device in high speed m ode, and configure a bulk-ty pe endpoint. do not fill this endpoint for sending nak to the host. upon command, a port?s transceiver must enter the high speed receive mode and remain in that mode until the exit action is taken. this enables the testing of output impedance, low level output voltage and loading characteristics. in addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any in token packet with a nak handshake (only if the packet crc is dete rmined to be correct) within the norm al allowed device response time. this enables testing of the device squelch level circuitry and, additi onally, provides a general purpose stimulus/response test for basic functional testing.
710 32003e?avr32?05/06 at32ap7000 32.6.12 udphs paddrsize register name: udphs_ippaddrsize access type: read-only ? ip_paddrsize 2^udphs_paddr_size apb address bus aperture of the udphs 31 30 29 28 27 26 25 24 ip_paddrsize 23 22 21 20 19 18 17 16 ip_paddrsize 15 14 13 12 11 10 9 8 ip_paddrsize 76543210 ip_paddrsize
711 32003e?avr32?05/06 at32ap7000 32.6.13 udphs name1 register name: udphs_ipname1 access type: read-only ? ip_name1 ascii string ?husb? 31 30 29 28 27 26 25 24 ip_name1 23 22 21 20 19 18 17 16 ip_name1 15 14 13 12 11 10 9 8 ip_name1 76543210 ip_name1
712 32003e?avr32?05/06 at32ap7000 32.6.14 udphs name2 register name: udphs_ipname2 access type: read-only ? ip_name2 ascii string ?2dev? 31 30 29 28 27 26 25 24 ip_name2 23 22 21 20 19 18 17 16 ip_name2 15 14 13 12 11 10 9 8 ip_name2 76543210 ip_name2
713 32003e?avr32?05/06 at32ap7000 32.6.15 udphs features register name: udphs_ipfeatures access type: read-only ? ept_nbr_max: max number of endpoints give the max number of endpoints. 0 = if 16 endpoints are hardware implemented. 1 = if 1 endpoint is hardware implemented. 2 = if 2 endpoints are hardware implemented. ... 15 = if 15 endpoints are hardware implemented. ? dma_channel_nbr: number of dma channels give the number of dma channels. 1 = if 1 dma channel is hardware implemented. 2 = if 2 dma channels are hardware implemented. ... 7 = if 7 dma channels are hardware implemented. ? dma_b_siz: dma buffer size 0 = if the dma buffer size is 16 bits. 1 = if the dma buffer size is 24 bits. ? dma_fifo_word_depth: dma fifo depth in words 0 = if fifo is 16 words deep. 1 = if fifo is 1 word deep. 2 = if fifo is 2 words deep. ... 15 = if fifo is 15 words deep. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iso_ept_7 iso_ept_6 iso_ept_5 iso_ept_4 is o_ept_3 iso_ept_2 iso_ept_1 datab16_8 15 14 13 12 11 10 9 8 bw_dpram fifo_max_size dma_fifo_word_depth 76543210 dma_b_siz dma_channel_nbr ept_nbr_max
714 32003e?avr32?05/06 at32ap7000 ? fifo_max_size: dpram size 0 = if dpram is 128 bytes deep. 1 = if dpram is 256 bytes deep. 2 = if dpram is 512 bytes deep. 3 = if dpram is 1024 bytes deep. 4 = if dpram is 2048 bytes deep. 5 = if dpram is 4096 bytes deep. 6 = if dpram is 8192 bytes deep. 7 = if dpram is 16384 bytes deep. ? bw_dpram: dpram by te write capability 0 = if dpram write data shadow logic is implemented. 1 = if dpram is byte write capable. ? datab16_8: utmi databus16_8 0 = if the utmi uses an 8-bit parallel data interface (60 mhz, unidirectional). 1 = if the utmi uses a 16-bit parallel data interface (30 mhz, bidirectional). ? iso_ept_x: endpointx high bandwidth isochronous capability 0 = if the endpoint does not have isochronous high bandwidth capability. 1 = if the endpoint has isochronous high bandwidth capability.
715 32003e?avr32?05/06 at32ap7000 32.6.16 udphs version register name: udphs_ipversion access type: read-only ? version_num: ip version give the ip version. ? metal_fix_num: number of metal fixes give the number of metal fixes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? metal_fix_num 15 14 13 12 11 10 9 8 version_num 76543210 version_num
716 32003e?avr32?05/06 at32ap7000 32.6.17 udphs endpoint configuration register name: udphs_eptcfgx access type: read/write ? ept_size: endpoint size read and write: set this field according to the endpoint size in bytes (see section 32.5.4 ?endpoint configuration? ). endpoint size note: 1. 1024 bytes is only for isochronous endpoint. ? ept_dir: endpoint direction read and write: 0 = clear this bit to configure out direction for bulk, interrupt and isochronous endpoints. 1 = set this bit to configure in direction for bulk, interrupt and isochronous endpoints. for control endpoints this bit has no effect and should be left at zero. ? ept_type: endpoint type read and write: set this field according to the endpoint type (see section 32.5.4 ?endpoint configuration? ). (endpoint 0 should always be configured as control) 31 30 29 28 27 26 25 24 ept_mapd??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? nb_trans 76543210 bk_number ept_type ept_dir ept_size 000 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101 256 bytes 110 512 bytes 111 1024 bytes (1)
717 32003e?avr32?05/06 at32ap7000 endpoint type: ? bk_number: number of banks read and write: set this field according to the endpoint?s number of banks (see section 32.5.4 ?endpoint configuration? ). number of banks ? nb_trans: number of tr ansaction per microframe read and write: the number of transactions per microframe is set by software. note: meaningful for high bandwidth isochronous endpoint only. ? ept_mapd: endpoint mapped read-only: 0 = the user should reprogram the register with correct values. 1 = set by hardware when the endpoint size (ept_size) an d the number of banks (bk_number) are correct regarding: ? the fifo max capacity (fifo_max_ size in udphs_ipfeatures register) ? the number of endpoints/banks already allocated ? the number of allowed banks for this endpoint 00 control endpoint 01 isochronous endpoint 10 bulk endpoint 11 interrupt endpoint 00 zero bank, the endpoint is not mapped in memory 01 one bank (bank 0) 10 double bank (ping-pong: bank 0/bank 1) 11 triple bank (bank 0/bank 1/bank 2)
718 32003e?avr32?05/06 at32ap7000 32.6.18 udphs endpoint control enable register name: udphs_eptctlenbx access type: write-only for additional information, see ?udphs endpoint contro l register? on page 722 . ? ept_enabl: endpoint enable 0 = no effect. 1 = enable endpoint according to the device configuration. ? auto_valid: packet auto-valid enable 0 = no effect. 1 = enable this bit to automatically validate the current packet and switch to the next bank for both in and out transfers. ? intdis_dma: interrupts disable dma 0 = no effect. 1 = if set, when an enabled endpoint-originated interrupt is triggered, the dma request is disabled. ? nyet_dis: nyet disable (only fo r high speed bulk out endpoints) 0 = no effect. 1 = forces an ack response to the next high spee d bulk out transfer instead of a nyet response. ? datax_rx: datax interrupt enable (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = enable datax interrupt. ? mdata_rx: mdata interrupt enable (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = enable mdata interrupt. 31 30 29 28 27 26 25 24 shrt_pckt??????? 23 22 21 20 19 18 17 16 ?????busy_bank?? 15 14 13 12 11 10 9 8 nak_out nak_in/ err_flush stall_snt/ err_criso/ err_nbtra rx_setup/ err_fl_iso tx_pk_rdy/ err_trans tx_complt rx_bk_rdy err_ovflw 76543210 mdata_rx datax_rx ? nyet_dis intdis_dma ? auto_valid ept_enabl
719 32003e?avr32?05/06 at32ap7000 ? err_ovflw: overflow error interrupt enable 0 = no effect. 1 = enable overflow error interrupt. ? rx_bk_rdy: received out data interrupt enable 0 = no effect. 1 = enable received out data interrupt. ? tx_complt: transmitted in data complete interrupt enable 0 = no effect. 1 = enable transmitted in data complete interrupt. ? tx_pk_rdy/err_trans: tx packet read y/transaction error interrupt enable 0 = no effect. 1 = enable tx packet ready/transaction error interrupt. ? rx_setup/err_fl_iso: received set up/error flow interrupt enable 0 = no effect. 1 = enable rx_setup/error flow iso interrupt. ? stall_snt/err_criso/err_nbtra: stal l sent /iso crc error/number of transaction error interrupt enable 0 = no effect. 1 = enable stall sent/error crc iso/erro r number of tran saction interrupt. ? nak_in/err_flush: nakin/bank flush error interrupt enable 0 = no effect. 1 = enable nakin/bank flush error interrupt. ? nak_out: nakout interrupt enable 0 = no effect. 1 = enable nakout interrupt. ? busy_bank: busy bank interrupt enable 0 = no effect. 1 = enable busy bank interrupt. ? shrt_pckt: short packet send/short packet interrupt enable for out endpoints: 0 = no effect. 1 = enable short packet interrupt. for in endpoints: guarantees short packet at end of dma transfer if the udphs_dmacontrolx register end_b_en and udphs_eptctlx register autovalid bits are also set.
720 32003e?avr32?05/06 at32ap7000 32.6.19 udphs endpoint control disable register name: udphs_eptctldisx access type: write-only for additional information, see ?udphs endpoint contro l register? on page 722 . ? ept_disabl: endpoint disable 0 = no effect. 1 = disable endpoint. ? auto_valid: packet auto-valid disable 0 = no effect. 1 = disable this bit to not automatically validate the current packet. ? intdis_dma: interrupts disable dma 0 = no effect. 1 = disable the ?interrupts disable dma?. ? nyet_dis: nyet enable (only for high speed bulk out endpoints) 0 = no effect. 1 = let the hardware handle the handshake response for the high speed bulk out transfer. ? datax_rx: datax interrupt disable (only fo r high bandwidth isochronous out endpoints) 0 = no effect. 1 = disable datax interrupt. ? mdata_rx: mdata interrupt disable (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = disable mdata interrupt. 31 30 29 28 27 26 25 24 shrt_pckt??????? 23 22 21 20 19 18 17 16 ?????busy_bank?? 15 14 13 12 11 10 9 8 nak_out nak_in/ err_flush stall_snt/ err_criso/ err_nbtra rx_setup/ err_fl_iso tx_pk_rdy/ err_trans tx_complt rx_bk_rdy err_ovflw 76543210 mdata_rx datax_rx ? nyet_dis intdis_dma ? auto_valid ept_disabl
721 32003e?avr32?05/06 at32ap7000 ? err_ovflw: overflow error interrupt disable 0 = no effect. 1 = disable overflow error interrupt. ? rx_bk_rdy: received out data interrupt disable 0 = no effect. 1 = disable received out data interrupt. ? tx_complt: transmitted in data complete interrupt disable 0 = no effect. 1 = disable transmitted in data complete interrupt. ? tx_pk_rdy/err_trans: tx packet read y/transaction error interrupt disable 0 = no effect. 1 = disable tx packet ready/transaction error interrupt. ? rx_setup/err_fl_iso: received setup /error flow interrupt disable 0 = no effect. 1 = disable rx_setup/error flow iso interrupt. ? stall_snt/err_criso/err_nbtra: stall sent/iso crc er ror/number of transacti on error interrupt disable 0 = no effect. 1 = disable stall sent/error crc iso/error number of transaction interrupt. ? nak_in/err_flush: nakin/bank flush error interrupt disable 0 = no effect. 1 = disable nakin/ bank flush error interrupt. ? nak_out: nakout interrupt disable 0 = no effect. 1 = disable nakout interrupt. ? busy_bank: busy bank interrupt disable 0 = no effect. 1 = disable busy bank interrupt. ? shrt_pckt: short packet interrupt disable for out endpoints: 0 = no effect. 1 = disable short packet interrupt. for in endpoints: never automatically add a zero length packet at end of dma transfer. .
722 32003e?avr32?05/06 at32ap7000 32.6.20 udphs endpoint control register name: udphs_eptctlx access type: read-only ? ept_enabl: endpoint enable 0 = if cleared, the endpoint is disabled according to the devi ce configuration. endpoint 0 should always be enabled after a hardware or udphs bus reset and participate in the device configuration. 1 = if set, the endpoint is enabled according to the device configuration. ? auto_valid: packet auto-valid enabled (not for control endpoints) set this bit to automatically validate the current packet and switch to the next bank for both in and out endpoints. for in transfer: if this bit is set, then the udphs_eptstax register tx_pk_ rdy bit is set automatically when the current bank is full and at the end of dma buffer if the udphs_dmacontrolx register end_b_en bit is set. the user may still set the udphs_eptstax register tx_pk_rdy bit if the curren t bank is not full, unless the user wants to send a zero length packet by software. for out transfer: if this bit is set, then the udphs_eptstax register rx_ bk_rdy bit is automatically reset for the current bank when the last packet byte has been read from the bank fifo or at the end of dma buffer if the udphs_dmacontrolx reg- ister end_b_en bit is set. for example, to truncate a padded data packet when the actual da ta transfer size is reached. the user may still clear the udphs_eptst ax register rx_bk_rdy bit, for exampl e, after completing a dma buffer by software if udphs_dmacontrolx register end_b_en bit was di sabled or in order to cancel the read of the remain- ing data bank(s). ? intdis_dma: interrupt disables dma if set, when an enabled endpoint-originated interrupt is triggered, the dma request is disabled regardless of the udphs_ien register ept_int_x bit for th is endpoint. then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed. if the exception raised is associated with the new system bank packet, then the previous dma packet transfer is normally completed, but the new dma packet transfer is not started (not requested). if the exception raised is not associated to a new system bank packet (nak_in, nak_out, err_fl_iso...), then the request cancellation may happen at any time and may immediately stop the current dma transfer. 31 30 29 28 27 26 25 24 shrt_pckt??????? 23 22 21 20 19 18 17 16 ?????busy_bank?? 15 14 13 12 11 10 9 8 nak_out nak_in/ err_flush stall_snt/ err_criso/ err_nbtra rx_setup/ err_fl_iso tx_pk_rdy/ err_trans tx_complt rx_bk_rdy err_ovflw 76543210 mdata_rx datax_rx ? nyet_dis intdis_dma ? auto_valid ept_enabl
723 32003e?avr32?05/06 at32ap7000 this may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a dma buffer by software after reception of a short packet, or to perform buffer truncation on err_fl_iso interrupt for adaptive rate. ? nyet_dis: nyet disable (only for high speed bulk out endpoints) 0 = if clear, this bit lets the hardware handle the handshake response for the high speed bulk out transfer. 1 = if set, this bit forces an ack response to the next high speed bulk out transfer instead of a nyet response. note: according to the universal serial bus specification, rev 2.0 (8.5.1.1 nak responses to out/ data during ping protocol), a nak response to an hs bulk out transfer is expected to be an unusual occurrence. ? datax_rx: datax interrupt enabled (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = send an interrupt when a data2, da ta1 or data0 packet has been received meaning the whole microframe data payload has been received. ? mdata_rx: mdata interrupt enabled (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = send an interrupt when an mdata packet has been received and so at least one packet of the microframe data pay- load has been received. ? err_ovflw: overflow error interrupt enabled 0 = overflow error interrupt is masked. 1 = overflow error interrupt is enabled. ? rx_bk_rdy: received out data interrupt enabled 0 = received out data interrupt is masked. 1 = received out data interrupt is enabled. ? tx_complt: transmitted in data complete interrupt enabled 0 = transmitted in data co mplete interrupt is masked. 1 = transmitted in data comp lete interrupt is enabled. ? tx_pk_rdy/err_trans: tx packet read y/transaction error interrupt enabled 0 = tx packet ready/transaction error interrupt is masked. 1 = tx packet ready/transaction error interrupt is enabled. caution: interrupt source is active as long as the corresponding udphs_eptstax register tx_pk_rdy flag remains low. if there are no more banks available for transmitting after the software has set udphs_eptstax/tx_pk_rdy for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at udphs_eptstax/tx_pk_rdy hardware clear. ? rx_setup/err_fl_iso: received setup /error flow interrupt enabled 0 = received setup/error flow interrupt is masked. 1 = received setup/error flow interrupt is enabled.
724 32003e?avr32?05/06 at32ap7000 ? stall_snt/err_criso/err_nbtra: stall sent/iso crc er ror/number of transaction error interrupt enabled 0 = stall sent/iso crc error/number of transaction error interrupt is masked. 1 = stall sent /iso crc error/number of transaction error interrupt is enabled. ? nak_in/err_flush: nakin/bank flush error interrupt enabled 0 = nakin interrupt is masked. 1 = nakin/bank flush error interrupt is enabled. ? nak_out: nakout interrupt enabled 0 = nakout interrupt is masked. 1 = nakout interrupt is enabled. ? busy_bank: busy bank interrupt enabled 0 = busy_bank interrupt is masked. 1 = busy_bank interrupt is enabled. for out endpoints : an interrupt is sent when all banks are busy. for in endpoints: an interrupt is sent when all banks are free . ? shrt_pckt: short packet interrupt enabled for out endpoints : send an interrupt when a short packet has been received. 0 = short packet interrupt is masked. 1 = short packet interrupt is enabled. for in endpoints : a short packet transmission is guaranteed upon end of the dma transfer, thus signaling a bulk or interrupt end of transfer or an end of isochronous (mic ro-)frame data, but only if the udphs_dmacontrolx reg- ister end_b_en and udphs_eptctlx regi ster auto_valid bits are also set.
725 32003e?avr32?05/06 at32ap7000 32.6.21 udphs endpoint set status register name: udphs_eptsetstax access type: write-only ? frcestall: stall handshake request set 0 = no effect. 1 = set this bit to request a stall answer to the host for the next handshake refer to chapters 8.4.5 (handshake packets) and 9.4.5 (get status) of the universal serial bus sp ecification, rev 2.0 for more information on the stall handshake. ? kill_bank: kill bank set (for in endpoint) 0 = no effect. 1 = kill the last written bank. ? tx_pk_rdy: tx packet ready set 0 = no effect. 1 = set this bit after a packet has been written into the endpoint fifo for in data transfers ? this flag is used to generate a data in transaction (device to host). ? device firmware checks that it can write a data payload in the fifo, checking that tx_pk_rdy is cleared. ? transfer to the fifo is done by writing in the ?buffer address? register. ? once the data payload has been transferred to the fifo, the firmware notifies the udphs device setting tx_pk_rdy to one. ? udphs bus transactions can start. ? txcomp is set once the data payload has been received by the host. ? data should be written into the endpoint fifo only after this bit has been cleared. ? set this bit without writing data to the endpoint fifo to send a zero length packet. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????tx_pk_rdy?ki ll_bank ? 76543210 ??frcestall?????
726 32003e?avr32?05/06 at32ap7000 32.6.22 udphs endpoint clear status register name: udphs_eptclrstax access type: write-only ? frcestall: stall handshake request clear 0 = no effect. 1 = clear the stall request. the next packets from host will not be stalled. ? togglesq: data toggle clear 0 = no effect. 1 = clear the pid data of the current bank for out endpoints, the next received packet should be a data0. for in endpoints, the next pa cket will be sent with a data0 pid. ? rx_bk_rdy: receive d out data clear 0 = no effect. 1 = clear the rx_bk_rdy flag of udphs_eptstax. ? tx_complt: transmitted in data complete clear 0 = no effect. 1 = clear the tx_complt flag of udphs_eptstax. ? rx_setup/err_fl_iso: received setup/error flow clear 0 = no effect. 1 = clear the rx_setup/err_fl_iso flags of udphs_eptstax. ? stall_snt/err_nbtra: stall sent/number of transaction error clear 0 = no effect. 1 = clear the stall_snt/err_nbtra flags of udphs_eptstax. ? nak_in/err_flush: nakin/bank flush error clear 0 = no effect. 1 = clear the nak_in/err_flus h flags of udphs_eptstax. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 nak_out nak_in/ err_flush stall_snt/ err_nbtra rx_setup/ err_fl_iso ? tx_complt rx_bk_rdy ? 76543210 ?togglesqfrcestall?????
727 32003e?avr32?05/06 at32ap7000 ? nak_out: nakout clear 0 = no effect. 1 = clear the nak_out flag of udphs_eptstax.
728 32003e?avr32?05/06 at32ap7000 32.6.23 udphs endpoint status register name: udphs_eptstax access type: read-only ? frcestall: stall handshake request 0 = no effect. 1= if set a stall answer will be done to the host for the next handshake. this bit is reset by hardware upon received setup. ? togglesq_sta: toggle sequencing toggle sequencing: in endpoint : it indicates the pid data toggle that will be used for the next packet sent. this is not relative to the current bank. control and out endpoint : these bits are set by hardware to indicate the pid data of the current bank: note 1: in out transfer, the toggle information is meaningful only when the current bank is busy (received out data = 1). note 2: these bits are updated for out transfer: ? a new data has been written into the current bank. ? the user has just cleared the received out data bit to switch to the next bank. note 3: for high bandwidth isochronous out endpoint, it is recommended to check the udphs_eptstax/err_trans bit to know if the toggle sequencing is correct or not. note 4: this field is reset to data1 by the udphs_eptclrs tax register togglesq bit, and by udphs_eptctldisx (disable endpoint). 31 30 29 28 27 26 25 24 shrt_pckt byte_count 23 22 21 20 19 18 17 16 byte_count busy_bank_sta current_bank/ control_dir 15 14 13 12 11 10 9 8 nak_out nak_in/ err_flush stall_snt/ err_criso/ err_nbtra rx_setup/ err_fl_iso tx_pk_rdy/ err_trans tx_complt rx_bk_rdy/ kill_bank err_ovflw 76543210 togglesq_stafrcestall????? 00 data0 01 data1 10 data2 (only for high bandwidth isochronous endpoint) 11 mdata (only for high bandwidth isochronous endpoint)
729 32003e?avr32?05/06 at32ap7000 ? err_ovflw: overflow error this bit is set by hardware when a new too-long packet is received. example: if the user programs an endpoint 64 bytes wide and th e host sends 128 bytes in an out transfer, then the over- flow error bit is set. this bit is updated at the same time as the byte_count field. this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). ? rx_bk_rdy/kill_bank: rece ived out data/kill bank received out data : (for out endpoint or control endpoint) this bit is set by hardware after a new packet has been stored in the endpoint fifo. this bit is cleared by the device firmware af ter reading the out data from the endpoint. for multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. hardware assertion of this bit may generate an interrupt if enabled by the udphs_eptctlx register rx_bk_rdy bit. this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). kill bank : (for in endpoint) ? the bank is really cleared or the bank is sent, busy_bank_sta is decremented. ? the bank is not cleared but sent on the in transfer, tx_complt ? the bank is not cleared because it was empty. the user sh ould wait that this bit is cleared before trying to clear another packet. note: ?kill a packet? may be refused if at the same time, an in token is coming and the curre nt packet is sent on the udphs line. in this case, the tx_complt bit is set. take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an in token is coming. in fa ct, in that case, the current bank is sent (in transfe r) and the last bank is killed. ? tx_complt: transmitted in data complete this bit is set by hardware after an in packet has been transmitted for isochronous endpoints and after it has been accepted (ack?ed) by the host for control, bulk and interrupt endpoints. this bit is reset by udphs_eptrst register rst_ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? tx_pk_rdy/err_trans: tx packet ready/transaction error tx packet ready: this bit is cleared by hardware, as soon as the packet has been sent for isochronous endpoints, or after the host has acknowledged the packet for control, bulk and interrupt endpoints. for multi-bank endpoints, this bit may remain clear even afte r software is set if another bank is available to transmit. hardware clear of this bit may generate an interrupt if enabled by the udphs_eptctlx register tx_pk_rdy bit. this bit is reset by udphs_eptrst register rst_ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). transaction error : (for high bandwidth isochronous out endpoints) (read-only)
730 32003e?avr32?05/06 at32ap7000 this bit is set by hardware when a transa ction error occurs inside one microframe. if one toggle sequencing problem occurs amo ng the n-transactions (n = 1, 2 or 3) in side a microframe, then this bit is still set as long as the current bank contains one ?bad? n-transaction. (see ?current_bank/control_dir: current bank/control direction? on page 731 ) as soon as the current bank is relative to a new ?good? n-transactions, then this bit is reset. note1 : a transaction error occurs when the toggle sequencing does not respect the universal serial bus specification, rev 2.0 (5.9.2 high bandwidth isochronous endpoints) (bad pid, missing data....) note2 : when a transaction error occurs, the user may empty all the ?bad? transactions by clearing the received out data flag (rx_bk_rdy). if this bit is reset, then the user should consider that a new n-transaction is coming. this bit is reset by udphs_eptrst register rst_ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? rx_setup/err_fl_iso: received setup/error flow received setup : (for control endpoint only) this bit is set by hardware when a valid setup packet has been received from the host. it is cleared by the device firmware after reading the setup data from the endpoint fifo. this bit is reset by udphs_eptrst register rst_ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). error flow : (for isochronous endpoint only) this bit is set by hardware w hen a transaction error occurs. ? isochronous in transaction is missed, the micr o has no time to fill t he endpoint (underflow). ? isochronous out data is dropped because the bank is busy (overflow). this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). ? stall_snt/err_criso/err_nbtra: stall sent/c rc iso error/number of transaction error stall_snt : (for control, bulk and interrupt endpoints) this bit is set by hardware after a stall handshake ha s been sent as requested by the udphs_eptstax register frcestall bit. this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). err_criso : (for isochronous out endpoints) (read-only) this bit is set by hardware if the last received data is corrupted (crc error on data). this bit is updated by hardware when new data is received (received out data bit). err_nbtra : (for high bandwidth isochronous in endpoints) this bit is set at the end of a microframe in which at l east one data bank has been transmitted, if less than the number of transactions per micro-frame banks (udphs_eptcfgx regist er nb_trans) have been validated for transmission inside this microframe. this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint).
731 32003e?avr32?05/06 at32ap7000 ? nak_in/err_flush: nak in/bank flush error nak_in : this bit is set by hardware when a nak handshake has bee n sent in response to an in request from the host. this bit is cleared by software. err_flush : (for high bandwidth isochronous in endpoints) this bit is set when flushing unsent banks at the end of a microframe. this bit is reset by udphs_eptrst register rst_ept_x (reset endpoint) and by ept_ctl_disx (disable endpoint). ? nak_out: nak out this bit is set by hardware when a nak handshake has been sent in response to an out or ping request from the host. this bit is reset by udphs_eptrst register rst_ept_x (reset endpoint) and by ept_ctl_disx (disable endpoint). ? current_bank/control_dir: cu rrent bank/control direction current bank : (all endpoints except control endpoint) these bits are set by hardware to indicate the number of the current bank. note: the current bank is updated each time the user: ? sets the tx packet ready bit to prepare the next in transfer and to switch to the next bank. ? clears the received out data bit to access the next bank. this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). control direction : (for control endpoint only) 0 = a control write is requested by the host. 1 = a control read is requested by the host. note1: this bit corresponds with the 7th bit of the bmrequesttype (byte 0 of the setup data). note2: this bit is updated after receiving new setup data. ? busy_bank_sta: busy bank number these bits are set by hardware to indicate the number of busy banks. in endpoint : it indicates the number of busy banks filled by the us er, ready for in transfer. out endpoint : it indicates the number of busy banks filled by out transaction from the host. 00 bank 0 (or single bank) 01 bank 1 10 bank 2 11 invalid 00 all banks are free 01 1 busy bank 10 2 busy banks 11 3 busy banks
732 32003e?avr32?05/06 at32ap7000 ? byte_count: udphs byte count byte count of a received data packet. this field is incremented after each write into the endpoint (to prepare an in transfer). this field is decremented after each reading into the endpoint (out transfer). this field is also updated at rx_bk_rdy flag clear with the next bank. this field is also updated at tx_pk_rdy flag set with the next bank. this field is reset by rst_ept _x of udphs_eptrst register. ? shrt_pckt: short packet an out short packet is detected when the receive byte count is less than the configured udphs_eptcfgx register ept_size. this bit is updated at the same time as the byte_count field. this bit is reset by udphs_eptrst register rst_ep t_x (reset endpoint) and by udphs_eptctldisx (disable endpoint).
733 32003e?avr32?05/06 at32ap7000 32.6.24 udphs dma channel transfer descriptor the dma channel transfer descriptor is loaded from the memory. be careful with the alignment of this buffer. the structure of the dma channel transfer descriptor is defined by three parameters as described below: offset 0: the address must be aligned: 0xxxxx0 next descriptor address register: udphs_dmanxtdscx offset 4: the address must be aligned: 0xxxxx4 dma channelx address register: udphs_dmaaddressx offset 8: the address must be aligned: 0xxxxx8 dma channelx control register: udphs_dmacontrolx to use the dma channel transfer descriptor, fill the structures with the correct va lue (as described in the following pages). then write directly in udphs_dmanxtdscx the address of the descriptor to be used first. then write 1 in the ldnxt_dsc bit of ud phs_dmacontrolx (load next channel tran sfer descriptor). the descriptor is automatically loaded upon endpointx request for packet transfer.
734 32003e?avr32?05/06 at32ap7000 32.6.25 udphs dma next de scriptor address register name: udphs_dmanxtdscx access type: read/write ? nxt_dsc_add this field points to the next channel descri ptor to be processed. this channel descri ptor must be aligned, so bits 0 to 3 of the address must be equal to zero. 31 30 29 28 27 26 25 24 nxt_dsc_add 23 22 21 20 19 18 17 16 nxt_dsc_add 15 14 13 12 11 10 9 8 nxt_dsc_add 76543210 nxt_dsc_add
735 32003e?avr32?05/06 at32ap7000 32.6.26 udphs dma channelx address register name: udphs_dmaaddressx access type: read/write ? buff_add this field determines the ahb bus starting address of a dma channel transfer. channel start and end addresses may be aligned on any byte boundary. the firmware may write this field only when the udphs_dmastatus register chann_enb bit is clear. this field is updated at the end of the address phase of the current access to the ahb bus. it is incrementing of the access byte width. the access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary. the packet start address is either the channel start addres s or the next channel address to be accessed in the channel buffer. the packet end address is either the channel end address or the latest channel address accessed in the channel buffer. the channel start address is written by software or loaded fr om the descriptor, whereas the channel end address is either determined by the end of buffer or the udphs device, usb end of transfer if th e udphs_dmacontrolx register end_tr_en bit is set. 31 30 29 28 27 26 25 24 buff_add 23 22 21 20 19 18 17 16 buff_add 15 14 13 12 11 10 9 8 buff_add 76543210 buff_add
736 32003e?avr32?05/06 at32ap7000 32.6.27 udphs dma channelx control register name: udphs_dmacontrolx access type: read/write ? chann_enb (channel enable command) 0 = dma channel is disabled at and no transfer will occur upon request. this bit is also cl eared by hardware when the chan- nel source bus is disabled at end of buffer. if the udphs_dmacontrol register ldnx t_dsc bit has been cleared by descript or loading, the fi rmware will have to set the corresponding chann_enb bit to start the described transfer, if needed. if the udphs_dmacontrol register ldnxt_dsc bit is cl eared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both udphs_dmastatus register chann_enb and chann_act flags read as 0. if a channel request is currently serviced when this bit is clear ed, the dma fifo buffer is drained until it is empty, then the udphs_dmastatus register chann_enb bit is cleared. if the ldnxt_dsc bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 1 = udphs_dmastatus register chann_enb bit will be set, thus enabling dma channel da ta transfer. then any pend- ing request will start the transfer. this may be used to start or resume any requested transfer. ? ldnxt_dsc: load next channel transfer descriptor enable (command) 0 = no channel register is loaded after the end of the channel transfer. 1 = the channel controller loads the next descriptor after the end of the current transfer, i.e. when the udphs_dmastatus/chann_enb bit is reset. if the udphs_dma control/chann_enb bit is cleared, the next descriptor is immediately loaded upon transfer request. dma channel control command summary 31 30 29 28 27 26 25 24 buff_length 23 22 21 20 19 18 17 16 buff_length 15 14 13 12 11 10 9 8 ???????? 76543210 burst_lck desc_ld_it end_buffit end_tr_it end_b_en end_tr_en ldnxt_dsc chann_enb ldnxt_dsc chann_enb description 0 0 stop now 0 1 run and stop at end of buffer 1 0 load next descriptor now 1 1 run and link at end of buffer
737 32003e?avr32?05/06 at32ap7000 ? end_tr_en: end of transfer enable (control) used for out transfers only. 0 = usb end of transfer is ignored. 1 = udphs device can put an end to the current buffer transfer. when set, a bulk or interrupt short packet or the last packet of an isoc hronous (micro) frame (datax) will close the current buffe r and the udphs_dmastatusx register end_tr_st flag will be raised. this is intended for udphs non-prenegotiated end of transfer (bulk or interrupt) or isochronous microframe data buffer closure. ? end_b_en: end of buffer enable (control) 0 = dma buffer end has no impact on usb packet transfer. 1 = endpoint can validate the packet (according to the valu es programmed in the udphs_eptctlx register auto_valid and shrt_pckt fields) at dma buffer end, i.e. when the udphs_dmastatus register buff_count reaches 0. this is mainly for short packet in validation initiated by the dma reaching end of buffer, but could be used for out packet truncation (discarding of unwanted packet data) at the end of dma buffer. ? end_tr_it: end of transfer interrupt enable 0 = udphs device initiated buffer transfer completion will not trigger any interrupt at udphs_statusx/end_tr_st rising. 1 = an interrupt is sent after the buffer transfer is complete, if the udphs device has ended the buffer transfer. use when the receive size is unknown. ? end_buffit: end of buffer interrupt enable 0 = udphs_dma_statusx/ end_bf_st rising will not trigger any interrupt. 1 = an interrupt is generated when the udphs_dmastatusx register buff_count reaches zero. ? desc_ld_it: descriptor loaded interrupt enable 0 = udphs_dmastatusx/desc_ldst risi ng will not trigge r any interrupt. 1 = an interrupt is generated when a descriptor has been loaded from the bus. ? burst_lck: burst lock enable 0 = the dma never locks bus access. 1 = usb packets ahb data bursts are locked for maximum opt imization of the bus bandwidth usage and maximization of fly-by ahb burst duration. ? buff_length: buffer byte length (write-only) this field determines the number of bytes to be transferred until end of buffer. the maximum channel transfer size (64 kb) is reached when this field is 0 (default value). if the transfer size is unknown, this field s hould be set to 0, but the transf er end may occur earlier under udphs device control. when this field is written, the udphs_dmastatusx regi ster buff_count field is updated with the write value. note: bits [31:2] are only writable when issuin g a channel control command other than ?stop now?. note: for reliability it is highly recommended to wait for bo th udphs_dmastatusx register chan_act and chan_enb flags are at 0, thus ensuring the channel has been stopp ed before issuing a command other than ?stop now?.
738 32003e?avr32?05/06 at32ap7000 32.6.28 udphs dma channelx status register name: udphs_dmastatusx access type: read/write ? chann_enb: channel enable status 0 = if cleared, the dma channel no longer transfers data, and may load the next descriptor if the udphs_dmacontrolx register ldnxt_dsc bit is set. when any transfer is ended either due to an elapsed byte count or a udphs device initiated transfer end, this bit is auto- matically reset. 1 = if set, the dma channel is currently enabled and transfers data upon request. this bit is normally set or cleared by writing into the udphs_dmacontrolx regist er chann_enb bit field either by soft- ware or descriptor loading. if a channel request is currently serviced when the udphs_ dmacontrolx register chan n_enb bit is cleared, the dma fifo buffer is drained until it is empty, then this status bit is cleared. ? chann_act: channel active status 0 = the dma channel is no longer trying to source the packet data. when a packet transfer is ended this bit is automatically reset. 1 = the dma channel is currently trying to source packet da ta, i.e. selected as the highest-priority requesting channel. when a packet transfer cannot be completed due to an end_bf_st, this flag stays set during the next channel descriptor load (if any) and potentially until udphs packet transfer completion, if allowed by the new descriptor. ? end_tr_st: end of channel transfer status 0 = cleared automatically when read by software. 1 = set by hardware when the last packet transfer is complete, if the udphs device has ended the transfer. valid until the chann_enb flag is cleared at the end of the next buffer transfer. ? end_bf_st: end of channel buffer status 0 = cleared automatically when read by software. 1 = set by hardware when the buff_count downcount reach zero. valid until the chann_enb flag is cleared at the end of the next buffer transfer. 31 30 29 28 27 26 25 24 buff_count 23 22 21 20 19 18 17 16 buff_count 15 14 13 12 11 10 9 8 ???????? 76543210 ? desc_ldst end_bf_st end_tr_st ? ? chann_act chann_enb
739 32003e?avr32?05/06 at32ap7000 ? desc_ldst: descriptor loaded status 0 = cleared automatically when read by software. 1 = set by hardware when a descriptor has been loaded from the system bus. valid until the chann_enb flag is cleared at the end of the next buffer transfer. ? buff_count: buffer byte count this field determines the current number of bytes still to be transfer red for this buffer. this field is decremented from the ahb source bus access byte width at the end of this bus address phase. the access byte width is 4 by default, or less, at dma start or end, if the start or end address is not aligned on a word boundary. at the end of buffer, the dma accesses the udphs device only for the number of bytes needed to complete it. this field value is reliable (stable) only if the c hannel has been stopped or frozen (udphs_eptctlx register nt_dis_dma bit is used to disable the channel request) a nd the channel is no longer active chann_act flag is 0. note: for out endpoints, if the receive buffer byte length (b uff_length) has been defaulted to zero because the usb transfer length is unknown, the actual buffer by te length received will be 0x10000-buff_count.
740 32003e?avr32?05/06 at32ap7000 33. timer/counter (tc) rev: 6082a 33.1 features ? three 16-bit timer counter channels ? a wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities ? each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? internal interrupt signal ? two global registers that act on all three tc channels 33.2 description the timer counter (tc) includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal inter- rupt signal which can be programmed to generate processor interrupts. the timer counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained.
741 32003e?avr32?05/06 at32ap7000 33.3 block diagram figure 33-1. timer counter block diagram table 33-1. signal name description block/channel sign al name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output sync synchronization input signal timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1
742 32003e?avr32?05/06 at32ap7000 33.4 pin name list 33.5 product dependencies 33.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 33.5.2 power management the timer counter clock is generated by the power manager. before using the tc, the program- mer must ensure that the tc clock is enabled in the power manager. 33.5.3 interrupt the tc has an interrupt line connected to the interrupt controller. handling the tc interrupt requires programming the interrupt controller before configuring the tc. 33.6 functional description 33.6.1 tc description the three channels of the timer counter are independent and identical in operation. the regis- ters for channel programming are listed in table 33-4 on page 755 . 33.6.1.1 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and th e covfs bit in sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 33.6.1.2 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to the configurable i/o signals tioa0, tioa1 or tioa2 for chaining by programming the bmr (block mode). see figure 33-2 . each channel can independently select an internal or external clock source for its counter: table 33-2. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o
743 32003e?avr32?05/06 at32ap7000 ? internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5. the peripherals chapter details the connection of these clock sources. ? external clock signals: xc0, xc1 or xc2. the peripherals chapter details the connection of these clock sources. this selection is made by the tcclks bits in the tc channel mode register . the selected clock can be inverted with the clki bit in cmr. this allows counting on the oppo- site edges of the clock. the burst function allows the clock to be validat ed when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). note: in all cases, if an external clock is used, the du ration of each of its leve ls must be longer than the master clock period. the external clock frequen cy must be at least 2.5 times lower than the mas- ter clock figure 33-2. clock selection 33.6.1.3 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 33-3 . ? the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock
744 32003e?avr32?05/06 at32ap7000 (ldbstop = 1 in cmr) or a rc compare event in waveform mode (cpcstop = 1 in cmr). the start and the stop commands have effect only if the clock is enabled. figure 33-3. clock control 33.6.1.4 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode is prog rammed with the wave bit in th e tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 33.6.1.5 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: ? software trigger: each channel has a software trigger, available by setting swtrg in ccr. ? sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing bcr (block control) with sync set. ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc val ue if cpctrg is set in cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in cmr. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
745 32003e?avr32?05/06 at32ap7000 if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.6.2 capture operating mode this mode is entered by clearing the wave parameter in cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob sig nals which are considered as inputs. figure 33-4 shows the configuration of the tc channel when programmed in capture mode. 33.6.2.1 capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a progr ammable event occurs on the signal tioa. the ldra parameter in cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in sr (status register). in this case, the old value is overwritten. 33.6.2.2 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trig- ger can be defined. the abetrg bit in cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the ed ge (rising, falling or both) det ected to genera te an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
746 32003e?avr32?05/06 at32ap7000 figure 33-4. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
747 32003e?avr32?05/06 at32ap7000 33.6.3 waveform operating mode waveform operating mode is entered by setting the wave pa rameter in cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same fre- quency and independently programmable duty cycles , or generates differe nt types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in cmr). figure 33-5 shows the configuration of the tc channel when programmed in waveform operat- ing mode. 33.6.3.1 waveform selection depending on the wavsel parameter in cmr (channel mode register), the behavior of cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
748 32003e?avr32?05/06 at32ap7000 figure 33-5. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel
749 32003e?avr32?05/06 at32ap7000 33.6.3.2 wavsel = 00 when wavsel = 00, the value of cv is increm ented from 0 to 0xffff. once 0xffff has been reached, the value of cv is reset. incrementation of cv starts again and the cycle continues. see figure 33-6 . an external event trigger or a software trigger can reset the value of cv. it is important to note that the trigger may occur at any time. see figure 33-7 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in cmr) and/or disable the counter clock (cpcdis = 1 in cmr). figure 33-6. wavsel= 00 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples
750 32003e?avr32?05/06 at32ap7000 figure 33-7. wavsel= 00 with trigger 33.6.3.3 wavsel = 10 when wavsel = 10, the value of cv is incremented from 0 to the value of rc, then automati- cally reset on a rc compare. once the value of cv has been reset, it is then incremented and so on. see figure 33-8 . it is important to note that cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 33-9 . in addition, rc compare can stop the counter clock (cpcstop = 1 in cmr) and/or disable the counter clock (cpcdis = 1 in cmr). figure 33-8. wavsel = 10 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples
751 32003e?avr32?05/06 at32ap7000 figure 33-9. wavsel = 10 with trigger 33.6.3.4 wavsel = 01 when wavsel = 01, the value of cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 33-10 . a trigger such as an external event or a software trigger can modify cv at any time. if a trigger occurs while cv is incr ementing, cv then decrements. if a trig ger is received while cv is decre- menting, cv then increments. see figure 33-11 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
752 32003e?avr32?05/06 at32ap7000 figure 33-10. wavsel = 01 without trigger figure 33-11. wavsel = 01 with trigger 33.6.3.5 wavsel = 11 when wavsel = 11, the value of cv is incremented from 0 to rc. once rc is reached, the value of cv is decremented to 0, then re-incremented to rc and so on. see figure 33-12 . a trigger such as an external event or a software trigger can modify cv at any time. if a trigger occurs while cv is incr ementing, cv then decrements. if a trig ger is received while cv is decre- menting, cv then increments. see figure 33-13 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpc- dis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
753 32003e?avr32?05/06 at32ap7000 figure 33-12. wavsel = 11 without trigger figure 33-13. wavsel = 11 with trigger 33.6.3.6 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the parameter eevt parameter in cmr selects the external tr igger. the eevtedg parameter defines the trigger edge for each of the possible external trig gers (rising, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used asan output and the tc channel can only generate a waveform on tioa. time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
754 32003e?avr32?05/06 at32ap7000 when an external event is defined, it can be used as a trigger by setting bit enetrg in cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 33.6.3.7 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in cmr.
755 32003e?avr32?05/06 at32ap7000 33.7 timer counter (tc) user interface bcr (block control register) and bmr (block mode register) control the whole tc block. tc channels are controlled by the registers listed in table 33-4 . the offset of each of the channel registers in table 33-4 is in relation to the offset of the corresponding channel as mentioned in table 33-4 . notes: 1. read only if wave = 0 table 33-3. tc global memory map offset channel/register name access reset value 0x00 tc channel 0 see table 33-4 0x40 tc channel 1 see table 33-4 0x80 tc channel 2 see table 33-4 0xc0 tc block control register bcr write-only ? 0xc4 tc block mode register bmr read/write 0 table 33-4. tc channel memory map offset register name access reset value 0x00 channel control register ccr write-only ? 0x04 channel mode register cmr read/write 0 0x08 reserved ? 0x0c reserved ? 0x10 counter value cv read-only 0 0x14 register a ra read/write (1) 0 0x18 register b rb read/write (1) 0 0x1c register c rc read/write 0 0x20 status register sr read-only 0 0x24 interrupt enable register ier write-only ? 0x28 interrupt disable register idr write-only ? 0x2c interrupt mask register imr read-only 0
756 32003e?avr32?05/06 at32ap7000 33.7.1 tc block control register register name: bcr access type: write-only ? sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync
757 32003e?avr32?05/06 at32ap7000 33.7.2 tc block mode register register name: bmr access type: read/write ? tc0xc0s: external clock signal 0 selection ? tc1xc1s: external clock signal 1 selection ? tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tc1xc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2 tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1
758 32003e?avr32?05/06 at32ap7000 33.7.3 tc channel control register register name: ccr access type: write-only ? clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. ? clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. ? swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????swtrgclkdisclken
759 32003e?avr32?05/06 at32ap7000 33.7.4 tc channel mode register: capture mode register name: cmr access type: read/write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. ? ldbdis: counter clock disable with rb loading 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave = 0 cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 000timer_clock1 001timer_clock2 010timer_clock3 011timer_clock4 100timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
760 32003e?avr32?05/06 at32ap7000 0 = counter clock is not disabl ed when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. ? etrgedg: external trigger edge selection ? abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. ? cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. ?wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ? ldra: ra loading selection ? ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
761 32003e?avr32?05/06 at32ap7000 33.7.5 tc channel mode register: waveform mode register name: cmr access type: read/write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. ? cpcdis: counter clock disable with rc compare 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave = 1 wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 000timer_clock1 001timer_clock2 010timer_clock3 011timer_clock4 100timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
762 32003e?avr32?05/06 at32ap7000 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. ? eevtedg: external ev ent edge selection ? eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms . ? enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. ? wavsel: waveform selection ? wave = 1 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as exte rnal event tiob direction 0 0 tiob input (1) 0 1 xc0 output 1 0 xc1 output 1 1 xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automa tic trigger on rc compare 0 1 updown mode without automatic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare
763 32003e?avr32?05/06 at32ap7000 ? acpa: ra compare effect on tioa ? acpc: rc compare effect on tioa ? aeevt: external event effect on tioa ? aswtrg: software trigger effect on tioa ? bcpb: rb compare effect on tiob acpa effect 0 0 none 0 1 set 1 0 clear 1 1 toggle acpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aeevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 0 0 none
764 32003e?avr32?05/06 at32ap7000 ? bcpc: rc compare effect on tiob ? beevt: external event effect on tiob ? bswtrg: software trigger effect on tiob 0 1 set 1 0 clear 1 1 toggle bcpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle beevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect
765 32003e?avr32?05/06 at32ap7000 33.7.6 tc counter value register register name: cv access type: read-only ? cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv
766 32003e?avr32?05/06 at32ap7000 33.7.7 tc register a register name: ra access type: read-only if wave = 0, read/write if wave = 1 ? ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra
767 32003e?avr32?05/06 at32ap7000 33.7.8 tc register b register name: rb access type: read-only if wave = 0, read/write if wave = 1 ? rb: register b rb contains the register b value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb
768 32003e?avr32?05/06 at32ap7000 33.7.9 tc register c register name: rc access type: read/write ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc
769 32003e?avr32?05/06 at32ap7000 33.7.10 tc status register register name: sr access type: read-only ? covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. ? lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. ? cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. ? cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. ? cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ? ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ? ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. ? etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. ? clksta: clock enabling status 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
770 32003e?avr32?05/06 at32ap7000 0 = clock is disabled. 1 = clock is enabled. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mean s that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. ? mtiob: tiob mirror 0 = tiob is low. if wave = 0, this mean s that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high.
771 32003e?avr32?05/06 at32ap7000 33.7.11 tc interrupt enable register register name: ier access type: write-only ? covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. ? cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. ? cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. ? cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ? ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. ? etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
772 32003e?avr32?05/06 at32ap7000 33.7.12 tc interrupt disable register register name: idr access type: write-only ? covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = disables the load overru n interrupt (if wave = 0). ? cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). ? cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). ? cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ? ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). ? etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
773 32003e?avr32?05/06 at32ap7000 33.7.13 tc interrupt mask register register name: imr access type: read-only ? covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. ? lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. ? cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. ? cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. ? cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ? ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ? ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. ? etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
774 32003e?avr32?05/06 at32ap7000 34. pulse width modulation controller (pwm) rev: 6044d 34.1 features ? 4 channels ? one 20-bit counter per channel ? common clock generator providin g thirteen different clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? independent channels ? independent enable disable command for each channel ? independent clock selection for each channel ? independent period and duty cycle for each channel ? double buffering of period or duty cycle for each channel ? programmable selection of the output waveform polarity for each channel ? programmable center or left aligne d output waveform for each channel 34.2 description the pwm macrocell controls several cha nnels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the cloc k generator provides several clocks resulting from the division of the pwm macrocell master clock. all pwm macrocell accesses are made through apb mapped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
775 32003e?avr32?05/06 at32ap7000 34.3 block diagram figure 34-1. pulse width modulation controller block diagram 34.4 i/o lines description each channel outputs one waveform on one external i/o line. pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio interrupt controller power manager mck clock generator apb interface interrupt generator clock selector period comparator update duty cycle counter clock selector period comparator pwm0 pwm0 table 34-1. i/o line description name description type pwmx pwm waveform output for channel x output
776 32003e?avr32?05/06 at32ap7000 34.5 product dependencies 34.5.1 i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desire d pwm pins to their peripheral function. if i/o lines of the pwm are not used by the applicati on, they can be used for other purposes by the pio controller. not all pwm outputs may be enabled. if an application requires only four channels, then only four pio lines will be as signed to pwm outputs. 34.5.2 power management the pwm clock is generated by the power manager. before using the pwm, the programmer must ensure that the twi clock is enabled in the power manager. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this ca se, the pwm will resume its oper ations where it left off. in the pwm description, master clock (mck) is the apb-bus clock, to which the pwm is connected. 34.5.3 interrupt sources the pwm interrupt line is connected to the interrupt controller. using the pwm interrupt requires the interrupt controller to be programmed first.
777 32003e?avr32?05/06 at32ap7000 34.6 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. ? clocked by the system clock, mck, the clock generator module provides 13 clocks. ? each channel can independently choose one of the clock generator outputs. ? each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 34.6.1 pwm clock generator figure 34-2. functional view of the clock generator block diagram caution: before using the pwm macrocell, the programmer must ensure that the pwm clock in the power manager is enabled. the pwm macrocell master clock, mck, is divide d in the clock generator module to provide dif- ferent clocks available for all channels. each channel can independently select one of the divided clocks. modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
778 32003e?avr32?05/06 at32ap7000 the clock generator is divided in three blocks: ? a modulo n counter whic h provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 ? two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clka and clkb each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made ac cording to the prea (preb) field of the pwm mode register (mr). the resulting clock clka (clk b) is the clock selected divided by diva (divb) field value in the pwm mode register (mr). after a reset of the pwm controller, diva (divb) and prea (preb) in the pwm mode register are set to 0. this implies that after reset clka (clkb) are turned off. at reset, all clocks provided by the modulo n counter are turned off except clock ?clk?. this situa- tion is also true when the pwm master cl ock is turned off through the power management controller. 34.6.2 pwm channel 34.6.2.1 block diagram figure 34-3. functional view of the channel block diagram each of the 4 channels is composed of three blocks: ? a clock selector which selects one of the clocks provided by the clock generator described in section 34.6.1 ?pwm clock generator? on page 777 . ? an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and comparators events. the size of the internal counter is 20 bits. ? a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. 34.6.2.2 waveform properties the different properties of output waveforms are: ? the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this channel parameter is defined in the cpre field of the cmrx register. this field is reset at 0. ? the waveform period . this channel parameter is defined in the cprd field of the cprdx register. comparator pwmx output waveform internal counter clock selector inputs from clock generator inputs from apb bus channel
779 32003e?avr32?05/06 at32ap7000 - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32 , 64, 128, 256, 512, or 1024), the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024 ). the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or ? the waveform duty cycle . this channel parameter is defined in the cdty field of the cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: ? the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of t he cmrx register. by default the signal starts by a low level. ? the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the cmrx register. the default mode is left aligned. xcprd () mck ------------------------------- crpd diva () mck ------------------------------------------ crpd divab () mck ---------------------------------------------- 2 x cprd () mck ---------------------------------------- - 2 cprd diva () mck --------------------------------------------------- - 2 cprd divb () mck --------------------------------------------------- - duty cycle period 1 fchannel_x_clock cdty ? ? () period ------------------------------------------------------------------------------------------------------- - = duty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? ()) period 2 ? () ---------------------------------------------------------------------------------------------------------------------- - =
780 32003e?avr32?05/06 at32ap7000 figure 34-4. non overlapped center aligned waveforms note: 1. see figure 34-5 on page 781 for a detailed description of center aligned waveforms. when center aligned, the internal channel count er increases up to cprd and.decreases down to 0. this ends the period. when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a ce nter aligned channel is twice the period for a left aligned channel. waveforms are fixed at 0 when: ? cdty = cprd and cpol = 0 ? cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: ? cdty = 0 and cpol = 0 ? cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the channel. this immediately affects the channel output level. changes on channel polari ty are not taken into account while the channel is enabled. pwm0 pwm1 period no overlap
781 32003e?avr32?05/06 at32ap7000 figure 34-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
782 32003e?avr32?05/06 at32ap7000 34.6.3 pwm controller operations 34.6.3.1 initialization before enabling the output channel, this chann el must have been configured by the software application: ? configuration of the clock generator if diva and divb are required ? selection of the clock for each channel (cpre field in the cmrx register) ? configuration of the waveform alignment for each channel (calg field in the cmrx register) ? configuration of the period for each channel (cprd in the cprdx register). writing in cprdx register is possible while the channel is disabl ed. after validation of the channel, the user must use cupdx register to update cprdx as explained below. ? configuration of the duty cycle fo r each channel (cdty in the cdtyx register). writing in cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use cupdx register to update cdtyx as explained below. ? configuration of the output waveform polarity for each channel (cpol in the cmrx register) ? enable interrupts (writing chidx in the ier register) ? enable the pwm channel (writing chidx in the ena register) it is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several chi dx bits in the ena register. in such a situation, all channels may have the same clock selector configuration and the same period specified. 34.6.3.2 source clock selection criteria the large number of source clocks can make selection difficult. the relationship between the value in the period register (cprdx) and the duty cycle register (cdtyx) can help the user in choosing. the event number written in the period register gives the pwm accuracy. the duty cycle quantum cannot be lower than 1/cprdx value. the higher the value of cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in cprdx, the user is able to set a value between 1 up to 14 in cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. 34.6.3.3 changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, cprdx and cdtyx regist ers are double buffered. the user can write a new period value or duty cycle value in the update register (cupdx). this register holds the new value until the end of the curren t cycle and updates the value for th e next cycle. according to the cpd field in the cmrx register, cupd x either updates the cprdx or cdtyx.
783 32003e?avr32?05/06 at32ap7000 figure 34-6. synchronized period or duty cycle update to prevent overwriting the cupdx by software, t he user can use status events in order to syn- chronize his software. two methods are possible. in both, the user must enable the dedicated interrupt in ier at pwm controller level. the first method (polling method) consists of r eading the relevant status bit in isr register according to the enabled channel(s). see figure 34-7 . the second method uses an interrupt service routine associated with the pwm channel. note: reading the isr register automatically clears chidx flags. figure 34-7. polling method note: polarity and alignment can be modified only when the channel is disabled. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
784 32003e?avr32?05/06 at32ap7000 34.6.3.4 interrupts depending on the interrupt mask in the imr register, an interrupt is generated at the end of the corresponding channel period. the interrupt remains active until a read operation in the isr reg- ister occurs. a channel interrupt is enabled by setting the corresponding bit in the ier register. a channel interrupt is disabled by setting the corresponding bit in the idr register.
785 32003e?avr32?05/06 at32ap7000 34.7 user interface 34.7.1 register mapping table 34-2. pwm controller registers offset register name access peripheral reset value 0x00 pwm mode register mr read/write 0 0x04 pwm enable register ena write-only - 0x08 pwm disable register dis write-only - 0x0c pwm status register sr read-only 0 0x10 pwm interrupt enable register ier write-only - 0x14 pwm interrupt disable register idr write-only - 0x18 pwm interrupt mask register imr read-only 0 0x1c pwm interrupt status register isr read-only 0 0x4c - 0xf8 reserved ? ? ? 0x4c - 0xfc reserved ? ? ? 0x100 - 0x1fc reserved 0x200 channel 0 mode register cmr0 read/write 0x0 0x204 channel 0 duty cycle register cdty0 read/write 0x0 0x208 channel 0 period register cprd0 read/write 0x0 0x20c channel 0 counter register ccnt0 read-only 0x0 0x210 channel 0 update register cupd0 write-only - ... reserved 0x220 channel 1 mode register cmr1 read/write 0x0 0x224 channel 1 duty cycle register cdty1 read/write 0x0 0x228 channel 1 period register cprd1 read/write 0x0 0x22c channel 1 counter register ccnt1 read-only 0x0 0x230 channel 1 update register cupd1 write-only - ... ... ... ... ...
786 32003e?avr32?05/06 at32ap7000 34.7.2 pwm mode register register name: mr access type: read/write ? diva, divb: clka, clkb divide factor ? prea, preb 31 30 29 28 27 26 25 24 ???? preb 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ???? prea 76543210 diva diva, divb clka, clkb 0 clka, clkb clock is turned off 1 clka, clkb clock is clock selected by prea, preb 2-255 clka, clkb clock is clock selected by prea, preb divided by diva, divb factor. prea, preb divider input clock 0000mck. 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1010mck/ 1024 other reserved
787 32003e?avr32?05/06 at32ap7000 34.7.3 pwm enable register register name: ena access type: write-only ? chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
788 32003e?avr32?05/06 at32ap7000 34.7.4 pwm disable register register name: dis access type: write-only ? chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
789 32003e?avr32?05/06 at32ap7000 34.7.5 pwm status register register name: sr access type: read-only ? chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
790 32003e?avr32?05/06 at32ap7000 34.7.6 pwm interrupt enable register register name: ier access type: write-only ? chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
791 32003e?avr32?05/06 at32ap7000 34.7.7 pwm interrupt disable register register name: idr access type: write-only ? chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
792 32003e?avr32?05/06 at32ap7000 34.7.8 pwm interrupt mask register register name: imr access type: read-only ? chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
793 32003e?avr32?05/06 at32ap7000 34.7.9 pwm interrupt status register register name: isr access type: read-only ? chidx: channel id 0 = no new channel period since the last read of the isr register. 1 = at least one new channel period since the last read of the isr register. note: reading isr automatically clears chidx flags. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
794 32003e?avr32?05/06 at32ap7000 34.7.10 pwm channel mode register register name: cmrx access type: read/write ? cpre: channel pre-scaler ? calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. ? cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????cpdcpolcalg 76543210 ???? cpre cpre channel pre-scaler 0000mck 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1 0 1 0 mck/1024 1011clka 1100clkb other reserved
795 32003e?avr32?05/06 at32ap7000 ? cpd: channel update period 0 = writing to the cupdx will modify the duty cycle at the next period start event. 1 = writing to the cupdx will modify the period at the next period start event.
796 32003e?avr32?05/06 at32ap7000 34.7.11 pwm channel duty cycle register register name: cdty x access type: read/write only the first 20 bits (internal ch annel counter size) are significant. ? cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty
797 32003e?avr32?05/06 at32ap7000 34.7.12 pwm channel period register register name: cprdx access type: read/write only the first 20 bits (internal ch annel counter size) are significant. ? cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resultin g period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resultin g period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd xcprd () mck ------------------------------- crpd diva () mck ------------------------------------------ crpd divab () mck ---------------------------------------------- 2 x cprd () mck ---------------------------------------- - 2 cprd diva () mck --------------------------------------------------- - 2 cprd divb () mck --------------------------------------------------- -
798 32003e?avr32?05/06 at32ap7000 34.7.13 pwm channel counter register register name: ccntx access type: read-only ? cnt: channel counter register internal counter value. this register is reset when: ? the channel is enabled (writing chidx in the ena register). ? the counter reaches cprd value defined in the cp rdx register if the wa veform is left aligned. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt
799 32003e?avr32?05/06 at32ap7000 34.7.14 pwm channel update register register name: cupdx access type: write-only this register acts as a double buffer for the period or the duty cycle. this prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. only the first 20 bits (internal chan nel counter size) are significant. 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd cpd (cmrx register) 0 the duty-cycle (cdtc in the cdrx register) is u pdated with the cupd value at the beginning of the next period. 1 the period (cprd in the cprx register) is upd ated with the cupd value at the beginning of the next period.
800 32003e?avr32?05/06 at32ap7000 35. lcd controller (lcdc) rev: 6063d 35.1 features ? stn panel features ? single and dual scan color and monochrome lcd panels ? 4-bit single scan, 8-bit single or du al scan, 16-bit dual scan interfaces ? up to 16 gray levels for monochrome and up to 4096 colors for color panel ? 1 or 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for monochrome ? 1, 2, 4 or 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color stn display ? tft panel features ? single scan active tft lcd panel ? up to 24-bit single scan interfaces ? 1, 2, 4 or 8 bits per pixel (palletized) , 16 or 24 bits per pixel (non-palletized) ? common features ? configurable screen si ze up to 2048 x 2048 ? dma controller for reading the disp lay data from an external memory ? 2k bytes input fif0 ? 2d frame buffer addressing allowing movement in an image larger than the screen size 35.2 description the lcd controller consists of logic for trans ferring lcd image data from an external display buffer to an lcd module with integrated common and segment drivers. the lcd controller supports single and double scan monochrome and color passive stn lcd modules and single scan active tft lcd modules. on monochrome stn displays, up to 16 gray shades are supported using a time-based dithering algorithm and frame rate control (frc) method. this method is also used in colo r stn displays to generate up to 4096 colors. the lcd controller has a display input buffer (fifo) to allow a flexible connection of the exter- nal ahb master interface, and a lookup table to allow palletized display configurations. the lcd controller is programmable in order to support many different requirements such as resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing. the lcd controller is connected to the advanced high performance bus (ahb) as a master for reading pixel data. however, th e lcd controller interfaces with the ahb as a slave in order to configure its registers.
801 32003e?avr32?05/06 at32ap7000 35.3 block diagram figure 35-1. lcd macrocell block diagram timegen pwm display cfg ch-l ahb if ch-u ctrl cfg ahb slave display if ahb master split lut mem fifo mem dma controller lcd controller core configuration if control interface lower push fifo serializer palette dithering output shifter ahb slave ahb slave input interface upper push dma data lcdd display if control signals dvalid dvalid ahb clock domain lcdc core clock domain lut mem interface fifo mem interface lut mem interface data pat h
802 32003e?avr32?05/06 at32ap7000 35.4 i/o lines description 35.5 product dependencies 35.5.1 i/o lines the pins used for interfacing the lcd controller may be multiplexed with pio lines. the pro- grammer must first program the pio controller to assign the pins to their peripheral function. if i/o lines of the lcd controller are not used by the application, they can be used for other pur- poses by the pio controller. 35.5.2 power management the lcd clock is generated by the power manager. before using the lcd, the programmer must ensure that the twi clock is enabled in the power manager. 35.5.3 interrupt sources the lcd interface has an interrupt line connected to the interrupt controller. in order to handle interrupts, the interrupt controller must be programmed before configuring the lcd. table 35-1. i/o lines description name description type cc contrast control signal output hsync line synchronous signal (stn) or horizontal synchronous signal (tft) output pclk lcd clock signal (stn/tft) output vsync frame synchronous signal (stn) or ve rtical synchronizati on signal (tft) output dval stn ac bias signal for the driver or data enable signal (tft) output mod lcd modulation signal output pwr lcd panel power enable control signal output gp[7:0] lcd general purpose lines output lcdd[23:0] lcd data bus output output
803 32003e?avr32?05/06 at32ap7000 35.6 functional description the lcd controller consists of two main blocks ( figure 35-1 on page 801 ), the dma controller and the lcd controller core (lcdc core). the dma controller reads the display data from an external memory through a ahb master interface. the lcd controller core formats the display data. the lcd controller core continuously pumps the pixel data into the lcd module via the lcd data bus (lcdd[23:0]); this bus is timed by the pclk, dval, hsync, and vsync signals. 35.6.1 dma controller 35.6.1.1 configuration block the configuration block is a set of programmable registers that are used to configure the dma controller operation. these registers are written vi a the ahb slave interface. only word access is allowed. for details on the configuration registers, see ?lcd controller (lcdc) user interface? on page 831 . 35.6.1.2 ahb interface this block generates the ahb transactions. it generates undefined-length incrementing bursts as well as 4- ,8- or 16-beat incrementing bursts. the size of the transfer can be configured in the brstln field of the dmafrmcfg register. for details on this register, see ?dma frame con- figuration register? on page 839 . 35.6.1.3 channel-u this block stores the base address and the number of words transferred for this channel (frame in single scan mode and upper panel in dual scan mode) since the beginning of the frame. it also generates the end of frame signal. it has two pointers, the base address and the number of words to transfer. when the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. when the module receives the new_frame signal, it also reloads the base address with the base address programmed by the host. the size of the frame/panel can be programmed in the frmsize field of the dmafrmcfg register. this size is calculated as follows: ? in tft mode: ? in stn monochrome mode: frame_size display_size bpp 32 -------------------------------------------------- = frame_size lineval 1 + () hozval 1 + () e_ifwidth bpp 32 ------------------------------------------------------------------------------------------------------------------------------- ---- =
804 32003e?avr32?05/06 at32ap7000 ? in stn color mode: where: ? lineval is the value of the lineval field of the lcdfrmcfg register of lcd controller ? hozval is the value of the hozval field of the lcdfrmcfg register of the lcd controller ? e_ifwidth is the number of data bits in the lcd interface for each panel ? bpp is the bits per pixel configuration x_size = ((linesize +1)*bpp+pixeloff)/32 y_size = (lineval+1) ? linesize is the horizontal size of the display in pixels, minus 1, as programmed in the linesize field of the lcdfrmcfg register of the lcd controller. ?bpp is the number of bits per pixel configured. ?pixeloff is the pixel offset for 2d addressing, as programmed in the dma2dcfg register. applicable only if 2d addressing is being used. ? lineval is the vertical size of the display in pixels, minus 1, as programmed in the lineval field of the lcdfrmcfg register of the lcd controller. note: x_size is calculated as an up-rounding of a division by 32. (this can also be done adding 31 to the dividend before using an integer division by 32). when using the 2d-addressing mode (see ?2d memory addressing? on page 827 ), it is important to note that the above calculation must be exe- cuted and the frmsize field programmed with ever y movement of the displaying window, since a change in the pixeloff field can change the resulting frmsize value. 35.6.1.4 channel-l this block has the same functionality as channel- u, but for the lower panel in dual scan mode only. 35.6.1.5 control this block receives the request signals from the lcdc core and generates the requests for the channels. frame_size lineval 1 + () hozval 1 + () e_ifwidth 3 -------------------------------------------------------------------- - ?? ?? bpp 32 ----------------------------------------------------------------------------------------------------------------------------- = frame_size x_size*y_size 32 ------------------------------------- - =
805 32003e?avr32?05/06 at32ap7000 35.6.2 lcd controller core 35.6.2.1 configuration block the configuration block is a set of programmable registers that are used to configure the lcdc core operation. these registers are written via the ahb slave interface. only word access is allowed. the description of the configuration registers can be found in ?lcd controller (lcdc) user interface? on page 831 . 35.6.2.2 datapath the datapath block contains five submodules: fif o, serializer, palette, dithering and shifter. the structure of the datapath is shown in figure 35-2 . figure 35-2. datapath structure this module transforms the data read from the memory into a format according to the lcd mod- ule used. it has four different interfaces: the input interface, the output interface, the configuration interface and the control interface. fifo serializer palette dithering output shifter input interface output interface configuration if control interface
806 32003e?avr32?05/06 at32ap7000 ? the input interface connects the datapath with the dma controller. it is a dual fifo interface with a data bus and two push lines that are used by the dma controller to fill the fifos. ? the output interface is a 24-bit data bus. the configuration of this interface depends on the type of lcd used (tft or stn, single or dual scan, 4-bit, 8-bit, 16-bit or 24-bit interface). ? the configuration interface connects the datapath with the configuration block. it is used to select between the different datapath configurations. ? the control interface connects the datapath with the timing generation block. the main control signal is the data-request signal, used by the timing generation module to request new data from the datapath. the datapath can be characterized by two parameters: initial_latency and cycles_per_data. the parameter initial_latency is defin ed as the number of lcdc core clock cycles until the first data is available at the output of the datapath. th e parameter cycles_per_data is the minimum num- ber of lcdc core clock cycles between two consecutive data at the output interface. these parameters are different for the different configurations of the lcd controller and are shown in table 35-2 . 35.6.2.3 fifo the fifo block buffers the input data read by the dma module. it contains two input fifos to be used in dual scan configuration that are configured as a single fifo when used in single scan configuration. the size of the fifos allows a wide range of architectures to be supported. the upper threshold of the fifos can be configured in the fifoth field of the lcdfifo regis- ter. the lcdc core will request a dm a transfer when the number of words in each fifo is less than fifoth words. to avoid overwriting in the fifo and to maximize the fifo utilization, the fifoth should be programmed with: where: ? fifo_effective_size is the effective size of the fifo. it is the total fifo memory size in single scan mode and half that size in dual scan mode. ? dma_burst_length is the burst length of the transfers made by the dma table 35-2. datapath parameters configuration initial_latency cycles_per_data distype scan ifwidth tft 9 1 stn mono single 4 13 4 stn mono single 8 17 8 stn mono dual 8 17 8 stn mono dual 16 25 16 stn color single 4 11 2 stn color single 8 12 3 stn color dual 8 14 4 stn color dual 16 15 6 fifoth fifo_effective_size 2 dma_burst_length 3 + () ? =
807 32003e?avr32?05/06 at32ap7000 35.6.2.4 serializer this block serializes the data read from memory. it reads words from the fifo and outputs pix- els (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the pixelsize field of the lcdcon2 register. it also adapts the memory-ordering format. both big- endian and little-endian formats are supported. they are configured in the memor field of the lcdcon2 register. the organization of the pixel data in the memory depends on the configur ation and is shown in table 35-3 and table 35-4 . note: for a color depth of 24 bits per pixel ther e are two different formats supported: packed and unpacked. the packed format needs less memory but has some limitations when working in 2d addressing mode ( see section ?35. 10? on page 827. ). table 35-3. little endian memory organization mem addr 0x3 0x2 0x1 0x0 bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 pixel 1bpp 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 pixel 2bpp 1514131211109876543210 pixel 4bpp 76543210 pixel 8bpp 3210 pixel 16bpp 10 pixel 24bpp 10 pixel 24bpp 21 pixel 24bpp 32 pixel 24bpp 54
808 32003e?avr32?05/06 at32ap7000 table 35-4. big endian memory organization mem addr 0x3 0x2 0x1 0x0 bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 pixel 1bpp 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 pixel 2bpp 0123456789101112131415 pixel 4bpp 01234567 pixel 8bpp 0123 pixel 16bpp 01 pixel 24bpp packed 01 pixel 24bpp packed 12 pixel 24bpp packed 23 pixel 24bpp packed 45 pixel 24bpp unpacke d not used 0
809 32003e?avr32?05/06 at32ap7000 35.6.2.5 palette this block is used to generate the pixel gray or color information in palletized configurations. the different modes with the palletized/non-palletized configuration can be found in table 35-6 . in these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. the corresponding entry in the lookup table contains the color or gray shade information for the pixel. the lookup table can be accessed by the host in r/w mode to allow the host to program and check the values stored in the palette. it is mapped in the lcd controller configuration memory table 35-5. wince pixel memory organization mem addr 0x3 0x2 0x1 0x0 bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 pixel 1bpp 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 89 1 0 1 1 1 2 1 3 1 4 1 5 01234567 pixel 2bpp 1213141589101145670123 pixel 4bpp 67452301 pixel 8bpp 3210 pixel 16bpp 10 pixel 24bpp packed 10 pixel 24bpp packed 21 pixel 24bpp packed 32 pixel 24bpp unpacke d not used 0 table 35-6. palette configurations configuration palette distype pixelsize tft 1, 2, 4, 8 palletized tft 16, 24 non-palletized stn mono 1, 2 palletized stn mono 4 non-palletized stn color 1, 2, 4, 8 palletized stn color 16 non-palletized
810 32003e?avr32?05/06 at32ap7000 map. the lut is mapped as 16-bit half-words aligned at word boundaries, only word write access is allowed (the 16 msb of the bus are not used). for the detailed memory map, see table 35-13 on page 831 . the lookup table contains 256 16 -bit wide entries. the 256 entries are chosen by the program- mer from the 2 16 possible combinations. for the structure of each lut entry, see table 35-7 . in stn monochrome, only the four most signifi cant bits of the red value are used (16 gray shades). in stn color, only the four most signi ficant bits of the blue, green and red value are used (4096 colors). in tft mode, all the bits in the blue, green and red values are used (32768 colors). in this mode, there is also a common intensity bit that can be used to double the possible colors. this bit is the least significant bit of each color component in the lcdd interface (lcdd[18], lcdd[10], lcdd[2]). the lcdd unused bits are tied to 0 when tft palletized configurations are used (lcdd[17:16], lcdd[ 9:8], lcdd[1:0]). 35.6.2.6 dithering the dithering block is used to generate the shades of gray or color when the lcd controller is used with an stn lcd module. it uses a time-based dithering algorithm and frame rate con- trol method. the frame rate control varies the duty cycle for which a given pixel is turned on, giving the dis- play an appearance of multiple shades. in order to reduce the flicker noise caused by turning on and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. this algorithm is expressed in terms of dithering pattern registers (dp_i) and considers not only the pixel gray level number, but also its horizontal coordinate. table 35-8 shows the correspondences between the gray levels and the duty cycle. table 35-7. lookup table structure in the memory address data output [15:0] 00 intensity_bit_0 blue_value_0[4:0] green_value_0[4:0] red_value_0[4:0] 01 intensity_bit_1 blue_value_1[4:0] green_value_1[4:0] red_value_1[4:0] ... fe intensity_bit_254 blue_value_254[4: 0] green_value_254[4:0] red_value_254[4:0] ff intensity_bit_255 blue_value_255[4: 0] green_value_255[4:0] red_value_255[4:0]
811 32003e?avr32?05/06 at32ap7000 the duty cycles for gray levels 0 and 15 are 0 and 1, respectively. the same dp_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). the dithering pattern for the first pair member is the inversion of the one for the second. the dp_i registers contain a series of 4-bit patterns. the (3-m) th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame. the operation is shown by the examples below. consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. the four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is dp3_5 =?1010 0101 1010 0101 1111?. the output sequence obtained in the data output for monochrome mode is shown in table 35-9 . table 35-8. dithering duty cycle gray level duty cycle pattern register 15 1 - 14 6/7 dp6_7 13 4/5 dp4_5 12 3/4 dp3_4 11 5/7 dp5_7 10 2/3 dp2_3 9 3/5 dp3_5 8 4/7 dp4_7 71/2~dp1_2 63/7~dp4_7 52/5~dp3_5 41/3~dp2_3 31/4~dp3_4 21/5~dp4_5 11/7~dp6_7 00-
812 32003e?avr32?05/06 at32ap7000 consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. a color pixel is composed of three components: {r, g, b}. pixel p0 will be dis- played sending the color components {r0, g0, b0 } to the display. pixe l p1 will be displayed sending the color components {r1, g1, b1}. suppose that the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color components of both pixels, with the dithering pattern to apply to all of them being dp2_3 = ?1101 1011 0110?. table 35-10 shows the output sequence in the data output bus for single scan configurations. (in dual scan configuration, each panel data bus acts like in the equivalent single scan configuration.) table 35-9. dithering algorithm for monochrome mode frame number pattern pixel a pixel b pixel c pixel d n 1010 on off on off n+1 0101 off on off on n+2 1010 on off on off n+3 0101 off on off on n+4 1111 on on on on n+5 1010 on off on off n+6 0101 off on off on n+7 1010 on off on off ... ... ... ... ... ... table 35-10. dithering algorithm for color mode frame signal shadow level bit used dithering pattern 4-bit lcdd 8-bit lcdd output n red_data_0 1010 3 1101 lcdd[3] lcdd[7] r0 n green_data_0 1010 2 1101 lcdd[2] lcdd[6] g0 n blue_data_0 1010 1 1101 lcdd[1] lcdd[5] b0 n red_data_1 1010 0 1101 lcdd[0] lcdd[4] r1 n green_data_1 1010 3 1101 lcdd[3] lcdd[3] g1 n blue_data_1 1010 2 1101 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? n+1 red_data_0 1010 3 1011 lcdd[3] lcdd[7] r0 n+1 green_data_0 1010 2 1011 lcdd[2] lcdd[6] g0 n+1 blue_data_0 1010 1 1011 lcdd[1] lcdd[5] b0 n+1 red_data_1 1010 0 1011 lcdd[0] lcdd[4] r1 n+1 green_data_1 1010 3 1011 lcdd[3] lcdd[3] g1 n+1 blue_data_1 1010 2 1011 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? n+2 red_data_0 1010 3 0110 lcdd[3] lcdd[7] r0 n+2 green_data_0 1010 2 0110 lcdd[2] lcdd[6] g0
813 32003e?avr32?05/06 at32ap7000 note: ri = red pixel component on. gi = green pixel component on. bi = blue pixel component on. ri = red pixel component off. gi = green pixel component off. bi = blue pixel component off. 35.6.2.7 shifter the fifo, serializer, palette and dithering modules process one pixel at a time in monochrome mode and three sub-pixels at a time in color mode (r,g,b components). this module packs the data according to the output interfac e. this interface can be programmed in the distype, scanmod, and ifwidth fields of the ldccon3 register. the distype field selects between tft, stn mo nochrome and stn color display. the scan- mode field selects between single and dual sc an modes; in tft mode, only single scan is supported. the ifwidth field configures the width of the interface in stn mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only). for a more detailed description of the fields, see ?lcd controller (lcdc) user interface? on page 831 . for a more detailed description of the lcd interface, see ?lcd interface? on page 819 . 35.6.2.8 timegen the time generator block ge nerates the c ontrol signals pclk, hsync, vsync, dval, and mode, used by the lcd module. this block is programmable in order to support different types of lcd modules and obtain the output clock signals, which are derived from the lcdc core clock. the mode signal provides an ac signal for the display. it is used by the lcd to alternate the polarity of the row and column voltages used to turn the pixels on and off. this prevents the liq- uid crystal from degradation. it can be configured to toggle every frame (bit mmode = 0 in lcdmval register) or to toggle every programmable number of hsync pulses (bit mmode = 1, number of pulses defined in mval field of lcdmval register). figure 35-3 and figure 35-4 on page 814 show the timing of mode in both configurations. n+2 blue_data_0 1010 1 0110 lcdd[1] lcdd[5] b0 n+2 red_data_1 1010 0 0110 lcdd[0] lcdd[4] r1 n+2 green_data_1 1010 3 0110 lcdd[3] lcdd[3] g1 n+2 blue_data_1 1010 2 0110 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? table 35-10. dithering algorithm for color mode (continued) frame signal shadow level bit used dithering pattern 4-bit lcdd 8-bit lcdd output f lcd_mode f lcd_hsync 2 mval 1 + () ---------------------------------------- =
814 32003e?avr32?05/06 at32ap7000 figure 35-3. full frame timing, mmode=1, mval=1 figure 35-4. full frame timing, mmode=0 the pclk signal is used to clock the data into the lcd drivers' shift register. the data is sent through lcdd[23:0] synchr onized by default with pclk falling ed ge (rising edge can be selected). the clkval field of lcdcon1 register controls the rate of this signal. the divisor can also be bypassed with the bypass bit in the lcdcon1 register. in this case , the rate of pclk is equal to the frequency of the lcdc core clock. t he minimum period of t he pclk signal depends on the configuration. this information can be found in table 35-11 . the pclk signal has two different timings that are selected with the clkmod field of the lcdcon2 register: ? always active (used with tft lcd modules) ? active only when data is ava ilable (used with stn lcd modules) table 35-11. minimum pclk period in lcdc core clock cycles configuration pclk period distype scan ifwidth tft 1 stn mono single 4 4 stn mono single 8 8 stn mono dual 8 8 stn mono dual 16 16 stn color single 4 2 lcd_vsync lcd_mode lcd_pclk line1 line2 line3 line4 line5 lcd_vsync lcd_mode lcd_pclk line1 line2 line3 line4 line5 f lcd_pclk f lcdc_clock 2 clkval -------------------------------- =
815 32003e?avr32?05/06 at32ap7000 the dval signal indicates valid data in the lcd interface. after each horizontal line of data has been shifted into the lcd, the hsync is asserted to cause the line to be displayed on the panel. the following timing parameters can be configured: ? vertical to horizontal delay (vhdly): the delay between begin_of_line and the generation of hsync is configurable in the vhdly field of the lcdtim1 register. the delay is equal to (vhdly+1) pclk cycles. ? horizontal pulse width (hpw): the hsync puls e width is configurable in hpw field of lcdtim2 register. the width is equal to (hpw + 1) pclk cycles. ? horizontal back porch (hbp): the delay between the hsync falling edge and the first pclk rising edge with valid data at the lcd interface is configurable in the hbp field of the lcdtim2 register. the delay is equal to (hbp+1) pclk cycles. ? horizontal front porch (hfp): the delay between end of valid data and the end of the line is configurable in the hfp field of the lcdtim2 register. the delay is equal to (hfp+1) pclk cycles. there is a limitation in the minimum values of vhdly, hpw and hbp parameters imposed by the initial latency of the datapath. the total de lay in lcdc clock cycles must be higher than or equal to the latency column in table 35-2 on page 806 . this limitation is given by the following formula: 35.6.2.9 equation 1 where: ? vhdly, hpw, hbp are the value of the fields of lcdtim1 and lcdtim2 registers ? pclk_period is the peri od of pclk signal meas ured in lcdc clock cycles ? dpath_latency is the datapath latency of the configuration, given in table 35-2 on page 806 the vsync is asserted once per fr ame. this signal is asserted to cause the lcd's line pointer to start over at the top of the display. the timing of this signal depends on the type of lcd: stn or tft lcd. in stn mode, the high phase corresponds to the complete first line of the frame. in stn mode, this signal is synchronized with the fi rst active pclk rising edge in a line. in tft mode, the high phase of this signal starts at the beginning of the first line. the following timing parameters can be selected: ? vertical pulse width (vpw): vsync pulse width is configurable in vpw field of the lcdtim1 register. the pulse width is equal to (vpw+1) lines. stn color single 8 2 stn color dual 8 4 stn color dual 16 6 table 35-11. minimum pclk period in lcdc core clock cycles (continued) configuration pclk period distype scan ifwidth vhdly hpw hbp 3 +++ () pclk_period dpath_latency
816 32003e?avr32?05/06 at32ap7000 ? vertical back porch: number of inactive lines at the beginning of the frame is configurable in vbp field of lcdtim1 register. the number of inactive lines is e qual to vbp. this field should be programmed with 0 in stn mode. ? vertical front porch: number of inactive lines at the end of the frame is configurable in vfp field of lcdtim2 register. the number of inactive lines is equal to vfp. this field should be programmed with 0 in stn mode. there are two other parameters to configure in this module, the hozval and the lineval fields of the lcdfrmcfg: ? hozval configures the number of active pclk cycles in each line. the number of active cycles in each line is equal to (hozval+1) cycles. the minimum value of this parameter is 1. ? lineval configures the number of active lines per frame. this number is equal to (lineval+1) lines. the minimum value of this parameter is 1. figure 35-5 , figure 35-6 and figure 35-7 show the timing of mode, pclk, dval, hsync and vsync signals: figure 35-5. stn panel timing, clkmod 0 lcd_hsync lcd_vsync lcd_mode lcd_dval lcd_pclk lcdd frame period vhdly+ hbp+1 hpw+1 hfp+1 hozval+1 lcd_pclk lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcd_vsync lcd_mode lcd_hsync lcd_dval
817 32003e?avr32?05/06 at32ap7000 figure 35-6. tft panel timing, clkmod = 0, vpw = 2, vbp = 2, vfp = 1 figure 35-7. tft panel timing (line expanded view), clkmod=1 usually the frm rate is about 70 hz to 75 hz. it is given by the following equation: where: ? hozval determines de number of pclk cycles per line ? lineval determines the number of hsync cycles per frame, according to the expressions shown below: in stn mode: vhdly+1 hbp+1 hpw+1 hfp+1 hozval+1 lcd_pclk lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcd_vsync lcd_hsync lcd_dval (vpw+1) lines lcd_vsync lcd_pclk lcdd lcd_dval vhdly+1 lcd_hsync vertical fron t porch = vfp lines vertical back porch = vbp lines frame period vhly+1 vbp+1 hpw+1 vfp+1 hozval+1 lcd_pclk lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcd_vsync lcd_hsync lcd_dval 1 f lcd_vsync ---------------------- vhdly hpw hbp hozval hfp 5 +++ ++ f lcd_pclk --------------------------------------------------------------------------------------------------------------------- ?? ?? vbp lineval vfp 1 +++ () = hozval horizontal_display_size number_data_lines -------------------------------------------------------------- - 1 ? =
818 32003e?avr32?05/06 at32ap7000 in monochrome mode, horizontal_display_size is equal to the number of horizontal pixels. the number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. in color mode, horizontal_display_size equals three times the number of horizontal pixels. in tft mode: the frame rate equation is used first without considering the clock periods added at the end beginning or at the end of each line to determine, approximately, the pclk rate: with this value, the clkval is fixed, as well as the corresponding pclk rate. then select vhdly, hpw and hbp according to the type of lcd used and ?equation 1? on page 815 . finally, the frame rate is adjusted to 70 hz - 75 hz with the hfp value: the line counting is controlled by the read-only field linecnt of lcdcon1 register. the linecnt field decreases by one unit at each falling edge of hsync. 35.6.2.10 display this block is used to configure the polarity of the data and control signals. the polarity of all clock signals can be configured by lcdcon2[12:8] register setting. the block also generates the pwr output that can be used to turn the lcd module on and off by software. this signal is controlled by the pwrcon register and respects the number of frames configured in the guard_time field of pwrcon register (pwrcon[7:1]) between the write access to pwr field (pwrcon[0]) and the activation/deactivation of pwr output signal. the minimum value for the guard_time field is one frame. this gives the dma controller enough time to fill the fifos before the start of data transfer to the lcd. 35.6.2.11 pwm this block generates the lcd contrast control signal (cc) to make possible the control of the display's contrast by software. this is an 8-bit pwm (pulse width modulation) signal that can be converted to an analog voltage with a simple passive filter. the pwm module has a free-running counter whose value is compared against a compare reg- ister (contrast_val register). if the value in the counter is less than that in the register, the output brings the value of the polarity (pol) bit in the pwm control register: contrast_ctr. otherwise, the opposite value is output. thus, a periodic waveform with a pulse width propor- tional to the value in the compare register is generated. lineval vertical_display_size 1 ? = hozval horizontal_display_size 1 ? = lineval vertical_display_size 1 ? = f lcd_pclk hozval 5 + () f lcd_vsync lineval 1 + () () = hfp f pclk 1 f lcd_vsync lineval vbp vfp 1 +++ () -------------------------------------------------------------------------------------------------------- - vhdly vpw vbp hozval 5 +++ + () ? =
819 32003e?avr32?05/06 at32ap7000 due to the comparison mechanism, the output pulse has a width between zero and 255 pwm counter cycles. thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) vdd can be obtained (for the positive polarity case, or between (1/256) vdd and vdd for the negative polarity case). other voltage values can be obtained by adding active external circuitry. for pwm mode, the frequency of the counter can be adjusted to four different values using field ps of contrast_ctr register. 35.6.3 lcd interface the lcd controller interfaces with the lcd module through the lcd interface ( table 35-12 on page 824 ). the controller supports the following interface configurations: 24-bit tft single scan, 16-bit stn dual scan mono (color), 8-bit stn dual (single) scan mono (color), 4-bit sin- gle scan mono (color). a 4-bit single scan stn display us es 4 parallel data lines to shift data to successive single hori- zontal lines one at a time until the entire frame has been shifted and transferred. the 4 lsb pins of lcd data bus (lcdd [3:0]) can be directly connected to the lcd driver; the 20 msb pins (lcdd [23:4]) are not used. an 8-bit single scan stn display uses 8 parallel data lines to shift data to successive single hor- izontal lines one at a time until the entire frame has been shifted and transferred. the 8 lsb pins of lcd data bus (lcdd [7:0]) can be directly connected to the lcd driver; the 16 msb pins (lcdd [23:8]) are not used. an 8-bit dual scan stn display uses two sets of 4 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. the bus lcdd[3:0] is connected to the upper panel data lines and the bus lcdd[7:4] is connected to the lower panel data lines. the re st of the lcd data bus lines (lcdd[23:8]) are not used. a 16-bit dual scan stn display uses two sets of 8 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. the bus lcdd[7:0] is connected to the upper panel data lines and the bus lcdd[15:8] is connected to the lower panel data lines. the rest of the lcd data bus lines (lcdd[23:16]) are not used. stn mono displays require one bit of image data per pixel. stn color displays require three bits (red, green and blue) of image data per pixel, resu lting in a horizontal shift register of length three times the number of pixels per horizontal line. this rgb or monochrome data is shifted to the lcd driver as consecutive bits via the parallel data lines. a tft single scan display uses up to 24 parallel data lines to shift data to successive horizontal lines one at a time until the entire frame has been shifted and transferred. the 24 data lines are divided in three bytes that define the color shade of each color component of each pixel. the lcdd bus is split as lcdd[23:16 ] for the blue component, lcdd [15:8] for the green component and lcdd[7:0] for the red component. if the lcd module has lower color resolution (fewer bits per color component), only the most significant bits of each component are used. all these interfaces are shown in figure 35-8 to figure 35-12 . figure 35-8 on page 820 shows the 24-bit single scan tft display timing; figure 35-9 on page 820 shows the 4-bit single scan stn display timing for monochrome and color modes; figure 35-10 on page 821 shows the 8-bit single scan stn display timing for monochrome and color modes; figure 35-11 on page 822
820 32003e?avr32?05/06 at32ap7000 shows the 8-bit dual scan stn display timing for monochrome and color modes; figure 35-12 on page 823 shows the 16-bit dual scan stn display timing for monochrome and color modes. figure 35-8. tft timing (first line expanded view) figure 35-9. single scan monochrome and color 4-bit panel timing (first line expanded view) lcd_vsync lcd_dval lcd_hsync lcd_pclk lcdd [24:16] lcdd [15:8] lcdd [7:0] g0 b0 r0 g1 b1 r1 lcd_vsync lcd_dval lcd_hsync lcd_pclk lcdd [3] lcdd [2] lcdd [1] lcdd [0] p1 p0 p2 p3 p5 p4 p6 p7 lcd_vsync lcd_dval lcd_h sync lcd_pclk lcdd [3] lcdd [2] lcdd [1] lcdd [0] g0 r0 b0 r1 b1 g1 r2 g2
821 32003e?avr32?05/06 at32ap7000 figure 35-10. single scan monochrome and color 8-bit panel timing (first line expanded view) lcdd [7] lcdd [6] lcdd [5] lcdd [4] p1 p0 p2 p3 p9 p8 p10 p11 lcdd [7] lcdd [6] lcdd [5] lcdd [4] g0 r0 b0 r1 r3 b2 g3 b3 lcdd [3] lcdd [2] lcdd [1] lcdd [0] p5 p4 p6 p7 p13 p12 p14 p15 lcdd [3] lcdd [2] lcdd [1] lcdd [0] b1 g1 r2 g2 g4 r4 b4 r5 lcd_vsync lcd_dval lcd_hsync lcd_pclk lcd_vsync lcd_dval lcd_hsync lcd_pclk
822 32003e?avr32?05/06 at32ap7000 figure 35-11. dual scan monochrome and color 8-bit pa nel timing (first line expanded view) lcdd [7] lcdd [6] lcdd [5] lcdd [4] lp1 lp0 l2 l3 lp5 lp4 lp6 lp7 lcdd [7] lcdd [6] lcdd [5] lcdd [4] lg0 lr0 lb0 lr1 lb1 lg1 lr2 lg2 lcdd [3] lcdd [2] lcdd [1] lcdd [0] up1 up0 up2 up3 up5 up4 up6 up7 lcdd [3] lcdd [2] lcdd [1] lcdd [0] ug0 ur0 ub0 ur1 ub1 ug1 ur2 ug2 lower pane upper pane lower pane upper pane lcd_vsync lcd_dval lcd_hsync lcd_pclk lcd_vsync lcd_dval lcd_hsync lcd_pclk
823 32003e?avr32?05/06 at32ap7000 figure 35-12. dual scan monochrome and color 16-bit panel timing (first line expanded view) lcd_vsync lcd_dval lcd_hsync lcd_pclk lcdd [15] lcdd [ 14 ] lcdd [13] lcdd [12] lp1 lp0 lp2 lp3 lp9 lp8 lp10 lp11 lcdd [15] lcdd [ 14 ] lcdd [13] lcdd [12] lg0 lr0 lb0 lr1 lr3 lb2 lg3 lb3 lcdd [11] lcdd [ 10 ] lcdd [9] lcdd [8] lp5 lp4 lp6 lp7 lp13 lp12 lp14 lp15 lcdd [11] lcdd [ 10 ] lcdd [9] lcdd [8] lb1 lg1 lr2 lg2 lg4 lr4 lb4 lr5 lcdd [7] lcdd [ 6 ] lcdd [5] lcdd [4] ug0 ur0 ub0 ur1 ur3 ub2 ug3 ub3 lcdd [3] lcdd [ 2 ] lcdd [1] lcdd [0] ub1 ug1 ur2 ug2 ug4 ur4 ub4 ur5 lower panel upper panel lc dd [7] lcdd [ 6 ] lcdd [5] lcdd [4] up1 up0 up2 up3 up9 up8 up10 up11 lcdd [3] lcdd [ 2 ] lcdd [1] lcdd [0] up5 up4 up6 up7 up13 up12 up14 up15 lower panel upper panel lcd_vsync lcd_dval lc d_hsync lcd_pclk
824 32003e?avr32?05/06 at32ap7000 table 35-12. lcd signal multiplexing lcd data bus 4-bit stn single scan (mono, color) 8-bit stn single scan (mono, color) 8-bit stn dual scan (mono, color) 16-bit stn dual scan (mono, color) 24-bit tft 16-bit tft lcdd[23] blue7 blue4 lcdd[22] blue6 blue3 lcdd[21] blue5 blue2 lcdd[20] blue4 blue1 lcdd[19] blue3 blue0 lcdd[18] blue2 intensity bit lcdd[17] blue1 lcdd[16] blue0 lcdd[15] lcdlp7 green7 green4 lcdd[14] lcdlp6 green6 green3 lcdd[13] lcdlp5 green5 green2 lcdd[12] lcdlp4 green4 green1 lcdd[11] lcdlp3 green3 green0 lcdd[10] lcdlp2 green2 intensity bit lcdd[9] lcdlp1 green1 lcdd[8] lcdlp0 green0 lcdd[7] lcd7 lcdlp3 lcdup7 red7 red4 lcdd[6] lcd6 lcdlp2 lcdup6 red6 red3 lcdd[5] lcd5 lcdlp1 lcdup5 red5 red2 lcdd[4] lcd4 lcdlp0 lcdup4 red4 red1 lcdd[3] lcd3 lcd3 lcdup3 lcdup3 red3 red0 lcdd[2] lcd2 lcd2 lcdup2 lcdup2 red2 intensity bit lcdd[1] lcd1 lcd1 lcdup1 lcdup1 red1 lcdd[0] lcd0 lcd0 lcdup0 lcdup0 red0
825 32003e?avr32?05/06 at32ap7000 35.7 interrupts the lcd controller generates six different irqs. a ll the irqs are synchronized with the internal lcd core clock. the irqs are: ? dma memory error irq. generated when the dma receives an error response from an ahb slave while it is doing a data transfer. ? fifo underflow irq. generated when the serializer tries to read a word from the fifo when the fifo is empty. ? fifo overwrite irq. generated when the dma co ntroller tries to write a word in the fifo while the fifo is full. ? dma end of frame irq. generated when the dma controller updates the frame base address pointers. this irq can be used to implement a double-buffer technique. for more information, see ?double-buffer technique? on page 827 . ? end of line irq. this irq is generated when the lineblank period of each line is reached and the dma controller is in inactive state. ? end of last line irq. this irq is generated when the lineblank period of the last line of the current frame is reached and the dma controller is in inactive state. each irq can be individually enabled, disabled or cleared, in the ier (interrupt enable regis- ter), idr (interrupt disable register) and icr (interrupt clear register) registers. the imr register contains the mask value for each irq source and the ldc_isr contains the status of each irq source. a more detailed description of these registers can be found in ?lcd controller (lcdc) user interface? on page 831 . 35.8 configuration sequence the dma controller starts to transfer image dat a when the lcdc core is activated (write to pwr field of pwrcon register). thus, the user should configure the lcdc core and configure and enable the dma contro ller prior to activation of the lcd controller. in addition, the image data to be shows should be available when the lcdc core is activated, regardless of the value programmed in the guard_time field of the pwrcon register. to disable the lcd controller, the user should disable the lcdc core and then disable the dma controller. the user should not enable the lcdc again until the lcdc core is in idle state. this is checked by reading t he busy bit in the pwrcon register. the initialization sequence that the user should follow to make the lcdc work is: ? create or copy the first image to show in the display buffer memory. ? if a palletized mode is used, create and store a palette in the internal lcd palette memory( see section ?35.6.2.5? on page 809. ? configure the lcd controller core without enabling it: ? lcdcon1 register: program the clkval a nd bypass fields: these fields control the pixel clock divisor that is used to generat e the pixel clock pclk. the value to program depends on the lcd core clock and on the type and size of the lcd module used. there is a minimum value of the pclk clock period that depends on the lcd controller configuration, this minimum value can be found in table 35-11 on page 814 . the equations that are used to calculat e the value of the pixel clock divisor can be found at the end of the section ?timegen? on page 813
826 32003e?avr32?05/06 at32ap7000 ? lcdcon2 register: program its fields fo llowing their descriptions in the lcd controller user interface se ction below and considering the type of lcd module used and the desired working mode. consider that not all combinations are possible. ? lcdtim1 and lcdtim2 registers: program their fields according to the datasheet of the lcd module used and with the help of the timegen section in page 10. note that some fields are not applicable to stn modules and must be programmed with 0 values. note also that there is a limitation on the minimum value of vhdly, hpw, hbp that depends on the configuration of the lcdc. ? lcdfrmcfg register: program the dimensions of the lcd module used. ? lcdfifo register: to program it, use the formula in section ?fifo? on page 806 ? lcdmval register: its configuration depends on the lcd module used and should be tuned to improve the image quality in the display ( see section ?35.6.2.8? on page 813. ) ? dp1_2 to dp6_7 registers: they are only used for stn displays. they contain the dithering patterns used to generate gray shades or colors in these modules. they are loaded with recommended patterns at reset, so it is not necessary to write anything on them. they can be used to improve the image quality in the display by tuning the patterns in each application. ? pwrcon register: this register controls the power-up sequence of the lcd, so take care to use it properly. do not enable the lcd (writing a 1 in pwr field) until the previous steps and the configuration of the dma have been finished. ? contrast_ctr and contrast_val: use this registers to adjust the contrast of the display, when the cc line is used. ? configure the dma controller. the user should configure the base address of the display buffer memory, the size of the ahb transaction and the size of the display image in memory. when the dma is configured the user should enable the dma. to do so the user should configure the following registers: ? dmabaddr1 and dmabaddr2 registers: in single scan mode only dmabaddr1 register must be configured with the base address of the display buffer in memory. in dual scan mode dmabaddr1 should be co nfigured with the base address of the upper panel display buffer and dmabaddr2 should be configured with the base address of the lower panel display buffer. ? dmafrmcfg register: program the frmsize field. note that in dual scan mode the vertical size to use in the calculation is that of each panel. respect to the brstln field, a recommended value is a 4-word burst. ? dmacon register: once both the lcd cont roller core and the dma controller have been configured, enable the dma controller by writing a ?1? to the dmaen field of this register. if using a dual scan module or the 2d addressing feature, do not forget to write the dmaupdt bit after every change to the set of dma configuration values. ? dma2dcfg register: required only in 2d memory addressing mode (see ?2d memory addressing? on page 827 ). ? finally, enable the lcd controller core by writing a ?1? in the pwr field of the pwrcon register and do any other action that may be required to turn the lcd module on.
827 32003e?avr32?05/06 at32ap7000 35.9 double-buffer technique the double-buffer technique is used to avoid flickering while the frame being displayed is updated. instead of using a single buffer, there are two different buffers, the backbuffer (back- ground buffer) and the primary buffer (the buffer being displayed). the host updates the backbuffer while the lcd controller is displaying the primary buffer. when the backbuffer has been updated the host updates the dma base address registers. when using a dual panel lcd module, both base address pointers should be updated in the same frame. there are two possibilities: ? check the dmafrmptx register to ensure that there is enough time to update the dma base address registers before the end of frame. ? update the frame base address registers when the end of frame irq is generated. once the host has updated the frame base address registers and the next dma end of frame irq arrives, the backbuffer and the primary buffer are swapped and the host can work with the new backbuffer. when using a dual-panel lcd module, both ba se address pointers should be updated in the same frame. in order to achieve this, the dm aupdt bit in dmacon register must be used to validate the new base address. 35.10 2d memory addressing the lcdc can be configured to work on a frame buffer larger than the actual screen size. by changing the values in a few registers, it is easy to move the displayed area along the frame buffer width and height. figure 35-13. .frame buffer addressing frame buffer pixel offset line address increment ... pixel offset addr.inc
828 32003e?avr32?05/06 at32ap7000 in order to locate the displayed window within a larger frame buffer, the software must: ? program the dmabaddr1 (dmabaddr2) register (s) to make them point to the word containing the first pixel of the area of interest. ? program the pixeloff field of dma2dcfg register to specify the offset of this first pixel within the 32-bit memory word that contains it. ? define the width of the complete frame buffer by programming in the field addrinc of dma2dcfg register the address increment between the last word of a line and the first word of the next line (in number of 32-bit words).
829 32003e?avr32?05/06 at32ap7000 ? enable the 2d addressing mode by writing the dma2den bit in dmacon register. if this bit is not activated, the values in the dma2dcfg register are not considered and the controller assumes that the displayed area occupies a continuous portion of the memory. the above configuration can be changed frame to frame, so the displayed window can be moved rapidly. note that the frmsize field of dmafrmcfg register must be updated with any movement of the displaying window. note also that the software must write bit dmaupdt in dmacon register after each configurat ion for it to be accepted by lcdc. note: in 24 bpp packed mode, the dma base address must point to a word containing a complete pixel (possible values of pixeloff are 0 and 8). this me ans that the horizontal origin of the displaying window must be a multiple of 4 pixels or a multiple of 4 pixels minus 1 ( x = 4n or x = 4n-1 , valid ori- gins are pixel 0,3,4,7,8,11,12, etc.). 35.11 general-pur pose register the lcd controller has eight general-purpose output lines that are controlled by a general-pur- pose register (lcdgpr). the use of these lines is not fixed; they can be used in a wide range of applications. some applications examples are: ? palette swapping: in this application, the size of the palette memory is doubled. the two extra bits in the addresses (one extra bit in the low-priority address and one extra bit in the high- priority address) are connected to two general-purpose lines. one line is used to select the palette being updated through the ahb slave interface and the other line is used to select the working palette. ? common intensity control in tft mode: in this application, the most significant bit of each lcd component of the tft interface is logically or-ed with a general-purpose line. if the most significant bit of each color component in the palette is 0, the intensity can be controlled with the single general-purpose line. ? control of signals of lcd modules not included in the lcd interface, such as a standard/reverse scanning configuration pin, backlight on/off pin or user leds of the lcd module.
830 32003e?avr32?05/06 at32ap7000 35.12 register configuration guide 35.12.1 stn mode example stn color(r,g,b) 320*240, 8-bit single scan, 70 frames/sec, core clock = 60 mhz data rate : 320*240*70*3/8 = 2.016mhz hozval= ((3*320)/8 ) -1 lineval= 240 -1 clkval = 60mhz/ (2*2.016mhz) = 15 lcdcon1= clkval << 12 lcdcon2 = littleendian | singlescan | stncolor | disp8bit| ps8bpp; lcdtim1 = 0; lcdtim2 = 10 | (10 << 21); lcdfrmcfg = (hozval << 21) | lineval; lcdmval = 0x80000004; dmafrmcfg = (7 << 24) + (320 * 240 * 8) / 32; 35.12.2 tft mode example this example is based on the nec tft color lcd module nl6448bc20-08 . tft 640*480, 16-bit single scan, 60 frames/sec, pixel clock frequency = [21mhz..29mhz] with a typical value = 25,175mhz. the core clock must be (2*n)*pi xel clock frequency [42mhz..100mhz] hozval = 640 -1 lineval = 240 -1 if core clock is 50 mhz clkval = 50mhz/ (2*25,175mhz) = 1 vfp = (12), vbp = (31), vpw = (2-1), vhdly= (2-1) hfp = (16-1), hbp = (48 -1), hpw= (96-1) lcdcon1= clkval << 12 lcdcon2 = littleendian | clkmod | invert_clk | invert_line | invert_frm | ps16bpp | singlescan | tft lcdtim1 = vfp | (vbp << 8) | (vpw << 16) | (vhdly << 24) lcdtim2 = hbp | (hpw << 8) | (hfp << 21) lcdfrmcfg = (hozval << 21) | lineval lcdmval = 0 dmafrmcfg = (7 << 24) + (640 * 480* 16) / 32;
831 32003e?avr32?05/06 at32ap7000 35.13 lcd controller (lcdc) user interface table 35-13. lcd controller (lcdc) user interface offset register register name access reset value 0x0 dma base address register 1 dmabaddr1 r/w 0x00000000 0x4 dma base address register 2 dmabaddr2 r/w 0x00000000 0x8 dma frame pointer register 1 dmafrmpt1 read-only 0x00000000 0xc dma frame pointer register 2 dmafrmpt2 read-only 0x00000000 0x10 dma frame address register 1 dmafrmadd1 read-only 0x00000000 0x14 dma frame address register 2 dmafrmadd2 read-only 0x00000000 0x18 dma frame configuration register dmafrmcfg r/w 0x00000000 0x1c dma control register dmacon r/w 0x00000000 0x20 dma control register dma2dcfg r/w 0x00000000 0x800 lcd control register 1 lcdcon1 r/w 0x00002000 0x804 lcd control register 2 lcdcon2 r/w 0x00000000 0x808 lcd timing register 1 lcdtim1 r/w 0x00000000 0x80c lcd timing register 2 lcdtim2 r/w 0x00000000 0x810 lcd frame configuration register lcdfrmcfg r/w 0x00000000 0x814 lcd fifo register lcdfifo r/w 0x00000000 0x818 mode toggle rate value register lcdmval r/w 0x00000000 0x81c dithering pattern dp1_2 dp1_2 r/w 0xa5 0x820 dithering pattern dp4_7 dp4_7 r/w 0x5af0fa5 0x824 dithering pattern dp3_5 dp3_5 r/w 0xa5a5f 0x828 dithering pattern dp2_3 dp2_3 r/w 0xa5f 0x82c dithering pattern dp5_7 dp5_7 r/w 0xfaf5fa5 0x830 dithering pattern dp3_4 dp3_4 r/w 0xfaf5 0x834 dithering pattern dp4_5 dp4_5 r/w 0xfaf5f 0x838 dithering pattern dp6_7 dp6_7 r/w 0xf5ffaff 0x83c power control register pwrcon r/w 0x0000000e 0x840 contrast control register contrast_ctr r/w 0x00000000 0x844 contrast value register contrast_val r/w 0x00000000 0x848 lcd interrupt enable register ier write-only 0x0 0x84c lcd interrupt disable register idr write-only 0x0 0x850 lcd interrupt mask register imr read-only 0x0 0x854 lcd interrupt status register isr read-only 0x0 0x858 lcd interrupt clear register icr write-only 0x0 0x85c lcd general-purpose register gpr r/w 0x0 0x860 lcd interrupt test register itr write-only 0 0x864 lcd interrupt raw status register irr read-only 0
832 32003e?avr32?05/06 at32ap7000 0xc00 palette entry 0 lut entry 0 r/w 0xc04 palette entry 1 lut entry 1 r/w 0xc08 palette entry 2 lut entry 2 r/w 0xc0c palette entry 3 lut entry 3 r/w ?? 0xffc palette entry 255 lut entry 255 r/w table 35-13. lcd controller (lcdc) user interface (continued) offset register register name access reset value
833 32003e?avr32?05/06 at32ap7000 35.13.1 dma base address register 1 name: dmabaddr1 access: read/write reset value: 0x00000000 ? baddr-u base address for the upper panel in dual scan mode. base address for the complete frame in single scan mode. if a dual scan configuration is selected in lcdcon2 register or bit dma2den in register dmacon is set, the bit dmaupdt in that same register must be written after writing an y new value to this field in or der to make the dma controller use this new value. 31 30 29 28 27 26 25 24 baddr-u 23 22 21 20 19 18 17 16 baddr-u 15 14 13 12 11 10 9 8 baddr-u 76543210 baddr-u
834 32003e?avr32?05/06 at32ap7000 35.13.2 dma base address register 2 name: dmabaddr2 access: read/write reset value: 0x00000000 ? baddr-l base address for the lower panel in dual scan mode only. if a dual scan configuration is selected in lcdcon2 register or bit dma2den in register dmacon is set, the bit dmaupdt in that same register must be written after writing an y new value to this field in or der to make the dma controller use this new value. 31 30 29 28 27 26 25 24 baddr-l 23 22 21 20 19 18 17 16 baddr-l 15 14 13 12 11 10 9 8 baddr-l 76543210 baddr-l
835 32003e?avr32?05/06 at32ap7000 35.13.3 dma frame pointer register 1 name: dmafrmpt1 access: read-only reset value: 0x00000000 ?frmpt-u current value of frame pointer for the upper panel in dual scan mode. current value of frame pointer for the complete frame in single scan mode. down count from frmsize to 0. note: this register is read-only and contains the current value of the frame pointer (number of wo rds to the end of the frame). it can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -frmpt-u 15 14 13 12 11 10 9 8 frmpt-u 76543210 frmpt-u
836 32003e?avr32?05/06 at32ap7000 35.13.4 dma frame pointer register 2 name: dmafrmpt2 access: read-only reset value : 0x00000000 ?frmpt-l current value of frame pointer for the lower panel in dual scan mode only. down count from frmsize to 0. note: this register is read-only and contains the current value of the frame pointer (number of wo rds to the end of the frame). it can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -frmpt-l 15 14 13 12 11 10 9 8 frmpt-l 76543210 frmpt-l
837 32003e?avr32?05/06 at32ap7000 35.13.5 dma frame address register 1 name: dmafrmadd1 access: read-only reset value: 0x00000000 ? frmadd-u current value of frame address for the upper panel in dual scan mode. current value of frame address for the complete frame in single scan. note: this register is read-only and contains the current val ue of the last dma transaction in the bus for the panel/frame. 31 30 29 28 27 26 25 24 frmadd-u 23 22 21 20 19 18 17 16 frmadd-u 15 14 13 12 11 10 9 8 frmadd-u 76543210 frmadd-u
838 32003e?avr32?05/06 at32ap7000 35.13.6 dma frame address register 2 name: dmafrmadd2 access: read-only reset value: 0x00000000 ? frmadd-l current value of frame address for the lower panel in single scan mode only. note: this register is read-only and contains the current va lue of the last dma transaction in the bus for the panel. 31 30 29 28 27 26 25 24 frmadd-l 23 22 21 20 19 18 17 16 frmadd-l 15 14 13 12 11 10 9 8 frmadd-l 76543210 frmadd-l
839 32003e?avr32?05/06 at32ap7000 35.13.7 dma frame c onfiguration register name: dmafrmcfg access: read/write reset value: 0x00000000 ? frmsize: frame size in single scan mode, this is the frame size in words. in dual scan mode, this is the size of each panel. if a dual scan configuration is selected in lcdcon2 register or bit dma2den in register dmacon is set, the bit dmaupdt in that same register must be written after writing an y new value to this field in or der to make the dma controller use this new value. ? brstln: burst length program with the desired burst length - 1 31 30 29 28 27 26 25 24 -brstln 23 22 21 20 19 18 17 16 frmsize 15 14 13 12 11 10 9 8 frmsize 76543210 frmsize
840 32003e?avr32?05/06 at32ap7000 35.13.8 dma control register name: dmacon access: read/write reset value: 0x00000000 ? dmaen: dma enable 0: dma is disabled. 1: dma is enabled. ? dmarst: dma reset (write-only) 0: no effect. 1: reset dma module. dma module should be reset only when disabled and in idle state. ? dmabusy: dma busy 0: dma module is idle. 1: dma module is busy (doing a transaction on the ahb bus). ? dmaupdt: dma configuration update 0: no effect 1: update dma configuration . used for simultaneous updating of dma parameters in dual scan mode or when using 2d addressing. the values written in the registers dmabaddr1, dmabaddr2 and dma2dcfg, and in the field frmsize of register dmafrmcfg, are accepted by the dma controller and are applied at the next frame. this bit is used only if a dual scan configuration is selected (bit scanmod of lcdcon2 register) or 2d addressing is enabled (bit dma2den in this register). otherwise, the lcd controller accepts immediately the values written in the registers referred to above. ? dma2den: dma 2d adressing enable 0: 2d adressing is disabled (values in register dma2dcfg are ?don?t care?). 1: 2d adressing is enabled. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 dma2den dmaupdt dmabusy dmarst dmaen
841 32003e?avr32?05/06 at32ap7000 35.13.9 lcd dma 2d adressing register name: dma2dcfg access: read/write reset value: 0x00000000 ? addrinc: dma 2d addressing address increment when 2-d dma addressing is enabled (bit dma2den is set in register dmacon), th is field specifies the number of bytes that the dma controller must jump between screen lines. itb must be programmed as: [({address of first 32-bit word in a screen line} - {address of last 32-bit word in previous line})]. in other words, it is equal to 4*[number of 32-bit words occu- pied by each line in the complete frame buffer minus the number of 32-bit words occupied by each displayed line]. bit dmaupdt in register dmacon must be writ ten after writing any new value to this field in order to make the dma control- ler use this new value. ? pixeloff: dam2d addressing pixel offset when 2d dma addressing is enabled (bit dma2den is set in register dmacon), this field specifies the offset of the first pixel in each line within th e memory word that contains this pixel. the offset is specified in number of bits in the range 0-31 , so for example a value of 4 indicates that the first pixel in th e screen starts at bit 4 of the 32-bit word pointed by register dmabaddr1. bits 0 to 3 of that word are not used. this example is valid for little end ian memory organization. when using big endian memory organization, this offset is considered from bit 31 dow nwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering con- figuration. bit dmaupdt in register dmacon must be written a fter writing any new value to this field in order to make the dma controller use this new value. 31 30 29 28 27 26 25 24 pixeloff 23 22 21 20 19 18 17 16 - 15 14 13 12 11 10 9 8 addrinc 76543210 addrinc
842 32003e?avr32?05/06 at32ap7000 35.13.10 lcd control register 1 name: lcdcon1 access: read/write, except linecnt: read-only reset value: 0x00002000 ? bypass: bypass pclk divider 0: the divider is not bypassed. pclk frequency defined by the clkval field. 1: the pclk divider is bypassed. pclk freq uency is equal to the lcdc clock frequency. ? clkval: clock divider 9-bit divider for pixel clock (pclk) frequency. ? linecnt: line counter (read-only) current value of 11-bit line counter. down count from lineval to 0. 31 30 29 28 27 26 25 24 linecnt 23 22 21 20 19 18 17 16 linecnt clkval 15 14 13 12 11 10 9 8 clkval ---- 76543210 -------bypass pixel_clock system_clock clkval ( 1 ) + 2 ? =
843 32003e?avr32?05/06 at32ap7000 35.13.11 lcd control register 2 name: lcdcon2 access: read/write reset value: 0x0000000 ? distype: display type ? scanmod: scan mode 0: single scan 1: dual scan ? ifwidth: interface width (stn) 31 30 29 28 27 26 25 24 memor ------ 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 clkmod - - invdval invclk invline invframe invvd 76543210 pixelsize ifwidth scanmod distype distype 0 0 stn monochrome 0 1 stn color 10tft 11reserved ifwidth 0 0 4-bit (only valid in single scan stn mono or color) 0 1 8-bit (only valid in stn mono or color) 1 0 16-bit (only valid in dual scan stn mono or color) 11reserved
844 32003e?avr32?05/06 at32ap7000 ? pixelsize: bits per pixel ? invvd: lcdd polarity 0: normal 1: inverted ? invframe: vsync polarity 0: normal (active high) 1: inverted (active low) ? invline: hsync polarity 0: normal (active high) 1: inverted (active low) ? invclk: pclk polarity 0: normal (lcdd fetche d at pclk falling edge) 1: inverted (lcdd fetched at pclk rising edge) ? invdval: dval polarity 0: normal (active high) 1: inverted (active low) ? clkmod: pclk mode 0: pclk only active during active display period 1: pclk always active ? memor: memory ordering format 00: big endian 10: little endian 11: wince format pixelsize 0 0 0 1 bit per pixel 0 0 1 2 bits per pixel 0 1 0 4 bits per pixel 0 1 1 8 bits per pixel 1 0 0 16 bits per pixel 1 0 1 24 bits per pixel (only valid in tft mode) 1 1 0 reserved 1 1 1 reserved
845 32003e?avr32?05/06 at32ap7000 35.13.12 lcd timing configuration register 1 name: lcdtim1 access: read/write reset value: 0x0000000 ? vfp: vertical front porch in tft mode, these bits equal the number of idle lines at the end of the frame. in stn mode, these bits should be set to 0. ?vbp: vertical back porch in tft mode, these bits equal the number of idle lines at the beginning of the frame. in stn mode, these bits should be set to 0. ? vpw: vertical synchronization pulse width in tft mode, these bits equal the vertical synchronization pu lse width, given in number of lines. vsync width is equal to (vpw+1) lines. in stn mode, these bits should be set to 0. ? vhdly: vertical to horizontal delay in tft mode, this is the delay between vsync rising or falling edge and hsync rising edge. delay is (vhdly+1) pclk cycles. in stn mode, these bits should be set to 0. 31 30 29 28 27 26 25 24 ---- vhdly 23 22 21 20 19 18 17 16 -- vpw 15 14 13 12 11 10 9 8 vbp 76543210 vfp
846 32003e?avr32?05/06 at32ap7000 35.13.13 lcd timing configuration register 2 name: lcdtim2 access: read/write reset value: 0x0000000 ? hbp: horizontal back porch number of idle pclk cycles at the beginning of the line. idle period is (hbp+1) pclk cycles. ? hpw: horizontal synch ronization pulse width width of the hsync pulse, given in pclk cycles. width is (hpw+1) pclk cycles. ? hfp: horizontal front porch number of idle pclk cycles at the end of the line. idle period is (hfp+1) pclk cycles. 31 30 29 28 27 26 25 24 hfp 23 22 21 20 19 18 17 16 hfp ----- 15 14 13 12 11 10 9 8 -- hpw 76543210 hbp
847 32003e?avr32?05/06 at32ap7000 35.13.14 lcd frame configuration register name: lcdfrmcfg access: read/write reset value: 0x0000000 ? lineval: vertical size of lcd module lineval = (vertical display size) - 1 in dual scan mode, vertical display size refers to the size of each panel. ? hozval: horizontal size of lcd module in stn mode: ? hozval = (horizontal display size / nu mber of valid lcdd data line) - 1 ? in stn monochrome mode, horizontal display size = number of horizontal pixels ? in stn color mode, horizontal display size = 3*number of horizontal pixels ? in 4-bit single scan or 8-bit dual scan stn display mode, number of valid lcdd data lines = 4 ? in 8-bit single scan or 16-bit dual scan stn display mode, number of valid lcdd data lines = 8 ? if the value calculated for hozval with the above formula is not an integer, it must be rounded up to the next integer value. in tft mode: ? hozval = horizontal display size 31 30 29 28 27 26 25 24 hozval 23 22 21 20 19 18 17 16 hozval ----- 15 14 13 12 11 10 9 8 ----- lineval 76543210 lineval
848 32003e?avr32?05/06 at32ap7000 35.13.15 lcd frame configuration register name: lcdfrmcfg access: read/write reset value: 0x0000000 ? lineval: vertical size of lcd module in single scan mode: vertical size of lcd module, in pixels, minus 1 in dual scan mode: vertical display size of each lcd panel, in pixels, minus 1 ? linesize: horizontal size of lcd module, in pixels, minus 1 31 30 29 28 27 26 25 24 linesize 23 22 21 20 19 18 17 16 linesize ----- 15 14 13 12 11 10 9 8 ----- lineval 76543210 lineval
849 32003e?avr32?05/06 at32ap7000 35.13.16 lcd fifo register name: lcdfifo access: read/write reset value: 0x0000000 ? fifoth: fifo threshold must be programmed with: where: ? fifo_effective_size is the effective size of the fifo. it is the total fifo memory size in single scan mode and half that size in dual scan mode. ? dma_burst_length is the burst length of the transfers made by the dma. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 fifoth 76543210 fifoth fifoth fifo_effective_size 2 dma_burst_length 3 + () ? =
850 32003e?avr32?05/06 at32ap7000 35.13.17 mode toggle rate value register name: lcdmval access: read/write reset value: 0x00000000 ? mval: mode toggle rate value mode toggle rate if mmode = 1. toggle rate is mval + 1 line periods. ? mmode: mode toggle rate select 0: each frame 1: rate defined by mval 31 30 29 28 27 26 25 24 mmode------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 mval
851 32003e?avr32?05/06 at32ap7000 35.13.18 dithering pattern dp1_2 register name: dp1_2 access: read/write reset value: 0xa5 ? dp1_2: pattern value for ? duty cycle 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 dp1_2
852 32003e?avr32?05/06 at32ap7000 35.13.19 dithering pattern dp4_7 register name: dp4_7 access: read/write reset value: 0x5af0fa5 ? dp4_7: pattern value for 4/7 duty cycle 31 30 29 28 27 26 25 24 ---- dp4_7 23 22 21 20 19 18 17 16 dp4_7 15 14 13 12 11 10 9 8 dp4_7 76543210 dp4_7
853 32003e?avr32?05/06 at32ap7000 35.13.20 dithering pattern dp3_5 register name: dp3_5 access: read/write reset value: 0xa5a5f ? dp3_5: pattern value for 3/5 duty cycle 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- dp3_5 15 14 13 12 11 10 9 8 dp3_5 76543210 dp3_5
854 32003e?avr32?05/06 at32ap7000 35.13.21 dithering pattern dp2_3 register name: dp2_3: dithering pattern dp2_3 register access: read/write reset value: 0xa5f ? dp2_3: pattern value for 2/3 duty cycle 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 ---- dp2_3 76543210 dp2_3
855 32003e?avr32?05/06 at32ap7000 35.13.22 dithering pattern dp5_7 register name: dp5_7: access: read/write reset value: 0xfaf5fa5 ? dp5_7: pattern value for 5/7 duty cycle 31 30 29 28 27 26 25 24 ---- dp5_7 23 22 21 20 19 18 17 16 dp5_7 15 14 13 12 11 10 9 8 dp5_7 76543210 dp5_7
856 32003e?avr32?05/06 at32ap7000 35.13.23 dithering pattern dp3_4 register name: dp3_4 access: read/write reset value: 0xfaf5 ? dp3_4: pattern value for 3/4 duty cycle 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 dp3_4 76543210 dp3_4
857 32003e?avr32?05/06 at32ap7000 35.13.24 dithering pattern dp4_5 register name: dp4_5 access: read/write reset value: 0xfaf5f ? dp4_5: pattern value for 4/5 duty cycle 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 ---- dp4_5 15 14 13 12 11 10 9 8 dp4_5 76543210 dp4_5
858 32003e?avr32?05/06 at32ap7000 35.13.25 dithering pattern dp6_7 register name: dp6_7 access: read/write reset value: 0xf5ffaff ? dp6_7: pattern value for 6/7 duty cycle 31 30 29 28 27 26 25 24 ---- dp6_7 23 22 21 20 19 18 17 16 dp6_7 15 14 13 12 11 10 9 8 dp6_7 76543210 dp6_7
859 32003e?avr32?05/06 at32ap7000 35.13.26 power control register name: pwrcon access: read/write reset value: 0x0000000e ? pwr: lcd module power control 0 = pwr pin is low, other * pins are low. 0->1 = * pins activated, pwr are set high with the delay of guard_time frame periods. 1 = pwr pin is high, other * pins are active 1->0 = pwr pin is low, other * pins are active, but are set low after guard_time frame periods. ? guard_time delay in frame periods between applying control signals to the lcd module and setting pwr high, and between setting pwr low and removing control signals from lcd module ?busy read-only field. if 1, it indicates that the lcd is busy (a ctive and displaying data, in power_on sequence or in power off sequence). 31 30 29 28 27 26 25 24 busy------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 guard_time pwr
860 32003e?avr32?05/06 at32ap7000 35.13.27 contrast control register name: contrast_ctr access: read/write reset value: 0x00000000 ?ps this 2-bit value selects the configuration of a counter prescaler. the meaning of each combination is as follows: ?pol this bit defines the polarity of the output. if 1, the ou tput pulses are high level (the out put will be high whenever the value in the counter is less than the value in the compare register contrast_val). if 0, the output pulses are low level. ?ena when 1, this bit enables the operation of the pwm generator. when 0, the pwm counter is stopped. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 ----enapol ps ps 0 0 the counter advances at a rate of fcounter = flcdc_clock. 0 1 the counter advances at a rate of fcounter = flcdc_cloc /2. 1 0 the counter advances at a rate of fcounter = flcdc_clock/4. 1 1 the counter advances at a rate of fcounter = flcdc_clock/8.
861 32003e?avr32?05/06 at32ap7000 35.13.28 contrast value register name: contrast_val access: read/write reset value: 0x00000000 ?cval pwm compare value. used to adjust the analog value obtained after an external filter to control the contrast of the display. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 cval
862 32003e?avr32?05/06 at32ap7000 35.13.29 lcd interrupt enable register name: ier access: write-only reset value: 0x0 ? lnie: line interrupt enable 0: no effect 1: enable each line interrupt ? lstlnie: last line interrupt enable 0: no effect 1: enable last line interrupt ? eofie: dma end of frame interrupt enable 0: no effect 1: enable end of frame interrupt ? uflwie: fifo underflow interrupt enable 0: no effect 1: enable fifo u nderflow interrupt ? owrie: fifo overwrite interrupt enable 0: no effect 1: enable fifo overwrite interrupt ? merie: dma memory error interrupt enable 0: no effect 1: enable dma memory error interrupt 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - merie owrie uflwie - eofie lstlnie lnie
863 32003e?avr32?05/06 at32ap7000 35.13.30 lcd interrupt disable register name: idr access: write-only reset value: 0x0 ? lnid: line interrupt disable 0: no effect 1: disable each line interrupt ? lstlnid: last line interrupt disable 0: no effect 1: disable last line interrupt ? eofid: dma end of frame interrupt disable 0: no effect 1: disable end of frame interrupt ? uflwid: fifo underflow interrupt disable 0: no effect 1: disable fifo un derflow interrupt ? owrid: fifo overwrite interrupt disable 0: no effect 1: disable fifo overwrite interrupt ? merid: dma memory error interrupt disable 0: no effect 1: disable dma memo ry error interrupt 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - merid owrid uflwid - eofid lstlnid lnid
864 32003e?avr32?05/06 at32ap7000 35.13.31 lcd interrupt mask register name: imr access: read-only reset value: 0x0 ? lnim: line interrupt mask 0: line interrupt disabled 1: line interrupt enabled ? lstlnim: last line interrupt mask 0: last line interrupt disabled 1: last line interrupt enabled ? eofim: dma end of frame interrupt mask 0: end of frame interrupt disabled 1: end of frame interrupt enabled ? uflwim: fifo underflow interrupt mask 0: fifo underflow interrupt disabled 1: fifo underflow interrupt enabled ? owrim: fifo overwrite interrupt mask 0: fifo overwrite interrupt disabled 1: fifo overwrite interrupt enabled ? merim: dma memory error interrupt mask 0: dma memory error interrupt disabled 1: dma memory error interrupt enabled 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 -merimowrimuflwim- eofim lstlnim lnim
865 32003e?avr32?05/06 at32ap7000 35.13.32 lcd interrupt status register name: isr access: read-only reset value: 0x0 ? lnis: line interrupt status 0: line interrupt not active 1: line interrupt active ? lstlnis: last line interrupt status 0: last line interrupt not active 1: last line interrupt active ? eofis: dma end of frame interrupt status 0: end of frame interrupt not active 1: end of frame interrupt active ? uflwis: fifo underflow interrupt status 0: fifo underflow interrupt not active 1: fifo underflow interrupt active ? owris: fifo overwrite interrupt status 0: fifo overwrite interrupt not active 1: fifo overwrite interrupt active ? meris: dma memory error interrupt status 0: dma memory error interrupt not active 1: dma memory error interrupt active 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - meris owris uflwis - eofis lstlnis lnis
866 32003e?avr32?05/06 at32ap7000 35.13.33 lcd interrupt clear register name: icr access: write-only reset value: 0x0 ? lnic: line interrupt clear 0: no effect 1: clear each line interrupt ? lstlnic: last line interrupt clear 0: no effect 1: clear last line interrupt ? eofic: dma end of frame interrupt clear 0: no effect 1: clear end of frame interrupt ? uflwic: fifo underflow interrupt clear 0: no effect 1: clear fifo underflow interrupt ? owric: fifo overwrite interrupt clear 0: no effect 1: clear fifo overwrite interrupt ? meric: dma memory error interrupt clear 0: no effect 1: clear dma memory error interrupt 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - meric owric uflwic - eofic lstlnic lnic
867 32003e?avr32?05/06 at32ap7000 35.13.34 lcd general-purpose register name: gpr access: read/write reset value: 0x0 ? gprbx: general-purpose bit controls the general-purpose line x. 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 gprb7 gprb6 gprb5 gprb4 gprb3 gprb2 gprb1 gprb0
868 32003e?avr32?05/06 at32ap7000 35.13.35 lcd interrupt test register name: itr access: write-only reset value: 0x0 ? lnit: line interrupt test 0: no effect 1: set each line interrupt ? lstlnit: last line interrupt test 0: no effect 1: set last line interrupt ? eofit: dma end of frame interrupt test 0: no effect 1: set end of frame interrupt ? uflwit: fifo underflow interrupt test 0: no effect 1: set fifo underflow interrupt ? owrit: fifo overwrite interrupt test 0: no effect 1: set fifo overwrite interrupt ? merit: dma memory error interrupt test 0: no effect 1: set dma memory error interrupt 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - merit owrit uflwit - eofit lstlnit lnit
869 32003e?avr32?05/06 at32ap7000 35.13.36 lcd interrupt raw status register name: irr access: write-only reset value: 0x0 ? lnir: line interrupt raw status 0: no effect 1: line interrupt condition present ? lstlnir: last line interrupt raw status 0: no effect 1: last line interrupt condition present ? eofir: dma end of frame interrupt raw status 0: no effect 1: end of frame interrupt condition present ? uflwir: fifo underflow interrupt raw status 0: no effect 1: fifo underflow interrupt condition present ? owrir: fifo overwrite interrupt raw status 0: no effect 1: fifo overwrite interrupt condition present ? merir: dma memory error interrupt raw status 0: no effect 1: dma memory error interrupt condition present 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - merir owrir uflwir - eofir lstlnir lnir
870 32003e?avr32?05/06 at32ap7000 36. image sensor interface (isi) rev: 6141a 36.1 features ? itu-r bt. 601/656 8-bit mode external inte rface support ? supports up to 12-bit grayscale cmos sensors ? support for itu-r bt.656-4 sa v and eav synchronization ? vertical and horizontal re solutions up to 2048 x 2048 ? preview path up to 640*480 ? 128 bytes fifo on codec path ? 128 bytes fifo on preview path ? support for packed data formatting for ycbcr 4:2:2 formats ? preview scaler to genera te smaller size image ? programmable frame capture rate 36.2 overview the image sensor interface (isi) connects a cmos-type image sensor to the processor and provides image capture in various formats. it does data conversion, if necessary, before the stor- age in memory through dma. the isi supports color cmos image sensor and grayscale image sensors with a reduced set of functionalities. in grayscale mode, the data stream is stored in memory without any processing and so is not compatible with th e lcd controller. internal fifos on the preview and codec paths are used to store the incoming data. the rgb output on the preview path is compatible with the lcd controller. this module outputs the data in rgb format (lcd compatible) and has scaling capabilities to make it compliant to the lcd display resolution (see table 36-3 on page 873 ). several input formats such as preprocessed rgb or ycbcr are supported through the data bus interface. it supports two modes of synchronization: 1. the hardware with vsync and hsync signals 2. the international telecommunication union recommendation itu-r bt.656-4 start-of- active-video (sav) and end-of-active-video (eav) synchronization sequence. using eav/sav for synchronization reduces th e pin count (vsync, hsync not used). the polarity of the synchronization pulse is pr ogrammable to comply with the sensor signals. table 36-1. i/o description signal dir description vsync in vertical synchronization hsync in horizontal synchronization data[11..0] in sensor pixel data mck out master clock provided to the image sensor pck in pixel clock provided by the image sensor
871 32003e?avr32?05/06 at32ap7000 figure 36-1. isi connection example 36.3 block diagram figure 36-2. image sensor interface block diagram 36.4 functional description the image sensor interface (isi) supports direct connection to the international telecommuni- cation union recommendation itu-r bt. 601/656 8-bit mode compliant sensors and up to 12- bit grayscale sensors. it receives the image dat a stream from the image sensor on the 12-bit data bus. this module receives up to 12 bits for data, the ho rizontal and vertical sy nchronizations and the pixel clock. the reduced pin count alternative for synchronization is supported for sensors that embed sav (start of active vide o) and eav (end of active video) delimiters in the data stream. the image sensor interface interrupt line is gener ally connected to the interrupt controller and can trigger an interrupt at the beginning of each frame and at the end of a dma frame transfer. if the sav/eav synchronization is us ed, an interrupt ca n be triggered on each delimiter event. image sensor image sensor interface data[11..0] isi_data[11..0] clk isi_mck pclk isi_pck vsync hsync isi_vsync isi_hsync timing signals interface ccir-656 embedded timing decoder(sav/eav) pixel sampling module clipping + color conversion ycc to rgb 2-d image scaler pixel formatter rx direct display fifo core video arbiter camera ahb master interface apb interface camera interrupt controller config registers clipping + color conversion rgb to ycc rx direct capture fifo scatter mode support packed formatter frame rate ycbcr 4:2:2 8:8:8 5:6:5 rgb cmos sensor pixel input up to 12 bit hsync/len vsync/fen cmos sensor pixel clock input pixel clock domain ahb clock domain apb clock domain from rx buffers camera interrupt request line codec_on ahb bus apb bus
872 32003e?avr32?05/06 at32ap7000 for 8-bit color sensors, the data stream received can be in several possible formats: ycbcr 4:2:2, rgb 8:8:8, rgb 5:6:5 and may be processed before the storage in memory. the data stream may be sent on both preview path and codec path if the bit codec_on in the cr1 is one. to optimize the bandwidth, the codec path should be enabled only when a capture is required. in grayscale mode, the input data stream is stored in memory without any processing. the 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the gs_mode bit in the cr2 register. the codec datapath is not available when grayscale image is selected. a frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. 36.4.1 data timing the two data timings using hori zontal and vertical synchroni zation and eav/sav sequence syn- chronization are shown in figure 36-3 and figure 36-4 . in the vsync/hsync synchronization, the valid da ta is captured with the active edge of the pixel clock (pck), after sfd lines of vertical blanking and sld pixel cl ock periods delay pro- grammed in the control register. the itu-rbt.656-4 defines the functional timing for an 8-bit wide interface. there are two timing reference signals, one at the beginning of each video data block sav (0xff000080) and one at the end of each video data block eav(0xff00009d). only data sent between eav and sav is capt ured. horizontal blanking and vert ical blanking are ignored. use of the sav and eav synchronization eliminates t he vsync and hsync signals from the inter- face, thereby reducing the pin count. in order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. figure 36-3. hsync and vsync synchronization isi_vsync isi_hsync isi_pck frame 1 line ycby crycb y crycby cr data[7..0]
873 32003e?avr32?05/06 at32ap7000 figure 36-4. sav and eav sequence synchronization 36.4.2 data ordering the rgb color space format is required for viewing images on a display screen preview, and the ycbcr color space format is required for encoding. all the sensors do not output the ycbcr or rgb components in the same order. the isi allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. isii_pck cr y cb y cr y y cr y cb ff 00 data[7..0] ff 00 00 80 y cb y 00 9d sav eav active video table 36-2. data ordering in ycbcr mode mode byte 0 byte 1 byte 2 byte 3 default cb(i) y(i) cr(i) y(i+1) mode1 cr(i) y(i) cb(i) y(i+1) mode2 y(i) cb(i) y(i+1) cr(i) mode3 y(i) cr(i) y(i+1) cb(i) table 36-3. rgb format in normal mode mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r7(i) r6(i) r5(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 g7(i) g6(i) g5(i) g4(i) g3(i) g2(i) g1(i) g0(i) byte 2 b7(i) b6(i) b5(i) b4 (i) b3(i) b2(i) b1(i) b0(i) byte 3 r7(i+1) r6(i+1) r5(i+1) r4(i +1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) rgb 5:6:5 byte 0 g2(i) g1(i) g0(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 b4(i) b3(i) b2(i) b1 (i) b0(i) g5(i) g4(i) g3(i) byte 2 g2(i+1) g1(i+1) g0(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) byte 3 b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1) g5(i+1) g4(i+1) g3(i+1) table 36-4. rgb format in rgb swap mode mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r0(i) r1(i) r2(i) r3(i) r4(i) r5(i) r6(i) r7(i) byte 1 g0(i) g1(i) g2(i) g3(i) g4(i) g5(i) g6(i) g7(i) byte 2 b0(i) b1(i) b2(i) b3 (i) b4(i) b5(i) b6(i) b7(i) byte 3 r0(i+1) r1(i+1) r2(i+1) r3(i +1) r4(i+1) r5(i+1) r6(i+1) r7(i+1)
874 32003e?avr32?05/06 at32ap7000 the rgb 5:6:5 input format is processed to be displayed as rgb 5:5:5 format, compliant with the 16-bit mode of the lcd controller. 36.4.3 clocks the sensor master clock (mck) can be generated either by the power manager through a pro- grammable clock output or by an extern al oscillator connec ted to the sensor. none of the sensors embeds a power management controller, so providing the clock by the power manager is a simple and efficient way to control power consumption of the system. care must be taken when programming the system clock. the isi has two clock domains, the system bus clock and the pixel clock provided by sensor. the two clock domains are not syn- chronized, but the system clock must be faster than pixel clock. 36.4.4 preview path 36.4.4.1 scaling, deci mation (subsampling) this module resizes captured 8-bit color sensor images to fit the lcd display format. the resize module performs only downscaling. the same ra tio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. the decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. rgb 5:6:5 byte 0 g3(i) g4(i) g5(i) b0(i) b1(i) b2(i) b3(i) b4(i) byte 1 b4(i) b3(i) b2(i) b1 (i) b0(i) g5(i) g4(i) g3(i) byte 2 g2(i+1) g1(i+1) g0(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) byte 3 r0(i+1) r1(i+1) r2(i+1) r3(i+1) r4(i+1) g0(i+1) g1(i+1) g2(i+1) table 36-4. rgb format in rgb swap mode (continued) table 36-5. decimation factor dec value 0->15 16 17 18 19 ... 124 125 126 127 dec factor x 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.938 table 36-6. decimation and scaler offset values input output 352*288 640*480 800*600 1280*1024 1600*1200 2048*1536 vga 640*480 fna1620324051 qvga 320*240 f1632406480102 cif 352*288 f162633566685 qcif 176*144 f 16 53 66 113 133 170
875 32003e?avr32?05/06 at32ap7000 example: input 1280*1024 output=640*480 hratio = 1280/640 =2 vratio = 1024/480 =2.1333 the decimation factor is 2 so 32/16. figure 36-5. resize examples 36.4.4.2 color space conversion this module converts ycrcb or yuv pixels to rg b color space. clipping is performed to ensure that the samples value do not exceed the allowable range. the conversion matrix is defined below: example of programmable value to convert ycrcb to rgb: an example of programmable value to convert from yuv to rgb: 1280 1024 480 640 32/16 decimation 1280 1024 288 352 56/16 decimation r g b c 0 0 c 1 c 0 c 2 ? c 3 ? c 0 c 4 0 yy off ? c b c boff ? c r c roff ? = r 1.164 y 16 ? () ? 1.596 c r 128 ? () ? + = g 1.164 y 16 ? () 0.813 c r 128 ? () ? ? 0.392 c b 128 ? () ? ? ? = b 1.164 y 16 ? () ? 2.107 c b 128 ? () ? + = ? ? ? ? ?
876 32003e?avr32?05/06 at32ap7000 36.4.4.3 memory interface preview datapath contains a data formatter that converts 8:8:8 pixel to rgb 5:5:5 format compli- ant with 16-bit format of the lcd controller. in general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. example: converting from rgb 8:8:8 to rgb 5:6:5, it discards the three lsbs from the red and blue chan- nels, and two lsbs from the green channel. when grayscale mode is enabled, two memory format are supported. one mode supports 2 pixels per word, and the other mode supports 1 pixel per word. 36.4.4.4 fifo and dma features both preview and codec datapaths contain fifos, asynchronous buffers that are used to safely transfer formatted pixels from pixel clock domain to ahb clock domain. a video arbiter is used to manage fifo thresholds and triggers a relevant dma request through the ahb master inter- face. thus, depending on fifo state, a specified length burst is asserted. regarding ahb master interface, it supports scatter dma mode through linked list operation. this mode of oper- ation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. the destination frame buffers are defined by a series of frame buffer descriptors (fbd). each fbd controls the transfer of one entire frame and then optionally loads a further fbd to switch the dma operation at another frame buffer address. the fbd is defined by a series of two words. the first one defines the current frame buffer address, and the second defines the next fbd memory location. this dm a transfer mode is only available for preview datapath and is configured in the ppfbd register that indicates the memory location of the first fbd. the primary fbd is programmed into the camera interface controller. the data to be transferred described by an fbd requires several burst access. in the example below, the use of 2 ping- pong frame buffers is described. 36.4.4.5 example the first fbd, stored at address 0x30000, defines the location of the first frame buffer. destination address: frame buffer id0 0x02a000 next fbd address: 0x30010 second fbd, stored at address 0x30010, defines the location of the second frame buffer. destination address: frame buffer id1 0x3a000 ry 1.596 v ? + = gy 0.394 u ? ? 0.436 v ? ? = by 2.032 u ? + = ? ? ? ? ? table 36-7. grayscale memory mapping configuration for 12-bit data gs_mode data[31:24] data[23:16] data[15:8] data[7:0] 0 p_0[11:4] p_0[3:0], 0000 p_1[11:4] p_1[3:0], 0000 1 p_0[11:4] p_0[3:0], 0000 0 0
877 32003e?avr32?05/06 at32ap7000 transfer width: 32 bit next fbd address: 0x30000, wrapping to first fbd. using this technique, several frame buffers can be configured through the linked list. figure 36-6 illustrates a typical three frame bu ffer application. frame n is ma pped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. a codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. figure 36-6. three frame buffers application and memory mapping 36.4.5 codec path 36.4.5.1 color space conversion depending on user selection, this module can be bypassed so that input ycrcb stream is directly connected to the format converter module. if the rgb input stream is selected, this mod- ule converts rgb to ycrcb color sp ace with the formulas given below: frame n frame n+1 frame n+2 frame n-1 frame n+3 frame n+4 frame buffer 0 frame buffer 1 frame buffer 3 4:2:2 image full roi isi config space codec request codec done lcd memory space y c r c b c 0 c 1 c 2 c 3 c ? 4 c ? 5 c ? 6 c ? 7 c 8 r g b y off cr off cb off + =
878 32003e?avr32?05/06 at32ap7000 an example of coefficients are given below: 36.4.5.2 memory interface dedicated fifo are used to support packed memory mapping. ycrcb pixel components are sent in a single 32-bit word in a contiguous space (packed). data is stored in the order of natural scan lines. planar mode is not supported. 36.4.5.3 dma features unlike preview datapath, codec datapath dma mode does not support linked list operation. only the codec_dma_addr register is used to configure the frame buffer base address. y 0.257 r ? 0.504 g 0.098 b 16 + ? + ? + = c r 0.439 r ? 0.368 g ? ? 0.071 b 128 + ? ? = c b 0.148 r ? ? 0.291 g 0.439 b 128 + ? + ? ? = ? ? ? ? ?
879 32003e?avr32?05/06 at32ap7000 36.5 image sensor interface (isi) user interface table 36-8. isi registers offset register name register access reset value 0x00 isi control 1 register cr1 read/write 0x00000002 0x04 isi control 2 register cr2 read/write 0x00000000 0x08 isi status register sr read 0x00000000 0x0c isi interrupt enable register ier write 0x00000000 0x10 isi interrupt disable register idr write 0x00000000 0x14 isi interrupt mask register imr read 0x00000000 0x18 reserved - - - 0x1c reserved - - - 0x20 isi preview size register psize read/write 0x00000000 0x24 isi preview decimation factor register pdecf read/write 0x00000010 0x28 isi preview primary fbd register ppfbd read/write 0x00000000 0x2c isi codec dma base address register cdba read/write 0x00000000 0x30 isi csc ycrcb to rgb set 0 register y2r_set0 read/write 0x6832cc95 0x34 isi csc ycrcb to rgb set 1 register y2r_set1 read/write 0x00007102 0x38 isi csc rgb to ycrcb set 0 register r2y_set0 read/write 0x01324145 0x3c isi csc rgb to ycrcb set 1 register r2y_set1 read/write 0x01245e38 0x40 isi csc rgb to ycrcb set 2 register r2y_set2 read/write 0x01384a4b 0x44-0xfc reserved ? ? ?
880 32003e?avr32?05/06 at32ap7000 36.5.1 isi control 1 register register name: cr1 access type: read/write reset value: 0x00000002 ? rst: image sensor interface reset 0: no action 1: resets the image sensor interface. ? dis: image sensor disable: 0: enable the image sensor interface. 1: finish capturing the current frame and then shut down the module. ? hsync_pol: horizontal synchronization polarity 0: hsync active high 1: hsync active low ? vsync_pol: vertical synchronization polarity 0: vsync active high 1: vsync active low ? pixclk_pol: pixel clock polarity 0: data is sampled on rising edge of pixel clock 1: data is sampled on fa lling edge of pixel clock ? emb_sync: embedded synchronization 0: synchronization by hsync, vsync 1: synchronization by embedded synchronization sequence sav/eav ? crc_sync: embedded synchronization 0: no crc correction is performed on embedded synchronization 1: crc correction is performed. if the correction is not possib le, the current frame is disc arded and the crc_err is set in the status register. ? frate: frame rate [0..7] 0: all the frames are captured, else one frame every frate+1 is captured. 31 30 29 28 27 26 25 24 sfd 23 22 21 20 19 18 17 16 sld 15 14 13 12 11 10 9 8 codec_en thmask full - frate 76543210 crc_sync emb_sync - pixclk_pol vsync_pol hsync_pol dis rst
881 32003e?avr32?05/06 at32ap7000 ? full: full mode is allowed 1: both codec and preview datapaths are working simultaneously ? thmask: threshold mask 0: 4, 8 and 16 ahb bursts are allowed 1: 8 and 16 ahb bursts are allowed 2: only 16 ahb bursts are allowed ? codec_en: enable the codec path enable bit this bit always read as zero 0: the codec path is disabled 1: the codec path is enabled and the next frame is captured ? sld: start of line delay sld pixel clock periods to wait before the beginning of a line. ? sfd: start of frame delay sfd lines are skipped at the beginning of the frame.
882 32003e?avr32?05/06 at32ap7000 36.5.2 isi control 2 register register name: cr2 access type: read/write reset value: 0x0 ? im_vsize: vertical size of the image sensor [0..2047] vertical size = im_vsize + 1 ?gs_mode 0: 2 pixels per word 1: 1 pixel per word ? rgb_mode: rgb input mode 0: rgb 8:8:8 24 bits 1: rgb 5:6:5 16 bits ? grayscale 0: grayscale mode is disabled 1: input image is assumed to be grayscale coded ?rgb_swap 0: d7 -> r7 1: d0 -> r7 the rgb_swap has no effect when the grayscale mode is enabled. ? col_space: color space for the image data 0: ycbcr 1: rgb ? im_hsize: horizontal size of the image sensor [0..2047] horizontal size = im_hsize + 1 31 30 29 28 27 26 25 24 rgb_cfg ycc_swap - im_hsize 23 22 21 20 19 18 17 16 im_hsize 15 14 13 12 11 10 9 8 col_space rgb_swap grayscale rgb_mode gs_mode im_vsize 76543210 im_vsize
883 32003e?avr32?05/06 at32ap7000 ? ycc_swap: defines the ycc image data ? rgb_cfg: defines rgb pattern when rgb_mode is set to 1 if rgb_mode is set to rgb 8:8:8, th en rgb_cfg = 0 implies rgb color sequen ce, else it implies bgr color sequence. ycc_swap byte 0 byte 1 byte 2 byte 3 00: default cb(i) y(i) cr(i) y(i+1) 01: mode1 cr(i) y(i) cb(i) y(i+1) 10: mode2 y(i) cb(i) y(i+1) cr(i) 11: mode3 y(i) cr(i) y(i+1) cb(i) rgb_cfg byte 0 byte 1 byte 2 byte 3 00: default r/g(msb) g(lsb)/b r/g(msb) g(lsb)/b 01: mode1 b/g(msb) g(lsb)/r b/g(msb) g(lsb)/r 10: mode2 g(lsb)/r b/g (msb) g(lsb)/r b/g(msb) 11: mode3 g(lsb)/b r/g(msb) g(lsb)/b r/g(msb)
884 32003e?avr32?05/06 at32ap7000 36.5.3 isi status register register name: sr access type: read reset value: 0x0 ? sof: start of frame 0: no start of frame has been detected. 1: a start of frame has been detected. ? dis: image sensor interface disable 0: the image sensor interface is enabled. 1: the image sensor in terface is disabled an d stops capturing data. the dma cont roller and the core can still read the fifos. ? softrst: software reset 0: software reset not asserted or not completed 1: software reset has completed successfully ? cdc_stat: codec request 0: codec request has been asserted 1: codec request has been serviced ? crc_err: crc synchronization error 0: no crc error in the embedd ed synchronization frame (sav/eav) 1: the crc_sync is enabled in the control register and an error has been detected and not corrected. the frame is dis- carded and the isi waits for a new one. ? fo_c_ovf: fifo codec overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the codec path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. ? fo_p_ovf: fifo preview overflow 0: no overflow 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_ovf crc_err cdc_stat softrst dis sof
885 32003e?avr32?05/06 at32ap7000 1: an overrun condition has occurred in input fifo on the preview path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. ? fo_p_emp 0:the dma has not finished transferring all the contents of the preview fifo. 1:the dma has finished transferring all the contents of the preview fifo. ?fo_c_emp 0: the dma has not finished transferring all the contents of the codec fifo. 1: the dma has finished transferring all the contents of the codec fifo. ? fr_ovr: frame rate overrun 0: no frame overrun. 1: frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing fifos.
886 32003e?avr32?05/06 at32ap7000 36.5.4 interrupt enable register register name: ier access type: write reset value: 0x0 ? sof: start of frame 1: enables the start of frame interrupt. ? dis: image sensor interface disable 1: enables the dis interrupt. ? softrst: soft reset 1: enables the soft reset completion interrupt. ? crc_err: crc synchronization error 1: enables the crc_sync interrupt. ? fo_c_ovf: fifo codec overflow 1: enables the codec fifo overflow interrupt. ? fo_p_ovf: fifo preview overflow 1: enables the preview fifo overflow interrupt. ? fo_p_emp 1: enables the preview fifo empty interrupt. ?fo_c_emp 1: enables the codec fifo empty interrupt. ? fr_ovr: frame overrun 1: enables the frame overrun interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
887 32003e?avr32?05/06 at32ap7000 36.5.5 isi interrupt disable register register name: idr access type: write reset value: 0x0 ? sof: start of frame 1: disables the start of frame interrupt. ? dis: image sensor interface disable 1: disables the dis interrupt. ?softrst 1: disables the soft reset completion interrupt. ? crc_err: crc synchronization error 1: disables the crc_sync interrupt. ? fo_c_ovf: fifo codec overflow 1: disables the codec fifo overflow interrupt. ? fo_p_ovf: fifo preview overflow 1: disables the preview fifo overflow interrupt. ? fo_p_emp 1: disables the preview fifo empty interrupt. ?fo_c_emp 1: disables the codec fifo empty interrupt. ?fr_ovr 1: disables frame overrun interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
888 32003e?avr32?05/06 at32ap7000 36.5.6 isi interrupt mask register register name: imr access type: read reset value: 0x0 ? sof: start of frame 0: the start of frame interrupt is disabled. 1: the start of frame interrupt is enabled. ? dis: image sensor interface disable 0: the dis interrupt is disabled. 1: the dis interrupt is enabled. ?softrst 0: the soft reset completion interrupt is enabled. 1: the soft reset completion interrupt is disabled. ? crc_err: crc synchronization error 0: the crc_sync interrupt is disabled. 1: the crc_sync interrupt is enabled. ? fo_c_ovf: fifo codec overflow 0: the codec fifo overflow interrupt is disabled. 1: the codec fifo overflow interrupt is enabled. ? fo_p_ovf: fifo preview overflow 0: the preview fifo overflow interrupt is disabled. 1: the preview fifo overflow interrupt is enabled. ? fo_p_emp 0: the preview fifo empty interrupt is disabled. 1: the preview fifo empty interrupt is enabled. ?fo_c_emp 0: the codec fifo empty interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????fr_ovrfo_c_emp 76543210 fo_p_emp fo_p_ovf fo_c_o vf crc_err ? softrst dis sof
889 32003e?avr32?05/06 at32ap7000 1: the codec fifo empty interrupt is enabled. ? fr_ovr: frame rate overrun 0: the frame overrun interrupt is disabled. 1: the frame overrun interrupt is enabled.
890 32003e?avr32?05/06 at32ap7000 36.5.7 isi preview size register register name: psize access type: read/write reset value: 0x0 ? prev_vsize: vertical size for the preview path vertical preview size = prev_vsize + 1 (480 max) ? prev_hsize: horizontal size for the preview path horizontal preview size = prev_hsize + 1 (640 max) 31 30 29 28 27 26 25 24 ?????? prev_hsize 23 22 21 20 19 18 17 16 prev_hsize 15 14 13 12 11 10 9 8 ?????? prev_vsize 76543210 prev_vsize
891 32003e?avr32?05/06 at32ap7000 36.5.8 isi preview decimation factor register register name: pdecf access type: read/write reset value: 0x00000010 ? dec_factor: decimation factor dec_factor is 8-bit width, range is from 16 to 255. values from 0 to 16 do not perform any decimation. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dec_factor
892 32003e?avr32?05/06 at32ap7000 36.5.9 isi preview primary fbd register register name: ppfbd access type: read/write reset value: 0x0 ? prev_fbd_addr: base address for preview frame buffer descriptor written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. forced to word alignement, ie the 2 lowest bits always read zero. 31 30 29 28 27 26 25 24 prev_fbd_addr 23 22 21 20 19 18 17 16 prev_fbd_addr 15 14 13 12 11 10 9 8 prev_fbd_addr 76543210 prev_fbd_addr
893 32003e?avr32?05/06 at32ap7000 36.5.10 isi codec dma base address register register name: cdba access type: read/write reset value: 0x0 ? codec_dma_addr: base address for codec dma this register contains codec datapath start address of buffer location. forced to word alignement, ie the 2 lowest bits always read zero. 31 30 29 28 27 26 25 24 codec_dma_addr 23 22 21 20 19 18 17 16 codec_dma_addr 15 14 13 12 11 10 9 8 codec_dma_addr 76543210 codec_dma_addr
894 32003e?avr32?05/06 at32ap7000 36.5.11 isi color space conversion ycrcb to rgb set 0 register register name: y2r_set0 access type: read/write reset value: 0x6832cc95 ? c3 : color space conversion matrix coefficient c3 c3 element, default step is 1/128, ranges from 0 to 255/128 ? c2 : color space conversion matrix coefficient c2 c2 element, default step is 1/128, ranges from 0 to 255/128 ? c1 : color space conversion matrix coefficient c1 c1 element, default step is 1/128, ranges from 0 to 255/128 ? c0 : color space conversion matrix coefficient c0 c0 element, default step is 1/128, ranges from 0 to 255/128 31 30 29 28 27 26 25 24 c3 23 22 21 20 19 18 17 16 c2 15 14 13 12 11 10 9 8 c1 76543210 c0
895 32003e?avr32?05/06 at32ap7000 36.5.12 isi color space conversion ycrcb to rgb set 1 register register name: y2r_set1 access type: read/write reset value: 0x00007102 ? c4: color space conversion matrix coefficient c4 c4 element default step is 1/128, ranges from 0 to 512/128 ? yoff: color space conversion luminance default offset 0: no offset 1: offset = 128 ? croff: color space conversion red chrominance default offset 0: no offset 1: offset = 16 ? cboff: color space conversion blue chrominance default offset 0: no offset 1: offset = 16 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? cboff croff yoff ? ? ? c4 c4
896 32003e?avr32?05/06 at32ap7000 36.5.13 isi color space conversion rgb to ycrcb set 0 register register name: r2y_set0 access type: read/write reset value: 0x01324145 ? c0: color space conversion matrix coefficient c0 c0 element default step is 1/256, from 0 to 127/256 ? c1: color space conversion matrix coefficient c1 c1 element default step is 1/128, from 0 to 127/128 ? c2: color space conversion matrix coefficient c2 c2 element default step is 1/512, from 0 to 127/512 ? roff: color space conversion red component offset 0: no offset 1: offset = 16 31 30 29 28 27 26 25 24 ???????roff 23 22 21 20 19 18 17 16 -c2 15 14 13 12 11 10 9 8 -c1 76543210 -c0
897 32003e?avr32?05/06 at32ap7000 36.5.14 isi color space conversion rgb to ycrcb set 1 register register name: r2y_set1 access type: read/write reset value: 0x01245e38 ? c3: color space conversion matrix coefficient c3 c0 element default step is 1/128, ranges from 0 to 127/128 ? c4: color space conversion matrix coefficient c4 c1 element default step is 1/256, ranges from 0 to 127/256 ? c5: color space conversion matrix coefficient c5 c1 element default step is 1/512, ranges from 0 to 127/512 ? goff: color space conversion green component offset 0: no offset 1: offset = 128 31 30 29 28 27 26 25 24 ???????goff 23 22 21 20 19 18 17 16 -c5 15 14 13 12 11 10 9 8 -c4 76543210 -c3
898 32003e?avr32?05/06 at32ap7000 36.5.15 isi color space conversion rgb to ycrcb set 2 register register name: r2y_set2 access type: read/write reset value: 0x01384a4b ? c6: color space conversion matrix coefficient c6 c6 element default step is 1/512, ranges from 0 to 127/512 ? c7: color space conversion matrix coefficient c7 c7 element default step is 1/256, ranges from 0 to 127/256 ? c8: color space conversion matrix coefficient c8 c8 element default step is 1/128, ranges from 0 to 127/128 ? boff: color space conversion blue component offset 0: no offset 1: offset = 128 31 30 29 28 27 26 25 24 ???????boff 23 22 21 20 19 18 17 16 -c8 15 14 13 12 11 10 9 8 -c7 76543210 -c6
899 32003e?avr32?05/06 at32ap7000 37. debug and test rev: 1.0.0 37.1 features ? ieee1149.1 compliant jtag and boundary scan ? direct memory access and programming capabilities through jtag interface ? extensive on-chip debug features in compliance with ieee-isto 5001-2003 (nexus 2.0) class 3 ? auxiliary port for high-speed trace information ? hardware support for 6 program and 2 data breakpoints ? unlimited number of softw are breakpoints supported ? advanced program, data, ownership, and watchpoint trace supported 37.2 jtag interface access to debug and test features is provided through a ieee1149.1 co mpliant jtag interface, using the pins shown in table 37-1 on page 899 . the test and programming technical refer- ence manual details operation of the jtag and the various commands, and only a brief overview follows. the jtag is a synchronous, serial protocol, which allows several devices on a circuit board to be accessed through a common jtag port. the clock signal tck and control signal tms is common to all devices, while the data output tdo is chained to the data input tdi of the next device in the jtag chain, effectively fo rming one long scan chain. devices are addressed through their position in the jtag chain. each jtag device contains a tap controller, which can be navigated through the tms pin. the state of the tap controller determines whether the serial data on tdi is a jtag instruction or jtag data. a number of serial data registers can be selected according to which jtag instruc- tion is loaded. the avr32 jtag has a 5-bit instruction register, which selects data registers of varying length. the implemented set of jtag instructio ns provides the following capabilities: ? ieee1149.1 compliant boundary-scan for testing interconnections between devices on a pcb. ? internal and external memory programming ? access to on-chip debug mechanisms ? access to production test mechanisms production test specific features are described only in the test and programming technical ref- erence manual. other features are additionally introduced below. table 37-1. jtag pins pin direction description trst_n input asynchronous reset for the tap controller and jtag registers tck input test clock. data is driven on falling edge, sampled on rising edge. tms input test mode select tdi input test data in tdo output test data out
900 32003e?avr32?05/06 at32ap7000 figure 37-1. avr32 jtag connections 37.3 public jtag instructions the following public (standard-defined) jtag instructions are provided: ?idcode ? sample_preload ? extest ?intest ? runbist ?clamp ? bypass the idcode is the default instruction loaded into the jtag on power-up or after a jtag reset. this selects the 32-bit jtag idcode register, unique to eac h jtag device. for at32ap7000 avr32 device jtag data registers tap controller tck tms tdi tdo instruction register id register by- pass reset register memory access boundary scan chain cpu internal memory caches ocd registers external bus interface pins and analog blocks instruction register scan enable data register scan enable nexus access jtag tap trst_n boundary scan enable jtag device jtag device jtag master trst_n tck tms tdi tdo tdi tdo external memory ahb
901 32003e?avr32?05/06 at32ap7000 this code is 0xr1e8203f, where r is the revisi on number of the device: rev a = 0x1, b = 0x2, etc. bypass selects the 1-bit bypass regi ster as data register. device s in a jtag chain should nor- mally be placed in bypass when not be ing addressed by the jtag master. the other instructions are used by boundary-scan, which allows testing pcb interconnections by scanning known data to the device pins, or samplin g data driven from other circuits on the pcb. for operation of these instructions, please see the test and programming technical reference manual. 37.4 memory programming the memory_access jtag instruction gives the user access to the ahb bus through the jtag interface. the physical address and the direction bit (read/write) is scanned into the jtag, followed by scanning out the read data or scanning in the write data, depending on the direction of the transfer. any physical memory address can be read or written, allowing internal memories to be written in the same way as when accessed by the cpu. similarly, external memories can be accessed thro ugh the external bus interface (ebi). a polling mechanism pro- vides the jtag master with status information, indicating when the memory operation is complete. the memory_block_access command allows fo r a burst mode memory access through jtag. this command automatically repeats a previous memory_access command, with automatic incrementation of the address. thus only data needs to be scanned in or out, giving negligible protocol overhead on the jtag interface. the jtag master can use the crc check feature described in section 37.5.1.6 on page 904 to automatically calculate the crc-32 value of the programmed memory contents, to ensure that no transmission or programming errors have occurred. when loading a new program to memory, t he cpu should be kept reset by the avr_reset jtag command. if the cpu executes a partially loaded program, unpredictable results may occur, and the program may be corrupted. 37.5 debugging debugging on the at32ap7000 is facilitated by a powerful on -chip debug (ocd) system. the user accesses this through an external debug tool which connects to the jtag port and the aux- iliary (aux) port. the aux port is primarily used for trace functi ons, and a jtag-based debugger is sufficient for basic debugging. the debug system is based on the nexus 2.0 standard, class 3, which includes: ? basic run-time control ? program breakpoints ? data breakpoints ?program trace ? ownership trace ? data trace ? run-time direct memory access in addition to the mandatory nexus debug features, the at32ap7000 implements several useful ocd features, such as:
902 32003e?avr32?05/06 at32ap7000 ? debug communication channel between cpu and jtag ? run-time pc monitoring ? crc checking ? nanotrace ? software quality analysis support the ocd features are controlled by ocd regist ers, which can be accessed by jtag when the nexus_access jtag instruction is loaded. the cpu can also access ocd registers directly using mtdr/mfdr instructions in any privileged mode. the ocd registers are implemented based on the recommendations in the nexus 2.0 standard, and are detailed in the ocd technical ref- erence manual. figure 37-2. on-chip debug block diagram 37.5.1 jtag-based debug features a debugger can control all ocd features by writing ocd registers over the jtag interface. many of these do not depend on output on the aux port, allowing a jtag-based debugger to be used. on-chip debug jtag debug pc debug instruction cpu breakpoints program trace data trace ownership trace watchpoints transmit queue aux jtag memory nanotrace module service access bus memory interface data cache
903 32003e?avr32?05/06 at32ap7000 a jtag-based debugger should connect to the device through a standard 10-pin idc connector as described in the ocd technical reference manual. figure 37-3. jtag-based debugger 37.5.1.1 debug communication channel the debug communication channel (d cc) consists of a pair ocd registers with associated handshake logic, accessible to both cpu an d jtag. the registers can be used to exchange data between the cpu and the jtag master, both runtime as well as in debug mode. 37.5.1.2 breakpoints one of the most fundamental debug features is the abilit y to halt the cpu, to examine registers and the state of the system. this is accomplish ed by breakpoints, of which many types are available: ? unconditional breakpoints halt the cpu immediately. breakpoints are set by writing the ocd registers directly via jtag. ? program breakpoints halt the cpu when a specific address in the program is executed. ? data breakpoints halt the cpu when a specific memory address is read or written, allowing variables to be watched. ? software breakpoints halt the cpu when the breakpoint instruction is executed. avr32 jtag-based debug tool pc jtag low speed 10-pin idc
904 32003e?avr32?05/06 at32ap7000 when a breakpoint triggers, the cpu enters debug mode, and the d bit in the status register is set. this is a privileged mode with dedicated return address and return status registers. all privi- leged instructions are permitted. debug mode can be entered as either ocd mode, running instructions from jtag, or monitor mode, running instructions from program memory. 37.5.1.3 ocd mode when a breakpoint triggers, the cpu enters ocd mode, and instructions are fetched from the debug instruction ocd register. each time this register is written by jtag, the instruction is executed, allowing the jtag to execute cpu instructions directly. the jtag master can e.g. read out the register file by issuing mtdr instructions to the cpu, writing each register to the debug communication channel ocd registers. 37.5.1.4 monitor mode since the ocd registers are directly accessible by the cpu, it is possible to build a software- based debugger that runs on the cpu itself. setting the monitor mode bit in the development control register causes the cpu to enter monitor mode instead of ocd mode when a breakpoint triggers. monitor mode is similar to ocd mode, except that instructions are fetched from the debug exception vector in regular program memory, instead of issued by jtag. 37.5.1.5 direct memory access direct memory access can be accomplished as described above using the memory_access jtag instruction. it is not ne cessary to halt the cpu when using this mechanism, so the memo- ries can be examined on-the-fly without disturbing the program. it is also possible to access memory by using ocd registers, as described in the nexus standard. 37.5.1.6 cyclic redundancy check (crc) the memory access ocd registers can additionally be used to automatically calculate the crc of a block of data in memory. the ocd will then read out each word in the specified memory block and report the crc32-value in an ocd register. 37.5.1.7 nanotrace nanotrace is an avr32-specific feature, in which trace data is output to memory instead of the aux port. this allows the trace data to be extracted by jtag memory_access, enabling trace features for jtag-based debuggers. the user must write ocd registers to configure the address and size of the memory block to be us ed for nanotrace. the nanotrace buffer can be anywhere in the physical address range, including internal and external ram, through the ebi. this area may not be used by the application running on the cpu. the nanotrace access error protection mechanism can trigger a reset or br eakpoint if the application erroneously accesses the nanotrace buffer. 37.5.1.8 program counter monitoring normally, the cpu would need to be halted for a jtag-based debugger to examine the current pc value. however, the at32ap7000 also proves a debug program counter ocd register, where the debugger can continuously read the current pc without affecting the cpu. this allows the debugger to generate a simple statistic of the time spent in various areas of the code, easing code optimization.
905 32003e?avr32?05/06 at32ap7000 37.5.2 aux-based debug features utilizing the auxiliary (aux) port gives a ccess to a wide range of advanced debug features. of prime importance are the trace features, which allow an external debugger to receive continuous information on the program execution in the cpu. additionally, event in and event out pins allow external events to be correlated with the program flow. the aux port contains a number of pins, as shown in table 37-2 . these are multiplexed with pio lines, and must explicitly be enabled by writing ocd registers before the debug session starts. the aux port is mapped to two different locations, selectable by ocd registers, minimiz- ing the chance that the aux port will nee d to be shared wit h an application. debug tools utilizing the aux port should connec t to the device throug h a nexus-compliant mic- tor-38 connector, as described in the ocd technical reference manual. this connector includes the jtag signals and the reset_n pin, giving full access to the programming and debug features in the device. table 37-2. auxiliary port signals signal direction description mcko output trace data output clock mdo[5:0] output trace data output mseo[1:0] output trace frame control evti_n input event in evto_n output event out
906 32003e?avr32?05/06 at32ap7000 figure 37-4. aux+jtag based debugger 37.5.2.1 trace operation trace features are enabled by writing ocd registers by jtag. the ocd extracts the trace infor- mation from the cpu, compresses this information and formats it into variable-length messages according to the nexus standard. the messages are buffered in a 16-frame transmit queue, and are output on the aux port one frame at a time. the trace features can be configured to be very selective, to reduce the bandwidth on the aux port. in case the transmit queue overflows, er ror messages are produced to indicate loss of data. the transmit queue module can optionally be configured to halt the cpu when an overflow occurs, to prevent the loss of messages, at the expense of longer run-time for the program. 37.5.2.2 program trace program trace allows the debugger to continuously monitor the program execution in the cpu. program trace messages are generated for every branch in the program, and contains com- pressed information, which allows the debugger to correlate the message with the source code to identify the branch instruction and target address. avr32 aux+jtag debug tool pc jtag low speed aux high speed mictor38 trace buffer
907 32003e?avr32?05/06 at32ap7000 37.5.2.3 data trace data trace outputs a message every time a specific location is read or written. the message contains information about the type (read/write) and size of the access, as well as the address and data of the accessed location. the at32ap7000 contains two data trace channels, each of which are controlled by a pair of ocd registers which determine the range of addresses (or sin- gle address) which should produce data trace messages. 37.5.2.4 ownership trace program and data trace operate on virtual addresses. in cases where an operating system runs several processes in overlapping virtual memory segments, the ownership trace feature can be used to identify the process switch. when the os activates a process, it will write the process id number to an ocd register, which produces an ownership trace message, allowing the debug- ger to switch context for the subsequent progra m and data trace messages. as the use of this feature depends on the software running on the cpu, it can also be used to extract other types of information from the system. 37.5.2.5 watchpoint messages the breakpoint modules normally used to generate program and data breakpoints can also be used to generate watchpoint messages, allowing a debugger to monitor program and data events without halting the cpu. watchpoints can be enabled independently of breakpoints, so a breakpoint module can optionally halt the cpu w hen the trigger condition occurs. data trace modules can also be configured to produce watc hpoint messages instead of regular data trace messages. 37.5.2.6 event in and event out pins the aux port also contains an event in pin (evti_n) and an event out pin (evto_n). evti_n can be used to trigger a breakpoint when an external event occurs. it can also be used to trigger specific program and data trace synchronization messages, allowing an external event to be correlated to the program flow. when the cpu enters debug mode, a debug status message is transmitted on the trace port. all trace messages can be timestamped when they are received by the debug tool. however, due to the latency of the trans mit queue buffering, the timest amp will not be 100% accurate. to improve this, evto_n can toggle every time a message is inserted into the transmit queue, allowing trace messages to be timestamped prec isely. evto_n can also toggle when a break- point module triggers, or when the cpu enters debug mode, for any reason. this can be used to measure precisely when the respective internal event occurs. 37.5.2.7 software quality analysis (sqa) software quality analysis (sqa) deals with two important issues regarding embedded software development. code coverage involves identifying untested parts of the embedded code, to improve test procedures and thus the quality of the released software. performance analysis allows the developer to precisely quantify the time spent in various parts of the code, allowing bottlenecks to be identified and optimized. program trace must be used to accomplish these tasks without instrumenting (altering) the code to be examined. however, traditional program trace cannot reconstruct the current pc value without correlating the trace information with the source code, which cannot be done on-the-fly.
908 32003e?avr32?05/06 at32ap7000 this limits program trace to a relatively short time segment, determined by the size of the trace buffer in the debug tool. the ocd system in at32ap7000 extends program trace with sqa capabilities, allowing the debug tool to reconstruct the pc value on-the-f ly. code coverage and performance analysis can thus be reported for an unlimited execution sequence.
909 32003e?avr32?05/06 at32ap7000 38. boot sequence this chapter summarizes the boot sequence of the avr32ap7000. the behaviour after power- up is controlled by the power manage r. for specific details, refer to section 11. ?power man- ager? on page 96 . 38.1 starting of clocks after power-up, the device will be held in a reset state by the power-on reset circuitry, until the power has stabilized throughout the device. once the power has stabilized, the device will use the xin0 pin as clock source. xin0 can be connect ed either to an external clock, or a crystal. the oscen_n pin is connected either to vdd or gnd to inform the power manager on how the xin0 pin is connected. if xin0 receives a signal from a crystal, dedicated circuitry in the power manager keeps the part in a reset state until the oscillator co nnected to xin0 has settled. if xin0 receives an external clock, no such settling delay is applied. on system start-up, the plls are disabled. all clocks to all modules are running. no clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the xin0 clock. 38.2 fetching of initial instructions after reset has been released, the avr32ap cpu starts fetching instructions from the reset address, which is 0xa000_0000. this address lies in the p2 segment, which is non-translated, non-cacheable, and permanently mapped to the physical address range 0x0000_0000 to 0x2000_0000. this means that the instruction being fetched from virtual address 0xa000_0000 is being fetched from physical address 0x0000_0000. physical address 0x0000_0000 is mapped to ebi sram cs0. this is the external memory the device boots from. the code read from the sram cs0 memory is free to configure the system to use for example the plls, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.
910 32003e?avr32?05/06 at32ap7000 39. electrical characteristics - tbd 39.1 absolute maximum ratings 39.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. table 39-1. absolute maximum ratings* operating temperature (industrial)............ -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature ............................... -60c to +150c voltage on input pins with respect to ground .............................................. tbd maximum operating voltage (vddcore, vddosc, vddpll and vddusb) ..... 1.95v maximum operating voltage (vddio ) ..................................................................... 3.6v total dc output current on all i/o lines ............... tbd ma table 39-2. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 1.65 1.95 v v vddbu dc supply backup 1.65 1.95 v vddosc dc supply oscillator 1.65 1.95 v v vddpll dc supply pll 1.65 1.95 v v vddusb dc supply usb 1.65 1.95 v v vddio dc supply peripheral i/os 3.0 3.6 v v il input low-level voltage -0.3 +0.8 v v ih input high-level voltage 2.0 v vddio +0.3 v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio = v vddiom or v vddiop v vddio -0.4 v i leak input leakage current pullup resistors disabled tbd a c in input capacitance 256-ball cabga package tbd pf r pullup pull-up resistance tbd kohm i o output current tbd ma i sc static current on v vddcore = 1.8v, cpu = 0 hz t a =25c tbd a all inputs driven; reset_n=1 t a =85c tbd
911 32003e?avr32?05/06 at32ap7000 39.3 power consumption ? typical power consumption of plls , slow clock and main oscillator. ? power consumption of power supply in active mode. ? power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 39.3.1 power consumption versus modes the values in table 39-3 and table 39-4 on page 912 are measured values of power consump- tion with operating conditions as follows: ?v ddio = 3.3v ?v ddcore = v ddusb = v ddpll = v ddosc = 1.8v ?t a = 25 c ? there is no consumption on the i/os of the device figure 39-1. measures schematics vddcore vddusb vddpll vddosc amp
912 32003e?avr32?05/06 at32ap7000 these figures represent the power consum ption measured on the power supplies. table 39-3. typical power consumption for different operating modes s mode conditions typical consumption unit active core clock is 133 mhz. ahb clock is 67mhz. apba clock is 33 mhz. apbb clock is 67mhz. all peripheral clocks activated. cpu is executing a recursive fibonacci algorithm. 200 ma low-speed all clocks are 125khz. all peripheral clocks disabled. cpu is accessing cached data. 400 a table 39-4. power consumption by peripheral in active mode peripheral consumption unit pio controller tbd ma usart tbd usb tbd macb tbd smc tbd sdramc tbd ac97 tbd isi tbd audio dac tbd lcdc tbd twi tbd spi tbd mci tbd ssc tbd timer counter channels tbd
913 32003e?avr32?05/06 at32ap7000 39.4 clock characteristics these parameters are given in the following conditions: ?v ddcore = 1.8v ? ambient temperature = 25c
914 32003e?avr32?05/06 at32ap7000 39.4.1 cpu clock characteristics 39.4.2 ahb clock characteristics 39.4.3 apba clock characteristics 39.4.4 apbb clock characteristics 39.4.5 xin clock characteristics note: 1. these characteristics apply only wh en the main oscillator is in bypass mo de (i.e., when moscen = 0 and oscbypass = 1 in the ckgr_mor register.) table 39-5. core clock waveform parameters symbol parameter conditions min max units 1/(t cpcpu ) cpu clock frequency 133 mhz t cpcpu cpu clock period 7.5 ns table 39-6. ahb clock waveform parameters symbol parameter conditions min max units 1/(t cpahb ) ahb clock frequency 67 mhz t cpahb ahb clock period 15 ns table 39-7. apba clock waveform parameters symbol parameter conditions min max units 1/(t cpapba ) apba clock frequency 33 mhz t cpapba apba clock period 30 ns table 39-8. apbb clock waveform parameters symbol parameter conditions min max units 1/(t cpapbb ) apbb clock frequency 67 mhz t cpapbb apbb clock period 15 ns table 39-9. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50.0 mhz t cpxin xin clock period 20.0 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance (1) tbd pf r in xin pulldown resistor (1) tbd k
915 32003e?avr32?05/06 at32ap7000 39.5 crystal oscillat or characteristics the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. 39.5.1 32 khz oscillator characteristics note: 1. r s is the equivalent series resistance, c l is the equivalent load capacitance. 39.5.2 main oscillators characteristics notes: 1. c s is the shunt capacitance 39.5.3 pll characteristics note: 1. startup time depends on pll rc filter. a calculation tool is provided by atmel. see ?pll operation? on page 99. table 39-10. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 hz duty cycle tbd tbd % t st startup time v ddosc = 1.8 v r s = tbd k , c l = tbd pf (1) tbd ms table 39-11. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 10 27 mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) tbd pf c l equivalent load capacitance tbd pf duty cycle tbd tbd tbd % t st startup time tbd ms i osc current consumption active mode @tbd mhz tbd a standby mode @tbd v tbd a table 39-12. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency pm_pll:pllopt = 0b100 80 133 mhz pm_pll:pllopt = 0b110 tbd tbd mhz f in input frequency tbd tbd mhz i pll current consumption active mode tbd ma standby mode tbd a
916 32003e?avr32?05/06 at32ap7000 39.6 usb transceiver characteristics 39.6.1 electrical characteristics 39.6.2 switching characteristics table 39-13. electrical parameters symbol parameter conditions min typ max unit input levels v il low level tbd v v ih high level tbd v v di differential input sensivity |(d+) - (d-)| tbd v v cm differential input common mode range tbd tbd v c in transceiver capacitance capacitance to ground on each line tbd pf i hi-z state data line leakage 0v < v in < 3.3v tbd tbd a r ext recommended external usb series resistor in series with each usb pin with 5% tbd output levels v ol low level output measured with r l of 1.425 k tied to 3.6v tbd tbd v v oh high level output measured with r l of 14.25 k tied to gnd tbd tbd v v crs output signal crossover voltage measure conditions described in figure 39-2 tbd tbd v table 39-14. in low speed symbol parameter conditions min typ max unit t fr transition rise time c load = 400 pf tbd tbd ns t fe transition fall time c load = 400 pf tbd tbd ns t frfm rise/fall time matching c load = 400 pf tbd tbd % table 39-15. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf tbd tbd ns t fe transition fall time c load = 50 pf tbd tbd ns t frfm rise/fall time matching tbd tbd %
917 32003e?avr32?05/06 at32ap7000 figure 39-2. usb data signal rise and fall times 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6 mhz/750khz r ext = 39 ohms c load buffer (b) (a)
918 32003e?avr32?05/06 at32ap7000 39.7 ac characteristics - tbd 39.8 ebi timings - tbd
919 32003e?avr32?05/06 at32ap7000 40. mechanical characteristics - tbd 40.1 thermal considerations 40.1.1 thermal data table 40-1 summarizes the thermal resistance data depending on the package. 40.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ? ja = package thermal resistance, junction-to-ambient (c/w), provided in table 40-4 on page 921 . ? jc = package thermal resistance, junction-to-ca se thermal resistance (c/w), provided in table 40-4 on page 921 . ? heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. ?p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 911 . ?t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a coolin g device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 40-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air cabga256 tbd c/w jc junction-to-case thermal resistance cabga256 tbd t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
920 32003e?avr32?05/06 at32ap7000 40.2 package drawings figure 40-1. 256-balls cabga package drawing a1 a a3 side view b a2 e d top view a1 ball pad corner symbol d e a a1 a2 a3 e 1.00 bsc b 0.46 ref common dimensions (unit of measure = mm) min - - 1.30 0.31 0.29 0.65 nom 17 bsc 17 bsc 1.40 0.36 0.34 0.70 max - - 1.50 0.41 0.39 0.75 note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t a1 ball pad corner e 1.00 ref 1.00 ref e bottom view notes: 1. this drawing is for general information only. refer to jedec drawing mo-205 for proper dimensions, tolerances, datums etc. 2. array as seen from the bottom of the package.
921 32003e?avr32?05/06 at32ap7000 40.3 soldering profile table 40-6 gives the recommended soldering profile from j-std-20. note: it is recommended to apply a soldering temperature higher than 250c. a maximum of three reflow passes is allowed per component. table 40-2. soldering information ball land tbd solder mask opening tbd table 40-3. device and 256-ball cabg a package maximum weight tbd mg table 40-4. 256-ball cabga package characteristics moisture sensitivity level tbd table 40-5. package reference jedec drawing reference tbd jesd97 classification tbd table 40-6. soldering profile profile feature green package average ramp-up rate (217c to peak) tbd preheat temperature 175c 25c tbd temperature maintained above 217c tbd time within 5 c of actual peak temperature tbd peak temperature range tbd ramp-down rate tbd time 25 c to peak temperature tbd
922 32003e?avr32?05/06 at32ap7000 41. ordering information figure 41-1. ordering information ordering code package package type temperature operating range at32ap7000-133cgu cabga256 green industrial (-40 c to 85 c) AT32AP7000-150CGU cabga256 green industrial (-40 c to 85 c)
923 32003e?avr32?05/06 at32ap7000 42. revision history this section refers to the datasheet revision. 42.1 rev. e 05/06 42.2 rev. d 04/06 42.3 rev. c 04/06 1. added ?usb device - high speed (480 mbits/s)? on page 665 . 1. some occurences of ap7000 renamed to at32ap7000. 2. updated ?real time counter? on page 117 . 3. updated ?audio dac - (dac)? on page 480 4. updated ?dc characteristics? on page 910 . 5. updated ?ordering information? on page 922 . 1. initial revision.
924 32003e?avr32?05/06 at32ap7000
i 32003e?avr32?05/06 at32ap7000 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 part description ......... ................ ................. ................ ................. ............ 2 2 blockdiagram ............. ................ ................. ................ ................. ............ 4 2.1 processor and architecture ......................................................................................5 3 package and pinout ................. ................ ................. ................ ............... 8 4 signals description ............ .............. ............... .............. .............. .......... 10 5 power considerations ........ .............. ............... .............. .............. .......... 16 5.1 power supplies ......................................................................................................16 5.2 power supply connections ....................................................................................16 6 i/o line considerations ...... .............. ............... .............. .............. .......... 17 6.1 jtag pins ...............................................................................................................17 6.2 wake_n pin ............ ................. ................ ................ ................ ................ .............17 6.3 reset_n pin .................. ................ ................ ................ ................ ............. ..........17 6.4 evti_n pin .............................................................................................................17 6.5 twi pins .................................................................................................................1 7 6.6 pio pins .................................................................................................................. 17 7 avr32 ap cpu ........... ................ ................. ................ ................. .......... 18 7.1 avr32 architecture ................................................................................................18 7.2 the avr32 ap cpu ..............................................................................................18 7.3 programming model ...............................................................................................24 8 pixel coprocessor (p ico) ............. ................ ................. .............. .......... 27 8.1 features .................................................................................................................2 7 8.2 description .............................................................................................................27 8.3 block diagram ........................................................................................................28 8.4 vector multiplication unit (vmu) .............................................................................29 8.5 input pixel selector ................................................................................................29 8.6 output pixel inserter ...............................................................................................31 8.7 user interface .........................................................................................................33 8.8 pico instructions ....................................................................................................51 8.9 data hazards .........................................................................................................72 9 memories ............... .............. .............. ............... .............. .............. .......... 73
ii 32003e?avr32?05/06 at32ap7000 9.1 embedded memories .............................................................................................73 9.2 physical memory map ............................................................................................73 10 peripherals ............ .............. .............. ............... .............. .............. .......... 75 10.1 peripheral address map .......................................................................................75 10.2 interrupt request signal map ...............................................................................77 10.3 dmac handshake interface map .........................................................................79 10.4 clock connections ...............................................................................................80 10.5 external interrupt pin mapping .............................................................................81 10.6 nexus ocd aux port connections ......................................................................81 10.7 peripheral multiplexing on io lines .......................................................................82 10.8 peripheral overview ..............................................................................................90 11 power manager ................. ................ ............... .............. .............. .......... 96 11.1 features ...............................................................................................................96 11.2 description ...........................................................................................................96 11.3 block diagram ......................................................................................................97 11.4 product dependencies .........................................................................................98 11.5 functional description ..........................................................................................98 11.6 user interface .....................................................................................................109 12 real time counter ... ................ ................ ................. ................ ........... 117 12.1 features .............................................................................................................117 12.2 description .........................................................................................................117 12.3 block diagram ....................................................................................................118 12.4 product dependencies .......................................................................................119 12.5 functional description ........................................................................................120 12.6 user interface .....................................................................................................121 13 interrupt controller ........... .............. .............. .............. .............. ........... 128 13.1 description .........................................................................................................128 13.2 block diagram ....................................................................................................128 13.3 operation ............................................................................................................129 13.4 user interface .....................................................................................................131 14 external interrupts .......... ................ .............. .............. .............. ........... 135 14.1 features .............................................................................................................135 14.2 description .........................................................................................................135 14.3 block diagram ....................................................................................................135
iii 32003e?avr32?05/06 at32ap7000 14.4 product dependencies .......................................................................................136 14.5 functional description ........................................................................................136 14.6 user interface .....................................................................................................138 15 ahb bus matrix (hmatrix) .. ................ ................. ................ ............. 142 15.1 features ............................................................................................................142 15.2 description .........................................................................................................142 15.3 memory mapping ................................................................................................142 15.4 special bus granting mechanism ......................................................................142 15.5 no default master ..............................................................................................143 15.6 last access master ............................................................................................143 15.7 fixed default master ..........................................................................................143 15.8 arbitration ...........................................................................................................143 15.9 ahb generic bus matrix user interface .............................................................146 15.10 bus matrix master configuration registers ......................................................149 15.11 bus matrix slave configuration registers ........................................................150 15.12 bus matrix priority registers a for slaves .......................................................151 15.13 bus matrix priority registers b for slaves .......................................................152 15.14 bus matrix master remap control register .....................................................153 15.15 bus matrix special function registers .............................................................154 16 external bus interface (ebi ) ................ .............. .............. ............ ........ 155 16.1 features .............................................................................................................155 16.2 description .........................................................................................................155 16.3 block diagram ....................................................................................................156 16.4 i/o lines description ..........................................................................................157 16.5 application example ...........................................................................................159 16.6 product dependencies .......................................................................................163 16.7 functional description ........................................................................................163 17 dma controller (dmac) ................. .............. .............. .............. ........... 171 17.1 features .............................................................................................................171 17.2 description .........................................................................................................171 17.3 block diagram ....................................................................................................172 17.4 functional description ........................................................................................172 17.5 memory peripherals ...........................................................................................176 17.6 handshaking interface .......................................................................................176 17.7 dmac transfer types ........................................................................................179
iv 32003e?avr32?05/06 at32ap7000 17.8 programming a channel ....................................................................................183 17.9 disabling a channel prior to transfer completion .............................................204 17.10 dma controller (dmac) user interface ...........................................................205 18 peripheral dma controller (pdc) ................ .............. .............. ........... 240 18.1 features .............................................................................................................240 18.2 description .........................................................................................................240 18.3 block diagram ....................................................................................................241 18.4 functional description ........................................................................................242 18.5 peripheral dma controller (pdc) user interface ..............................................244 19 parallel input/output contro ller (pio) ......... .............. .............. ........... 255 19.1 features .............................................................................................................255 19.2 description .........................................................................................................255 19.3 block diagram ....................................................................................................256 19.4 product dependencies .......................................................................................257 19.5 functional description ........................................................................................258 19.6 i/o lines programming example .......................................................................262 19.7 user interface .....................................................................................................264 20 serial peripheral interface (spi) ................ ................ .............. ........... 292 20.1 features .............................................................................................................292 20.2 description .........................................................................................................292 20.3 block diagram ....................................................................................................293 20.4 application block diagram .................................................................................294 20.5 signal description ..............................................................................................295 20.6 product dependencies .......................................................................................296 20.7 functional description ........................................................................................297 20.8 user interface .....................................................................................................307 21 two-wire interface (twi) .... .............. ............... .............. .............. ........ 321 21.1 features ............................................................................................................321 21.2 description .........................................................................................................321 21.3 block diagram ....................................................................................................321 21.4 application block diagram .................................................................................321 21.5 product dependencies .......................................................................................322 21.6 functional description ........................................................................................323 21.7 twi user interface .............................................................................................328
v 32003e?avr32?05/06 at32ap7000 22 ps/2 module (psif) ........... .............. .............. .............. .............. ........... 339 22.1 features .............................................................................................................339 22.2 description .........................................................................................................339 22.3 product dependencies .......................................................................................339 22.4 the ps/2 protocol ..............................................................................................339 22.5 functional description ........................................................................................341 22.6 user interface .....................................................................................................343 23 synchronous serial controller (ssc) .... ................. ................ ........... 352 23.1 features ............................................................................................................352 23.2 description .........................................................................................................352 23.3 block diagram ....................................................................................................353 23.4 application block diagram .................................................................................353 23.5 pin name list .....................................................................................................354 23.6 product dependencies .......................................................................................354 23.7 functional description ........................................................................................354 23.8 ssc application examples .................................................................................366 23.9 synchronous serial controller (ssc) user interface .........................................368 24 universal synchr onous/asynchronous receiver/t ransmitter (usart) 393 24.1 features .............................................................................................................393 24.2 description .........................................................................................................393 24.3 block diagram ....................................................................................................394 24.4 application block diagram .................................................................................395 24.5 i/o lines description .........................................................................................395 24.6 product dependencies .......................................................................................396 24.7 functional description ........................................................................................397 24.8 usart user interface .......................................................................................427 25 ac97 controller(ac97c) ....... ................ ................. ................ ............. 448 25.1 features ............................................................................................................448 25.2 description .........................................................................................................448 25.3 block diagram ....................................................................................................449 25.4 pin name list .....................................................................................................450 25.5 application block diagram .................................................................................450 25.6 product dependencies .......................................................................................451 25.7 functional description ........................................................................................452
vi 32003e?avr32?05/06 at32ap7000 25.8 ac97 controller (ac97c) user interface ...........................................................463 26 audio dac - (dac) ..... ................ ................. ................ .............. ........... 480 26.1 features .............................................................................................................480 26.2 description .........................................................................................................480 26.3 block diagram ....................................................................................................481 26.4 pin name list .....................................................................................................481 26.5 product dependencies .......................................................................................481 26.6 functional description ........................................................................................482 26.7 audio dac user interface ..................................................................................483 26.8 frequency response .........................................................................................491 27 static memory controller (smc) ........... ................. ................ ............. 492 27.1 features ............................................................................................................492 27.2 description .........................................................................................................492 27.3 block diagram ....................................................................................................493 27.4 i/o lines description ..........................................................................................494 27.5 multiplexed signals ............................................................................................494 27.6 application example ...........................................................................................495 27.7 product dependencies .......................................................................................495 27.8 external memory mapping .................................................................................496 27.9 connection to external devices .........................................................................496 27.10 standard read and write protocols .................................................................500 27.11 automatic wait states ......................................................................................508 27.12 data float wait states .....................................................................................513 27.13 external wait ....................................................................................................517 27.14 slow clock mode ..............................................................................................523 27.15 asynchronous page mode ...............................................................................526 27.16 static memory controller (smc) user interface ...............................................529 28 sdram controller (sdramc) ................ ................. ................ ........... 535 28.1 features .............................................................................................................535 28.2 description .........................................................................................................535 28.3 block diagram ....................................................................................................536 28.4 i/o lines description ..........................................................................................536 28.5 application example ...........................................................................................537 28.6 product dependencies .......................................................................................540 28.7 functional description ........................................................................................542
vii 32003e?avr32?05/06 at32ap7000 28.8 sdram controller user interface ......................................................................549 29 error corrected code (ecc ) controller ...... .............. .............. ........... 562 29.1 features ............................................................................................................562 29.2 description .........................................................................................................562 29.3 block diagram ....................................................................................................562 29.4 functional description ........................................................................................563 29.5 ecc user interface ............................................................................................567 30 multimedia card interface (m ci) ........... ................. ................ ............. 573 30.1 features .............................................................................................................573 30.2 description .........................................................................................................573 30.3 block diagram ....................................................................................................574 30.4 application block diagram .................................................................................575 30.5 pin name list ....................................................................................................575 30.6 product dependencies .......................................................................................576 30.7 bus topology .....................................................................................................576 30.8 multimedia card operations ...............................................................................579 30.9 sd card operations ...........................................................................................585 30.10 user interface ...................................................................................................586 31 ethernet mac 10/100 (macb) .. ............... ................. ................ ........... 602 31.1 features .............................................................................................................602 31.2 description .........................................................................................................602 31.3 block diagram ....................................................................................................603 31.4 functional description ........................................................................................604 31.5 programming interface .......................................................................................616 31.6 ethernet mac 10/100 (macb) user interface ....................................................619 32 usb device - high speed (480 mbits/s) ......... .............. .............. ........ 665 32.1 features .............................................................................................................665 32.2 description .........................................................................................................665 32.3 block diagram ....................................................................................................666 32.4 typical connection .............................................................................................667 32.5 usb v2.0 high speed device introduction ........................................................668 32.6 usb high speed device (udphs) user interface .............................................692 33 timer/counter (tc) ........... .............. .............. .............. .............. ........... 740 33.1 features .............................................................................................................740
viii 32003e?avr32?05/06 at32ap7000 33.2 description .........................................................................................................740 33.3 block diagram ....................................................................................................741 33.4 pin name list .....................................................................................................742 33.5 product dependencies .......................................................................................742 33.6 functional description ........................................................................................742 33.7 timer counter (tc) user interface .....................................................................755 34 pulse width modulation c ontroller (pwm) . .............. .............. ........... 774 34.1 features .............................................................................................................774 34.2 description .........................................................................................................774 34.3 block diagram ....................................................................................................775 34.4 i/o lines description ..........................................................................................775 34.5 product dependencies .......................................................................................776 34.6 functional description ........................................................................................777 34.7 user interface .....................................................................................................785 35 lcd controller (lcdc) .......... ................ ................. ................ ............. 800 35.1 features .............................................................................................................800 35.2 description .........................................................................................................800 35.3 block diagram ....................................................................................................801 35.4 i/o lines description ..........................................................................................802 35.5 product dependencies .......................................................................................802 35.6 functional description ........................................................................................803 35.7 interrupts ............................................................................................................825 35.8 configuration sequence .....................................................................................825 35.9 double-buffer technique ....................................................................................827 35.10 2d memory addressing ....................................................................................827 35.11 general-purpose register ................................................................................829 35.12 register configuration guide ...........................................................................830 35.13 lcd controller (lcdc) user interface .............................................................831 36 image sensor interface (isi) ............. ............... .............. .............. ........ 870 36.1 features .............................................................................................................870 36.2 overview ............................................................................................................870 36.3 block diagram ....................................................................................................871 36.4 functional description ........................................................................................871 36.5 image sensor interface (isi) user interface .......................................................879 37 debug and test ............... ................ .............. .............. .............. ........... 899
ix 32003e?avr32?05/06 at32ap7000 37.1 features .............................................................................................................899 37.2 jtag interface ...................................................................................................899 37.3 public jtag instructions ....................................................................................900 37.4 memory programming ........................................................................................901 37.5 debugging ..........................................................................................................901 38 boot sequence ........... ................ ................. ................ .............. ........... 909 38.1 starting of clocks ................................................................................................909 38.2 fetching of initial instructions .............................................................................909 39 electrical characteristics - tbd ........... ................. ................ ............. 910 39.1 absolute maximum ratings ................................................................................910 39.2 dc characteristics .............................................................................................910 39.3 power consumption ...........................................................................................911 39.4 clock characteristics ..........................................................................................913 39.5 crystal oscillator characteristics ........................................................................915 39.6 usb transceiver characteristics ........................................................................916 39.7 ac characteristics - tbd ...................................................................................918 39.8 ebi timings - tbd ..............................................................................................918 40 mechanical characteristics - tb d .................. .............. .............. ........ 919 40.1 thermal considerations .....................................................................................919 40.2 package drawings .............................................................................................920 40.3 soldering profile .................................................................................................921 41 ordering information .......... .............. ............... .............. .............. ........ 922 42 revision history ....... ................ ................ ................. ................ ........... 923 42.1 rev. e 05/06 .......................................................................................................923 42.2 rev. d 04/06 ......................................................................................................923 42.3 rev. c 04/06 ......................................................................................................923 table of contents.......... ................. ................ ................. ................ ........... i
x 32003e?avr32?05/06 at32ap7000
32003e?avr32?05/06 ? 2006 atmel corporation . all rights reserved. at m e l ? , logo and combinations thereof, everywhere you are ? , avr ? , and others, are regis- tered trademarks or trademarks of atmel corporation or its subsid iaries. other terms and product names may be trademarks of oth ers. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature

▲Up To Search▲

Price & Availability of AT32AP7000-150CGU

	To Download AT32AP7000-150CGU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .